265 lines
8.5 KiB
C
265 lines
8.5 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _DWC_ETH_H_
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#define _DWC_ETH_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ROUND_UP(x, align) (((uint32_t) (x) + (align - 1)) & ~(align - 1))
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#define ETH_BUFFER_ALIGN_SIZE(x) ROUND_UP(x, sizeof(uint32_t))
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#define ETH_ADDR_LEN 6
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#define ETH_TYPE_LEN 2
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#define ETH_CRC_LEN 4
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#define ETH_MAX_LEN 1518
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#define ETH_MIN_LEN 64
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#define ETH_HDR_LEN (ETH_ADDR_LEN*2 + ETH_TYPE_LEN) /* 14 */
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#define ETH_MTU \
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(ETH_MAX_LEN - ETH_CRC_LEN) /* 1514 */
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#define ETH_MIN \
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(ETH_MIN_LEN - ETH_CRC_LEN) /* 60 */
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#define ETH_INVALID_LEN(s) \
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(((s) > (ETH_MAX_LEN - ETH_CRC_LEN)) || ((s) < (ETH_MIN_LEN - ETH_CRC_LEN)))
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#define ETH_BUFFER_SIZE ETH_BUFFER_ALIGN_SIZE(ETH_MAX_LEN)
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#define ETH_MAX_RX_FRAME_CNT 64
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#define ETH_SPEED_10M 10
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#define ETH_SPEED_100M 100
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/* No need to support 1000M for port up-to CPU. */
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#define ETH_SPEED_1000M 1000
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#define ETH_DUPLEX_HALF 0
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#define ETH_DUPLEX_FULL 1
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#define ETH_RX_FLOWCTRL 1
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#define ETH_TX_FLOWCTRL 2
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#define ETH_PHY_MDI 0
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#define ETH_PHY_MDIX 1
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#define ETH_PHY_MDIX_AUTO 2
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#define ETH_DEVICE_UNIT_CNT 1
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#define ETH_FILTER_UNICAST 0x1
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#define ETH_FILTER_MULTICAST 0x2
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#define ETH_FILTER_BROADCAST 0x4
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#define ETH_FILTER_PROMISCUOUS 0x8
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typedef enum eth_segment
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{
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ETH_SEGMENT_FIRST = 1,
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ETH_SEGMENT_LAST = 2,
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ETH_SEGMENT_NORMAL = 4
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}segment_type;
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#define DWC_INT_STATUS_MAC 0x00020000
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#define DWC_INT_STATUS_MTL 0x00010000
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#define DWC_INT_STATUS_DMA 0x000000FF
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#define DWC_DMA_intTxCompleted 0x00000001
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#define DWC_DMA_intTxStopped 0x00000002
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#define DWC_DMA_intTxBufferRunout 0x00000004
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#define DWC_DMA_intRxCompleted 0x00000040
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#define DWC_DMA_intRxBufferRunout 0x00000080
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#define DWC_DMA_intRxStopped 0x00000100
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#define DWC_DMA_intRxWDTTimeout 0x00000200
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//#define DWC_DMA_intRxEarly 0x00000400
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//#define DWC_DMA_intTxEarly 0x00000800
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#define DWC_DMA_intRxEarly 0x00000800
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#define DWC_DMA_intTxEarly 0x00000400
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#define DWC_DMA_intBusError 0x00001000
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#define DWC_DMA_intContextDesError 0x00002000
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#define DWC_DMA_intAbnormalSum 0x00004000
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#define DWC_DMA_intNormalSum 0x00008000
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#define DWC_DMA_intStatusTxDmaBitError 0x00070000
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#define DWC_DMA_intStatusRxDmaBitError 0x00380000
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#define DWC_MTL_intEnableRxOverflow 0x01000000
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#define DWC_MTL_intStatusRxOverflow 0x00010000
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#define DWC_MTL_intEnableAverageBits 0x00000200
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#define DWC_MTL_intEnableTxUnderflow 0x00000100
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#define DWC_MTL_intStatusAverageBits 0x00000002
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#define DWC_MTL_INTStatusTxUnderflow 0x00000001
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#define DWC_ETH_INT_TX_MASK \
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(DWC_DMA_intTxCompleted | DWC_DMA_intTxEarly)
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#define DWC_ETH_INT_RX_MASK \
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(DWC_DMA_intRxEarly | DWC_DMA_intRxBufferRunout | DWC_DMA_intRxCompleted)
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#define DWC_ETH_INT_TRX_MASK (DWC_ETH_INT_TX_MASK | DWC_ETH_INT_RX_MASK)
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#define DWC_ETH_INT_MASK \
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(DWC_ETH_INT_TRX_MASK | DWC_DMA_intAbnormalSum | DWC_DMA_intNormalSum)
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#define DWC_ETH_INT_MMC_MASK \
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(MMCIS_MASK | MMCRXIS_MASK | MMCTXIS_MASK | MMCRXIPIS_MASK)
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/* RDES0 */
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#define DWC_DESC_DESC0(d) \
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(*(volatile uint32_t *)((uint32_t)(d)+(0)))
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/* RDES1 */
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#define DWC_DESC_DESC1(d) \
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(*(volatile uint32_t *)((uint32_t)(d)+(sizeof(uint32_t))))
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/* RDES2 */
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#define DWC_DESC_DESC2(d) \
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(*(volatile uint32_t *)((uint32_t)(d)+(2*sizeof(uint32_t))))
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/* RDES3 */
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#define DWC_DESC_DESC3(d) \
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(*(volatile uint32_t *)((uint32_t)(d)+(3*sizeof(uint32_t))))
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/* RDES4 */
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/* For tx it's a iot_pkt_t*, for rx it's just a pointer of data buffer. */
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#define DWC_DESC_BUFFER(d) \
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(*(volatile uint32_t *)((uint32_t)(d)+(4*sizeof(uint32_t))))
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#define DWC_DESC_DATA_LEN_BITS 0x00003FFF
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#define DWC_DESC_DATA_LEN_OFFSET 0
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#define DWC_DESC_GET_DATA_LEN(p) \
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(((p) & DWC_DESC_DATA_LEN_BITS) >> DWC_DESC_DATA_LEN_OFFSET)
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#define DWC_DESC_DATA_LEN(len) \
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(((len) << DWC_DESC_DATA_LEN_OFFSET) & DWC_DESC_DATA_LEN_BITS)
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#define DWC_DESC_STATUS_OWNER_DMA 0x80000000
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#define DWC_DESC_STATUS_FIRST_SEG 0x20000000
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#define DWC_DESC_STATUS_LAST_SEG 0x10000000
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#define DWC_DESC_STATUS_ERROR_SUM 0x00008000
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#define DWC_DESC_STATUS_CRC_PAD_INS 0x00000000
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#define DWC_DESC_STATUS_CRC_INS 0x04000000
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#define DWC_DESC_STATUS_CRC_REP 0x0C000000
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#define DWC_DESC_STATUS_CTXT 0x40000000
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#define DWC_DESC_STATUS_SA_REP_R1 0x01000000
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#define DWC_DESC_STATUS_INT_ENA 0x40000000
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#define DWC_DESC_STATUS_BUF_2_ENA 0x02000000
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#define DWC_DESC_STATUS_BUF_1_ENA 0x01000000
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#define DWC_DESC_CTRL_INT_ENA 0x80000000
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#define DWC_DESC_CTRL_BUF1_LEN(len) \
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(((len) << DWC_DESC_DATA_LEN_OFFSET) & DWC_DESC_DATA_LEN_BITS)
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#define DWC_RTXQEN_MODE 0x00000002
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#define DWC_RTXPBL 0x00000010
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#define DWC_RTXQ_SIZE_1K 0x00000003
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typedef struct port_statistics
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{
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uint32_t bytes_toltal; /* Toltal bytes of transfered packets */
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uint32_t pk_toltal; /* Toltal packets transfered */
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uint32_t pk_tf_uni; /* Unicast packets transfered */
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uint32_t pk_tf_broad; /* Broadcast packets transfered */
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uint32_t pk_tf_multi; /* Multicast packets transfered */
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uint32_t pk_dp_uni; /* Unicast packets dropped */
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uint32_t pk_dp_broad; /* Broadcast packets dropped */
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uint32_t pk_dp_multi; /* Multicast packets dropped */
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}t_dwc_stat;
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typedef struct port_cfg
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{
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uint8_t enable; /* 1:enable this port. 0:disable this port. */
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uint8_t autonegotiation; /* 1:enable autonegotiation.
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0:disable autonegotiation. */
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uint8_t speed; /* Port speed. Like ETH_SPEED_10M. */
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uint8_t duplex; /* Duplex set. Like ETH_DUPLEX_FULL. */
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uint8_t mdix;
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uint8_t flowctrl;
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uint16_t filter; /* Default to be set as UNICAST|BROADCAST */
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}t_port_cfg;
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typedef struct dwc_dma
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{
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uint32_t des0;
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uint32_t des1;
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uint32_t des2;
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uint32_t des3;
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uint32_t pkt;
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}t_dwc_dma;
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#define DWC_DES_MEB_END_SIZE(type, meb) \
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(((int)(&(((type*)0)->meb))) + sizeof(((type*)0)->meb))
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#define DWC_DES_SKIP \
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((sizeof(t_dwc_dma) - DWC_DES_MEB_END_SIZE(t_dwc_dma, des3)) / sizeof(int))
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typedef struct dma_buf
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{
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void *desc_base;
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void *buf_base;
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t_dwc_dma *desc[ETH_MAX_RX_FRAME_CNT];
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uint32_t dinx;
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uint32_t last_dinx;
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}t_dwc_buf;
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typedef struct multicast_list
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{
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struct multicast_list *next;
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uint8_t addr[ETH_ADDR_LEN];
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}t_dwc_mcast;
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typedef struct dwc_dev
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{
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uint32_t in_use;
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uint8_t unit;
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uint8_t phy_addr;
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uint8_t eth_addr[ETH_ADDR_LEN];
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uint32_t int_status;
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uint32_t int_handle;
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void (*dwc_packet_recv)(struct dwc_dev *pc, uint8_t *p_data, uint32_t len);
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t_port_cfg port_cfg;
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t_dwc_stat statistics;
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t_dwc_buf rxd;
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t_dwc_buf txd;
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t_dwc_mcast *mcast_lst;
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}t_dwc_ctrl;
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t_dwc_ctrl * dwc_eth_open(int unit, void *recv_func);
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int dwc_eth_config(t_dwc_ctrl *p_ctrl, t_port_cfg *p_cfg, uint8_t *addr);
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int dwc_mac_addr_get(t_dwc_ctrl *p_ctrl, uint8_t *addr);
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int dwc_eth_mcast_addr_add(t_dwc_ctrl *p_ctrl, uint8_t addr[]);
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int dwc_eth_start(t_dwc_ctrl *p_ctrl);
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int dwc_eth_restart(t_dwc_ctrl *p_ctrl);
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int dwc_eth_send_frame(t_dwc_ctrl *p_ctrl, iot_pkt_ls* pkt_l);
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int dwc_eth_close(t_dwc_ctrl *p_ctrl);
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uint8_t dwc_eth_get_link_status(t_dwc_ctrl *p_ctrl);
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int dwc_eth_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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