98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef __QSPI_H
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#define __QSPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U)/* 5 s */
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#define SFC_WIP_IS_BUSY_BIT (1<<0)
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/**
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* @brief QSPI Status structures definition
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*/
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typedef enum
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{
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SMC_QSPI_OK = 0x00U,
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SMC_QSPI_ERROR = 0x01U,
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SMC_QSPI_BUSY = 0x02U,
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SMC_QSPI_TIMEOUT = 0x03U,
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SMC_QSPI_NOT_SUPPORTED = 0x04U
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} smc_sts_type_t;
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typedef enum
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{
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MOD_SMC_OP_REV0 = 0x00U,
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MOD_SMC_OP_ERV1 = 0x01U,
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MOD_SMC_OP_TRANS = 0x02U,
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MOD_SMC_OP_REG_WR = 0x03U
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} smc_operation_mode_t;
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typedef enum
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{
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MOD_SMC_READ_SIG = 0x00U,
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MOD_SMC_READ_FAST = 0x01U,
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MOD_SMC_READ_QUAD = 0x02U
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} smc_read_mode_t;
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typedef enum
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{
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SMC_REG_ACCESS = 0x00U,
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SMC_BUF_ACCESS = 0x01U
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} smc_access_type_t;
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/**
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* @brief QSPI Command structure definition
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*/
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typedef struct
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{
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uint8_t smc_dlen; /* spi trans data length, unit is byte */
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uint8_t smc_cmode; /* Operation Mode */
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smc_operation_mode_t smc_mode; /* spi continus mode byte */
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bool_t emc_crypt_mode; /* emc data cryption mode, 0- bypass mode, 1- cryption mode */
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smc_read_mode_t cache_rd_mode; /* read mode */
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bool_t qpi_mode; /* qpi mode en */
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uint8_t cmd; /* Specifies the Instruction to be sent */
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uint32_t addr; /* Specifies the Address to be sent */
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uint32_t pe_wait_time; /* program or erase wait time, unit is clock cycle num */
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uint32_t smc_rd_sts; /* status */
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uint32_t smc_wr_sts; /* status */
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} smc_op_t;
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bool_t is_smc_cmd_busy();
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smc_sts_type_t hal_smc_qspi_start();
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smc_sts_type_t hal_smc_qspi_quad_cfg(uint8_t clk);
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smc_sts_type_t hal_smc_spi_cfg(uint8_t clk);
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smc_sts_type_t hal_smc_qspi_rst_en();
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smc_sts_type_t hal_smc_qspi_rst();
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smc_sts_type_t hal_smc_qspi_command(smc_op_t *cmd, uint32_t timeout);
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smc_sts_type_t hal_smc_qspi_receive(uint8_t *data, uint32_t len, uint8_t is_buf, uint32_t timeout);
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smc_sts_type_t hal_smc_qspi_transmit(uint8_t *data, uint32_t len, uint8_t is_buf, uint32_t timeout);
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smc_sts_type_t hal_smc_disable();
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void hal_smc_clk_div_set(uint8_t div);
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void hal_smc_clk_out(int enable);
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#ifdef __cplusplus
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}
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#endif
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#endif
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