82 lines
2.6 KiB
C
Executable File
82 lines
2.6 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _SPI_H_
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#define _SPI_H_
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#include "gpio_mtx.h"
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#include "iot_spi_api.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef OK
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#define OK (0)
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#define ERROR (-1)
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typedef int STATUS;
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#endif
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#ifndef BIT
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#define BIT(b) (1<<(b))
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#endif
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/* Interrupts masks */
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#define SPI_RXFIFO_FULL INT_RXFIFO_FULL
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#define SPI_RXFIFO_OVFL INT_RXFIFO_OVERFLOW
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#define SPI_RXFIFO_UDFL INT_RXFIFO_UNDERFLOW
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#define SPI_TXFIFO_EMPTY INT_TXFIFO_EMPTY
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#define SPI_TXFIFO_OVFL INT_TXFIFO_OVERFLOW
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#define SPI_DEFAULT_FRAM_SIZE SPI_DFRAME_SIZE_8
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#define SPI_DEFAULT_FRQ DEVICE_SPI_DEFAULT_FREQUENCY
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#define SPI_DEFAULT_RX_THR DEVICE_SPI_DEFAULT_RX_THRESHOULD
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#define SPI_DEFAULT_TX_THR DEVICE_SPI_DEFAULT_TX_THRESHOULD
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#define SPI_DEFAULT_CS_EN DEVICE_SPI_DEFAULT_CS_EN
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#define SPI_INT_MASK (0x3FF)
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typedef struct spi_opr_entity
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{
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int dev_cnt;
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STATUS (*config)(int, spi_cfg*, tm_cfg*, sdma_cfg*);
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STATUS (*reset)(int);
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int (*get)(int);
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STATUS (*put)(int, int);
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STATUS (*set_int_enable)(int, int);
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STATUS (*set_int_disable)(int, int);
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STATUS (*clear_int)(int, int);
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int (*get_int_status)(int);
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int (*get_int_raw_status)(int);
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int (*rx_fifo_empty)(int);
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int (*rx_fifo_frame_rcvd_num)(int);
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int (*tx_fifo_full)(int);
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int (*tx_fifo_frame_rest_num)(int);
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int (*tx_fifo_empty)(int);
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STATUS (*get_sig_info)(int, gpio_sig_info_t *);
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STATUS (*get_dev_by_vec_num)(unsigned int vec_num, int *dev);
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STATUS (*get_vec_num_by_dev)(int dev, unsigned int *vec_num);
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/* return value is invalidity */
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int (*check_dev_invalidity)(int);
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}spi_opr;
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#ifdef INCLUDE_DW_APB_SSI
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extern const spi_opr dw_ssi_ctrl;
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#define SPI_OPR_ENTRY (&dw_ssi_ctrl)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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