146 lines
7.9 KiB
C
146 lines
7.9 KiB
C
#ifndef __MEM_CONFIG_H__
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#define __MEM_CONFIG_H__
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#include "iot_mem_org.h"
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//FLASH SIZE && PSRAM SIZE
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#define MEM_CFG_FLASH_SIZE (0x400000)
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#define MEM_CFG_PSRAM_SIZE (0x0)
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//FLASH LAYOUT
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//0x000000 ~ 0x020000
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#define MEM_CFG_LAYOUT_SBL_OFFSET (0x00000000)
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#define MEM_CFG_LAYOUT_SBL_LENGTH (0xc000) //48k
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#define MEM_CFG_LAYOUT_DD1_OFFSET (0x0000c000)
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#define MEM_CFG_LAYOUT_DD1_LENGTH (0x2000) //8k
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#define MEM_CFG_LAYOUT_DD2_OFFSET (0x0000e000)
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#define MEM_CFG_LAYOUT_DD2_LENGTH (0x2000) //8k
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#define MEM_CFG_LAYOUT_PARAM_OFFSET (0x00010000)
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#define MEM_CFG_LAYOUT_PARAM_LENGTH (0x1000) //4k
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#define MEM_CFG_LAYOUT_OEM_OFFSET (0x00011000)
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#define MEM_CFG_LAYOUT_OEM_LENGTH (0x1000) //4k
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#define MEM_CFG_LAYOUT_PIB1_OFFSET (0x00012000)
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#define MEM_CFG_LAYOUT_PIB1_LENGTH (0x7000) //28k
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#define MEM_CFG_LAYOUT_PIB2_OFFSET (0x00019000)
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#define MEM_CFG_LAYOUT_PIB2_LENGTH (0x7000) //28k
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//0x300000 ~ 0x400000
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#define MEM_CFG_LAYOUT_CUST_CUS_OFFSET (0x00300000)
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#define MEM_CFG_LAYOUT_CUST_CUS_LENGTH (0xdf000) //892k
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#define MEM_CFG_LAYOUT_CUST_PLC_OFFSET (0x003df000)
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#define MEM_CFG_LAYOUT_CUST_PLC_LENGTH (0x1f000) //124k
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#define MEM_CFG_LAYOUT_CALI_CUS_OFFSET (0x003fe000)
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#define MEM_CFG_LAYOUT_CALI_CUS_LENGTH (0x1000) //4k
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#define MEM_CFG_LAYOUT_CALI_PLC_OFFSET (0x003ff000)
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#define MEM_CFG_LAYOUT_CALI_PLC_LENGTH (0x1000) //4k
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//without psram
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#define MEM_CFG_LAYOUT_RUN_CUS_OFFSET (0x00020000)
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#define MEM_CFG_LAYOUT_RUN_CUS_LENGTH (0x40000) //256k
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#define MEM_CFG_LAYOUT_RUN_PLC_OFFSET (0x00060000)
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#define MEM_CFG_LAYOUT_RUN_PLC_LENGTH (0x120000) //1152k
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#define MEM_CFG_LAYOUT_FW1_CUS_OFFSET (0x00180000)
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#define MEM_CFG_LAYOUT_FW1_CUS_LENGTH (0x20000) //128k
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#define MEM_CFG_LAYOUT_FW1_PLC_OFFSET (0x001a0000)
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#define MEM_CFG_LAYOUT_FW1_PLC_LENGTH (0xa0000) //640k
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#define MEM_CFG_LAYOUT_FW2_CUS_OFFSET (0x00240000)
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#define MEM_CFG_LAYOUT_FW2_CUS_LENGTH (0x20000) //128k
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#define MEM_CFG_LAYOUT_FW2_PLC_OFFSET (0x00260000)
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#define MEM_CFG_LAYOUT_FW2_PLC_LENGTH (0xa0000) //640k
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#define MEM_CFG_LAYOUT_LOG1_OFFSET (0x00000000)
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#define MEM_CFG_LAYOUT_LOG1_LENGTH (0x0) //0k
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#define MEM_CFG_LAYOUT_LOG2_OFFSET (0x00000000)
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#define MEM_CFG_LAYOUT_LOG2_LENGTH (0x0) //0k
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#define MEM_CFG_CUS_FLASH_ADDRS (MEM_CFG_CHIP_ICACHE0_SFC_BASE + MEM_CFG_LAYOUT_RUN_CUS_OFFSET)
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#define MEM_CFG_CUS_FLASH_SIZE (MEM_CFG_LAYOUT_RUN_CUS_LENGTH) //256k
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#define MEM_CFG_CUS_DRAM_ADDRS (MEM_CFG_CHIP_DCACHE0_SMC_BASE)
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#define MEM_CFG_CUS_DRAM_SIZE (0x10000) //64k
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#define MEM_CFG_CUS_IRAM_ADDRS (MEM_CFG_CHIP_DCACHE1_SMC_BASE)
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#define MEM_CFG_CUS_IRAM_SIZE (0x8000) //32k
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#define MEM_CFG_PLC_FLASH_ADDRS (MEM_CFG_CHIP_ICACHE1_SFC_BASE + MEM_CFG_LAYOUT_RUN_PLC_OFFSET)
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#define MEM_CFG_PLC_FLASH_SIZE (MEM_CFG_LAYOUT_RUN_PLC_LENGTH)
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#define MEM_CFG_PLC_DRAM_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x800)
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#define MEM_CFG_PLC_DRAM_SIZE (0x5F800) //382k
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#define MEM_CFG_PLC_IRAM_ADDRS (MEM_CFG_CHIP_ICACHE2_SMC_BASE)
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#define MEM_CFG_PLC_IRAM_SIZE (0x80000) //32k
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//bbcpu fw
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//run addrs
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#define MEM_CFG_BBCPU_RUN_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x60000)
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#define MEM_CFG_BBCPU_RUN_SIZE (0xD000) //52k
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#define MEM_CFG_BBCPU_DRAM_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x6D000)
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#define MEM_CFG_BBCPU_DRAM_SIZE (0x3000) //12k
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//DCACHE used as heap
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#define MEM_CFG_HEAP1_ADDRS (MEM_CFG_CHIP_DCACHE0_SMC_BASE)
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#define MEM_CFG_HEAP1_SIZE (0x10000) //64k
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#define MEM_CFG_HEAP2_ADDRS (MEM_CFG_CHIP_DCACHE1_SMC_BASE)
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#define MEM_CFG_HEAP2_SIZE (0x10000) //64k
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#define MEM_CFG_HEAP_COUNT 2
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#define MEM_CFG_HEAP_GROUP MEM_CFG_HEAP1_ADDRS, MEM_CFG_HEAP1_SIZE, \
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MEM_CFG_HEAP2_ADDRS, MEM_CFG_HEAP2_SIZE
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//AUTHORITY FOR PARTITIONS
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#define MEM_CFG_AUTH_FOR_SBL (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2))
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#define MEM_CFG_AUTH_FOR_DD1 (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2))
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#define MEM_CFG_AUTH_FOR_DD2 (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2))
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#define MEM_CFG_AUTH_FOR_PARAM (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_OEM (MEM_CFG_R_ONLY(0) | MEM_CFG_R_ONLY(1) | MEM_CFG_R_ONLY(2))
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#define MEM_CFG_AUTH_FOR_PIB1 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_PIB2 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_RUN_CUS (MEM_CFG_NONE(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2))
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#define MEM_CFG_AUTH_FOR_RUN_PLC (MEM_CFG_RW(0) | MEM_CFG_NONE(1) | MEM_CFG_NONE(2))
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#define MEM_CFG_AUTH_FOR_FW1_CUS (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_FW1_PLC (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_FW2_CUS (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_FW2_PLC (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_CUS (MEM_CFG_RW(0) | MEM_CFG_R_ONLY(1) | MEM_CFG_R_ONLY(2))
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#define MEM_CFG_AUTH_FOR_PLC (MEM_CFG_NONE(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_CALI_CUS (MEM_CFG_RW(0) | MEM_CFG_R_ONLY(1) | MEM_CFG_R_ONLY(2))
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#define MEM_CFG_AUTH_FOR_CALI_PLC (MEM_CFG_NONE(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_LOG1 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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#define MEM_CFG_AUTH_FOR_LOG2 (MEM_CFG_RW(0) | MEM_CFG_RW(1) | MEM_CFG_RW(2))
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//PARTITIONS TABLE
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#define MEM_CFG_PARTITIONS {\
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{MEM_CFG_PART_NUM_SBL, MEM_CFG_LAYOUT_SBL_OFFSET, MEM_CFG_LAYOUT_SBL_LENGTH,\
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MEM_CFG_AUTH_FOR_SBL},\
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{MEM_CFG_PART_NUM_DD1, MEM_CFG_LAYOUT_DD1_OFFSET, MEM_CFG_LAYOUT_DD1_LENGTH,\
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MEM_CFG_AUTH_FOR_DD1},\
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{MEM_CFG_PART_NUM_DD2, MEM_CFG_LAYOUT_DD2_OFFSET, MEM_CFG_LAYOUT_DD2_LENGTH,\
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MEM_CFG_AUTH_FOR_DD2},\
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{MEM_CFG_PART_NUM_PARAM, MEM_CFG_LAYOUT_PARAM_OFFSET, MEM_CFG_LAYOUT_PARAM_LENGTH,\
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MEM_CFG_AUTH_FOR_PARAM},\
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{MEM_CFG_PART_NUM_OEM, MEM_CFG_LAYOUT_OEM_OFFSET, MEM_CFG_LAYOUT_OEM_LENGTH,\
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MEM_CFG_AUTH_FOR_OEM},\
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{MEM_CFG_PART_NUM_PIB1, MEM_CFG_LAYOUT_PIB1_OFFSET, MEM_CFG_LAYOUT_PIB1_LENGTH,\
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MEM_CFG_AUTH_FOR_PIB1},\
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{MEM_CFG_PART_NUM_PIB2, MEM_CFG_LAYOUT_PIB2_OFFSET, MEM_CFG_LAYOUT_PIB2_LENGTH,\
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MEM_CFG_AUTH_FOR_PIB2},\
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{MEM_CFG_PART_NUM_CUS, MEM_CFG_LAYOUT_CUST_CUS_OFFSET, MEM_CFG_LAYOUT_CUST_CUS_LENGTH,\
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MEM_CFG_AUTH_FOR_CUS},\
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{MEM_CFG_PART_NUM_PLC, MEM_CFG_LAYOUT_CUST_PLC_OFFSET, MEM_CFG_LAYOUT_CUST_PLC_LENGTH,\
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MEM_CFG_AUTH_FOR_PLC},\
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{MEM_CFG_PART_NUM_CALI_CUS, MEM_CFG_LAYOUT_CALI_CUS_OFFSET, MEM_CFG_LAYOUT_CALI_CUS_LENGTH,\
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MEM_CFG_AUTH_FOR_CALI_CUS},\
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{MEM_CFG_PART_NUM_CALI_PLC, MEM_CFG_LAYOUT_CALI_PLC_OFFSET, MEM_CFG_LAYOUT_CALI_PLC_OFFSET,\
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MEM_CFG_AUTH_FOR_CALI_PLC},\
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{MEM_CFG_PART_NUM_RUN_CUS, MEM_CFG_LAYOUT_RUN_CUS_OFFSET, MEM_CFG_LAYOUT_RUN_CUS_LENGTH,\
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MEM_CFG_AUTH_FOR_RUN_CUS},\
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{MEM_CFG_PART_NUM_RUN_PLC, MEM_CFG_LAYOUT_RUN_PLC_OFFSET, MEM_CFG_LAYOUT_RUN_PLC_LENGTH,\
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MEM_CFG_AUTH_FOR_RUN_PLC},\
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{MEM_CFG_PART_NUM_FW1_CUS, MEM_CFG_LAYOUT_FW1_CUS_OFFSET, MEM_CFG_LAYOUT_FW1_CUS_LENGTH,\
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MEM_CFG_AUTH_FOR_FW1_CUS},\
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{MEM_CFG_PART_NUM_FW1_PLC, MEM_CFG_LAYOUT_FW1_PLC_OFFSET, MEM_CFG_LAYOUT_FW1_PLC_LENGTH,\
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MEM_CFG_AUTH_FOR_FW1_PLC},\
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{MEM_CFG_PART_NUM_FW2_CUS, MEM_CFG_LAYOUT_FW2_CUS_OFFSET, MEM_CFG_LAYOUT_FW2_CUS_LENGTH,\
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MEM_CFG_AUTH_FOR_FW2_CUS},\
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{MEM_CFG_PART_NUM_FW2_PLC, MEM_CFG_LAYOUT_FW2_PLC_OFFSET, MEM_CFG_LAYOUT_FW2_PLC_LENGTH,\
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MEM_CFG_AUTH_FOR_FW2_PLC},\
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{MEM_CFG_PART_NUM_LOG1, MEM_CFG_LAYOUT_LOG1_OFFSET, MEM_CFG_LAYOUT_LOG1_LENGTH,\
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MEM_CFG_AUTH_FOR_LOG1},\
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{MEM_CFG_PART_NUM_LOG2, MEM_CFG_LAYOUT_LOG2_OFFSET, MEM_CFG_LAYOUT_LOG2_LENGTH,\
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MEM_CFG_AUTH_FOR_LOG2}\
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}
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#endif |