185 lines
7.1 KiB
C
185 lines
7.1 KiB
C
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//-----------------------------------
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#define CFG_LEDC_PROT_REG_ADDR 0x0004
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#define LEDC_REG_PROT_ENABLE_OFFSET 16
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#define LEDC_REG_PROT_ENABLE_MASK 0x00010000
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#define LEDC_REG_PROT_PATTERN_OFFSET 0
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#define LEDC_REG_PROT_PATTERN_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC_COMMON_DUTY_CNT_ADDR 0x0008
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#define LEDC_COMMON_DUTY_CNT_THRS_OFFSET 16
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#define LEDC_COMMON_DUTY_CNT_THRS_MASK 0xFFFF0000
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#define LEDC_RDATA_SAMPLE_ENA_OFFSET 9
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#define LEDC_RDATA_SAMPLE_ENA_MASK 0x00000200
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#define LEDC_COMMON_DUTY_CNT_ENA_OFFSET 8
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#define LEDC_COMMON_DUTY_CNT_ENA_MASK 0x00000100
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#define LEDC_COMMON_TIMER_SEL_OFFSET 0
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#define LEDC_COMMON_TIMER_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_LEDC0_CONF_ADDR 0x0200
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#define LEDC0_DUTY_RELOAD_NOP_OFFSET 16
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#define LEDC0_DUTY_RELOAD_NOP_MASK 0xFFFF0000
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#define LEDC0_RDATA_SEL_EN_OFFSET 10
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#define LEDC0_RDATA_SEL_EN_MASK 0x00000400
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#define LEDC0_OUT_INV_OFFSET 9
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#define LEDC0_OUT_INV_MASK 0x00000200
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#define LEDC0_IDLE_LV_OFFSET 8
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#define LEDC0_IDLE_LV_MASK 0x00000100
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#define LEDC0_TIMER_SEL_OFFSET 0 // 每个通道使用公共定时器的时候可以选择定时器?
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#define LEDC0_TIMER_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_LEDC0_DUTY_CONF0_ADDR 0x0204
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#define LEDC0_DUTY_H2L_POINT_OFFSET 16
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#define LEDC0_DUTY_H2L_POINT_MASK 0xFFFF0000
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#define LEDC0_DUTY_L2H_POINT_OFFSET 0
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#define LEDC0_DUTY_L2H_POINT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC0_DUTY_CONF1_ADDR 0x0208
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#define LEDC0_DUTY_CNT_SEL_OFFSET 28
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#define LEDC0_DUTY_CNT_SEL_MASK 0x10000000
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#define LEDC0_DUTY_MODE_OFFSET 26
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#define LEDC0_DUTY_MODE_MASK 0x0C000000
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#define LEDC0_DUTY_ENA_OFFSET 25
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#define LEDC0_DUTY_ENA_MASK 0x02000000
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#define LEDC0_DUTY_SCALE_OFFSET 16
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#define LEDC0_DUTY_SCALE_MASK 0x00FF0000
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#define LEDC0_DUTY_THRS_OFFSET 0
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#define LEDC0_DUTY_THRS_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC0_DUTY_CONF2_ADDR 0x020C
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#define LEDC0_DUTY_NUM_CNT_RELOAD_OFFSET 16
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#define LEDC0_DUTY_NUM_CNT_RELOAD_MASK 0x00010000
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#define LEDC0_DUTY_NUM_CNT_RELOAD_VAL_OFFSET 0
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#define LEDC0_DUTY_NUM_CNT_RELOAD_VAL_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC0_DUTY_CONF3_ADDR 0x0210
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#define LEDC0_DUTY_PHASE_NUM_OFFSET 16
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#define LEDC0_DUTY_PHASE_NUM_MASK 0xFFFF0000
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#define LEDC0_DUTY_NUM_OFFSET 0
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#define LEDC0_DUTY_NUM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC0_INT_ADDR 0x0214
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#define LEDC0_DUTY_PHASE_RELOAD_INT_ST_OFFSET 22
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#define LEDC0_DUTY_PHASE_RELOAD_INT_ST_MASK 0x00400000
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#define LEDC0_NOP_INT_ST_OFFSET 21
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#define LEDC0_NOP_INT_ST_MASK 0x00200000
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#define LEDC0_DUTY_PHASE_RELOAD_INT_RAW_OFFSET 20
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#define LEDC0_DUTY_PHASE_RELOAD_INT_RAW_MASK 0x00100000
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#define LEDC0_NOP_INT_RAW_OFFSET 19
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#define LEDC0_NOP_INT_RAW_MASK 0x00080000
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#define LEDC0_DUTY_PHASE_RELOAD_INT_ENA_OFFSET 18
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#define LEDC0_DUTY_PHASE_RELOAD_INT_ENA_MASK 0x00040000
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#define LEDC0_NOP_INT_ENA_OFFSET 17
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#define LEDC0_NOP_INT_ENA_MASK 0x00020000
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#define LEDC0_DUTY_PHASE_RELOAD_INT_CLR_OFFSET 16
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#define LEDC0_DUTY_PHASE_RELOAD_INT_CLR_MASK 0x00010000
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#define LEDC0_NOP_INT_CLR_OFFSET 15
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#define LEDC0_NOP_INT_CLR_MASK 0x00008000
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#define LEDC0_SHADOW_INT_CLR_OFFSET 14
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#define LEDC0_SHADOW_INT_CLR_MASK 0x00004000
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_CLR_OFFSET 13
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_CLR_MASK 0x00002000
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#define LEDC0_DONE_INT_CLR_OFFSET 12
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#define LEDC0_DONE_INT_CLR_MASK 0x00001000
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#define LEDC0_SHADOW_INT_ENA_OFFSET 10
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#define LEDC0_SHADOW_INT_ENA_MASK 0x00000400
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ENA_OFFSET 9
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ENA_MASK 0x00000200
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#define LEDC0_DONE_INT_ENA_OFFSET 8
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#define LEDC0_DONE_INT_ENA_MASK 0x00000100
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#define LEDC0_SHADOW_INT_ST_OFFSET 6
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#define LEDC0_SHADOW_INT_ST_MASK 0x00000040
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ST_OFFSET 5
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_ST_MASK 0x00000020
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#define LEDC0_DONE_INT_ST_OFFSET 4
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#define LEDC0_DONE_INT_ST_MASK 0x00000010
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#define LEDC0_SHADOW_INT_RAW_OFFSET 2
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#define LEDC0_SHADOW_INT_RAW_MASK 0x00000004
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_RAW_OFFSET 1
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#define LEDC0_DUTY_NUM_CNT_RELOAD_INT_RAW_MASK 0x00000002
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#define LEDC0_DONE_INT_RAW_OFFSET 0
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#define LEDC0_DONE_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_LEDC0_DUTY_CONF4_ADDR 0x0218
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#define LEDC0_DUTY_CYCLE_NUM_OFFSET 24
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#define LEDC0_DUTY_CYCLE_NUM_MASK 0xFF000000
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#define LEDC0_DUTY_LOOP_NUM_OFFSET 16
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#define LEDC0_DUTY_LOOP_NUM_MASK 0x00FF0000
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#define LEDC0_DUTY_NOP_NUM_OFFSET 0
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#define LEDC0_DUTY_NOP_NUM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC0_DUTY_CONF5_ADDR 0x021C
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#define LEDC0_DUTY_PHASE_RELOAD_OFFSET 31
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#define LEDC0_DUTY_PHASE_RELOAD_MASK 0x80000000
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#define LEDC0_DUTY_PHASE_OPT_OFFSET 29
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#define LEDC0_DUTY_PHASE_OPT_MASK 0x20000000
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#define LEDC0_DUTY_PHASE_MODE_NUM_OFFSET 28
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#define LEDC0_DUTY_PHASE_MODE_NUM_MASK 0x10000000
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#define LEDC0_DUTY_PHASE_MODE_OFFSET 24
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#define LEDC0_DUTY_PHASE_MODE_MASK 0x0F000000
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#define LEDC0_DUTY_PHASE_SCALE_OFFSET 16
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#define LEDC0_DUTY_PHASE_SCALE_MASK 0x00FF0000
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#define LEDC0_DUTY_RELOAD_LOOP_OFFSET 8
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#define LEDC0_DUTY_RELOAD_LOOP_MASK 0x0000FF00
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#define LEDC0_DUTY_RELOAD_CYCLE_OFFSET 0
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#define LEDC0_DUTY_RELOAD_CYCLE_MASK 0x000000FF
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//-----------------------------------
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#define CFG_LEDC_TIMER0_CONF_ADDR 0x0600
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#define LEDC_TIMER0_PAUSE_OFFSET 18
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#define LEDC_TIMER0_PAUSE_MASK 0x00040000
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#define LEDC_TIMER0_START_OFFSET 17
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#define LEDC_TIMER0_START_MASK 0x00020000
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#define LEDC_TIMER0_RST_OFFSET 16
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#define LEDC_TIMER0_RST_MASK 0x00010000
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#define LEDC_TIMER0_DIV_OFFSET 0
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#define LEDC_TIMER0_DIV_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC_TIMER0_RELOAD_ADDR 0x0604
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#define LEDC_TIMER0_RELOAD_OFFSET 16
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#define LEDC_TIMER0_RELOAD_MASK 0x00010000
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#define LEDC_TIMER0_RELOAD_VAL_OFFSET 0
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#define LEDC_TIMER0_RELOAD_VAL_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC_TIMER0_STATUS_ADDR 0x0608
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#define LEDC_TIMER0_CNT_OFFSET 0
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#define LEDC_TIMER0_CNT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_LEDC_TIMER0_INT_ADDR 0x060C
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#define LEDC_TIMER0_RELOAD_INT_CLR_OFFSET 25
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#define LEDC_TIMER0_RELOAD_INT_CLR_MASK 0x02000000
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#define LEDC_TIMER0_OVF_INT_CLR_OFFSET 24
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#define LEDC_TIMER0_OVF_INT_CLR_MASK 0x01000000
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#define LEDC_TIMER0_RELOAD_INT_ENA_OFFSET 17
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#define LEDC_TIMER0_RELOAD_INT_ENA_MASK 0x00020000
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#define LEDC_TIMER0_OVF_INT_ENA_OFFSET 16
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#define LEDC_TIMER0_OVF_INT_ENA_MASK 0x00010000
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#define LEDC_TIMER0_RELOAD_INT_ST_OFFSET 9
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#define LEDC_TIMER0_RELOAD_INT_ST_MASK 0x00000200
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#define LEDC_TIMER0_OVF_INT_ST_OFFSET 8
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#define LEDC_TIMER0_OVF_INT_ST_MASK 0x00000100
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#define LEDC_TIMER0_RELOAD_INT_RAW_OFFSET 1
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#define LEDC_TIMER0_RELOAD_INT_RAW_MASK 0x00000002
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#define LEDC_TIMER0_OVF_INT_RAW_OFFSET 0
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#define LEDC_TIMER0_OVF_INT_RAW_MASK 0x00000001
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//HW module read/write macro
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#define LEDC0_READ_REG(addr) SOC_READ_REG(LEDC_REG_BASEADDR + addr)
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#define LEDC0_WRITE_REG(addr,value) SOC_WRITE_REG(LEDC_REG_BASEADDR + addr,value)
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#define LEDC1_READ_REG(addr) SOC_READ_REG(LEDC_FREE_REG_BASEADDR + addr)
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#define LEDC1_WRITE_REG(addr,value) SOC_WRITE_REG(LEDC_FREE_REG_BASEADDR + addr,value)
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