63 lines
2.7 KiB
C
63 lines
2.7 KiB
C
#define PHY_INT_RX_FC_RAW_RECEIVE_OFFSET 30
|
|
#define PHY_INT_RX_FC_RAW_RECEIVE_MASK 0x40000000
|
|
#define PHY_INT_RX_PPM_FIFO_OFFSET 29
|
|
#define PHY_INT_RX_PPM_FIFO_MASK 0x20000000
|
|
#define PHY_INT_RX_TD_PKT_DET_OFFSET 28
|
|
#define PHY_INT_RX_TD_PKT_DET_MASK 0x10000000
|
|
#define PHY_INT_RX_TD_AGC_TIMEOUT_OFFSET 27
|
|
#define PHY_INT_RX_TD_AGC_TIMEOUT_MASK 0x8000000
|
|
#define PHY_INT_RX_TD_AGC_DONE_OFFSET 26
|
|
#define PHY_INT_RX_TD_AGC_DONE_MASK 0x4000000
|
|
#define PHY_INT_RX_TD_AGC_RAMPUP_OFFSET 25
|
|
#define PHY_INT_RX_TD_AGC_RAMPUP_MASK 0x2000000
|
|
#define PHY_INT_RX_TD_AGC_DROP_OFFSET 24
|
|
#define PHY_INT_RX_TD_AGC_DROP_MASK 0x1000000
|
|
#define PHY_INT_RX_FD_GP_SOUND_OFFSET 23
|
|
#define PHY_INT_RX_FD_GP_SOUND_MASK 0x800000
|
|
#define PHY_INT_RX_FD_PLD_FAIL_OFFSET 22
|
|
#define PHY_INT_RX_FD_PLD_FAIL_MASK 0x400000
|
|
#define PHY_INT_RX_FD_PLD_OK_OFFSET 21
|
|
#define PHY_INT_RX_FD_PLD_OK_MASK 0x200000
|
|
#define PHY_INT_RX_FD_PB_FAIL_OFFSET 20
|
|
#define PHY_INT_RX_FD_PB_FAIL_MASK 0x100000
|
|
#define PHY_INT_RX_FD_PB_OK_OFFSET 19
|
|
#define PHY_INT_RX_FD_PB_OK_MASK 0x80000
|
|
#define PHY_INT_RX_FD_FC_FAIL_OFFSET 18
|
|
#define PHY_INT_RX_FD_FC_FAIL_MASK 0x40000
|
|
#define PHY_INT_RX_FD_FC_OK_OFFSET 17
|
|
#define PHY_INT_RX_FD_FC_OK_MASK 0x20000
|
|
#define PHY_INT_RX_FD_CH_EST_DONE_OFFSET 16
|
|
#define PHY_INT_RX_FD_CH_EST_DONE_MASK 0x10000
|
|
#define PHY_INT_WAIT_PARSE_TIME_OUT_OFFSET 15
|
|
#define PHY_INT_WAIT_PARSE_TIME_OUT_MASK 0x8000
|
|
#define PHY_INT_RX_FD_OVERFLOW_OFFSET 14
|
|
#define PHY_INT_RX_FD_OVERFLOW_MASK 0x4000
|
|
#define PHY_INT_LOOPBACK_DONE_OFFSET 13
|
|
#define PHY_INT_LOOPBACK_DONE_MASK 0x2000
|
|
#define PHY_INT_TX_SW_FC_TIMEOUT_OFFSET 12
|
|
#define PHY_INT_TX_SW_FC_TIMEOUT_MASK 0x1000
|
|
#define PHY_INT_DC_LARGE_OFFSET 11
|
|
#define PHY_INT_DC_LARGE_MASK 0x800
|
|
#define PHY_INT_TX_PPM_FIFO_OFFSET 10
|
|
#define PHY_INT_TX_PPM_FIFO_MASK 0x400
|
|
#define PHY_INT_LIC_OVR_STRESS_OFFSET 9
|
|
#define PHY_INT_LIC_OVR_STRESS_MASK 0x200
|
|
#define PHY_INT_TX_FD_PB_TURBO_DONE_OFFSET 8
|
|
#define PHY_INT_TX_FD_PB_TURBO_DONE_MASK 0x100
|
|
#define PHY_INT_TX_FD_FC_TURBO_DONE_OFFSET 7
|
|
#define PHY_INT_TX_FD_FC_TURBO_DONE_MASK 0x80
|
|
#define PHY_INT_TX_FD_INSERT_PREAM_DONE_OFFSET 6
|
|
#define PHY_INT_TX_FD_INSERT_PREAM_DONE_MASK 0x40
|
|
#define PHY_INT_TX_TD_FC_DONE_OFFSET 5
|
|
#define PHY_INT_TX_TD_FC_DONE_MASK 0x20
|
|
#define PHY_INT_TX_TD_PREAM_DONE_OFFSET 4
|
|
#define PHY_INT_TX_TD_PREAM_DONE_MASK 0x10
|
|
#define PHY_INT_TX_TD_START_OFFSET 3
|
|
#define PHY_INT_TX_TD_START_MASK 0x8
|
|
#define PHY_INT_TX_FD_TX_STUCK_OFFSET 2
|
|
#define PHY_INT_TX_FD_TX_STUCK_MASK 0x4
|
|
#define PHY_INT_TX_FD_TX_ABORT_OFFSET 1
|
|
#define PHY_INT_TX_FD_TX_ABORT_MASK 0x2
|
|
#define PHY_INT_TX_FD_TX_DONE_OFFSET 0
|
|
#define PHY_INT_TX_FD_TX_DONE_MASK 0x1
|