459 lines
15 KiB
C
459 lines
15 KiB
C
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//-----------------------------------
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#define CFG_SFC_RVER_ADDR 0x0000
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#define SFC_RF_VER_OFFSET 0
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#define SFC_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SFC_CMD0_ADDR 0x0004
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#define SW_SFC_ENA_OFFSET 31
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#define SW_SFC_ENA_MASK 0x80000000
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#define SW_SFC_DLEN_OFFSET 16
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#define SW_SFC_DLEN_MASK 0x7FFF0000
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#define SW_SFC_CMODE_OFFSET 8
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#define SW_SFC_CMODE_MASK 0x0000FF00
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#define SW_SFC_MODE_OFFSET 0
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#define SW_SFC_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_SFC_CMD1_ADDR 0x0008
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#define SW_SFC_CMD_OFFSET 24
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#define SW_SFC_CMD_MASK 0xFF000000
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#define SW_SFC_ADDR_OFFSET 0
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#define SW_SFC_ADDR_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SFC_CTRL0_ADDR 0x000c
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#define SFC_SW_FORCE_MODE_OFFSET 31
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#define SFC_SW_FORCE_MODE_MASK 0x80000000
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#define CACHE_REQ_ENA_OFFSET 30
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#define CACHE_REQ_ENA_MASK 0x40000000
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#define WIP_CACHE_RD_ENA_OFFSET 29
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#define WIP_CACHE_RD_ENA_MASK 0x20000000
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//-----------------------------------
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#define CFG_SPI_CS0_CFG_ADDR 0x0010
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#define SPI_CS1_FORCE_SEL_OFFSET 4
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#define SPI_CS1_FORCE_SEL_MASK 0x00000010
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#define SPI_CS0_SIZE_OFFSET 0
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#define SPI_CS0_SIZE_MASK 0x0000000F
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//-----------------------------------
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#define CFG_SPI_IO_MAP0_ADDR 0x0014
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#define SFC_CS1_MAP_SEL_OFFSET 28
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#define SFC_CS1_MAP_SEL_MASK 0xF0000000
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#define SFC_SMC_CS_MAP_SEL_OFFSET 24
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#define SFC_SMC_CS_MAP_SEL_MASK 0x0F000000
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#define SFC_CS0_MAP_SEL_OFFSET 20
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#define SFC_CS0_MAP_SEL_MASK 0x00F00000
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#define SFC_HOLD_MAP_SEL_OFFSET 16
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#define SFC_HOLD_MAP_SEL_MASK 0x000F0000
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#define SFC_WP_MAP_SEL_OFFSET 12
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#define SFC_WP_MAP_SEL_MASK 0x0000F000
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#define SFC_SO_MAP_SEL_OFFSET 8
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#define SFC_SO_MAP_SEL_MASK 0x00000F00
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#define SFC_SI_MAP_SEL_OFFSET 4
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#define SFC_SI_MAP_SEL_MASK 0x000000F0
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#define SFC_CLK_MAP_SEL_OFFSET 0
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#define SFC_CLK_MAP_SEL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_SFC_PE_STS_ADDR 0x0018
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#define PE_CMD_CNT_CLR_OFFSET 8
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#define PE_CMD_CNT_CLR_MASK 0x00000100
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#define PE_CMD_CNT_OFFSET 0
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#define PE_CMD_CNT_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SFC_CFG0_ADDR 0x0030
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#define SFC_DATA_LE_OFFSET 16
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#define SFC_DATA_LE_MASK 0x00010000
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#define SFC_DUMMY_NUM_OFFSET 12
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#define SFC_DUMMY_NUM_MASK 0x00003000
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#define SFC_PROG_SUS_ENA_OFFSET 8
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#define SFC_PROG_SUS_ENA_MASK 0x00000100
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#define SPI_1P8V_OFFSET 5
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#define SPI_1P8V_MASK 0x00000020
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#define SFC_CRYPT_MODE_OFFSET 4
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#define SFC_CRYPT_MODE_MASK 0x00000010
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#define SFC_CACHE_RD_MODE_OFFSET 0
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#define SFC_CACHE_RD_MODE_MASK 0x00000007
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//-----------------------------------
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#define CFG_SFC_CLK0_ADDR 0x0034
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#define CLK_SPI_SFC_FORCE_DIV_OFFSET 5
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#define CLK_SPI_SFC_FORCE_DIV_MASK 0x00000020
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#define CLK_SPI_SFC_ENA_OFFSET 4
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#define CLK_SPI_SFC_ENA_MASK 0x00000010
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#define CLK_SPI_SFC_DIV_OFFSET 0
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#define CLK_SPI_SFC_DIV_MASK 0x00000007
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//-----------------------------------
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#define CFG_SFC_CFG1_ADDR 0x0040
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#define PE_WAIT_TIME_OFFSET 0
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#define PE_WAIT_TIME_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SFC_CFG2_ADDR 0x00044
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#define RESUME_WAIT_TIME_OFFSET 16
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#define RESUME_WAIT_TIME_MASK 0xFFFF0000
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#define SUS_WAIT_TIME_OFFSET 0
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#define SUS_WAIT_TIME_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SFC_STS0_ADDR 0x0048
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#define SFC_DP_FSM_STATE_OFFSET 12
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#define SFC_DP_FSM_STATE_MASK 0x0000F000
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#define SFC_CTRL_FSM_STATE_OFFSET 4
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#define SFC_CTRL_FSM_STATE_MASK 0x000001F0
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#define SFC_SPI_FSM_STATE_OFFSET 0
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#define SFC_SPI_FSM_STATE_MASK 0x00000007
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//-----------------------------------
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#define CFG_SFC_RDATA_ADDR 0x004c
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#define SW_SFC_RDATA_OFFSET 0
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#define SW_SFC_RDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SFC_WDATA_ADDR 0x0050
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#define SW_SFC_WDATA_OFFSET 0
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#define SW_SFC_WDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SFC_DBG_ADDR 0x0054
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#define SFC_SMC_ARB_SHARE_OFFSET 9
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#define SFC_SMC_ARB_SHARE_MASK 0x00000200
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#define SFC_WIP_SEL_OFFSET 6
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#define SFC_WIP_SEL_MASK 0x000001C0
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#define SFC_SMC_IO_SHARE_OFFSET 5
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#define SFC_SMC_IO_SHARE_MASK 0x00000020
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#define SFC_TX_EDGE_SEL_OFFSET 4
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#define SFC_TX_EDGE_SEL_MASK 0x00000010
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#define SFC_ADDR_MAP_MODE_OFFSET 3
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#define SFC_ADDR_MAP_MODE_MASK 0x00000008
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#define SFC_ADDR_MAP_ENA_OFFSET 2
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#define SFC_ADDR_MAP_ENA_MASK 0x00000004
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#define SFC_RX_EDGE_SEL_OFFSET 1
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#define SFC_RX_EDGE_SEL_MASK 0x00000002
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#define SFC_CLK_FORCE_OUT_OFFSET 0
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#define SFC_CLK_FORCE_OUT_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_AMAP0_ADDR 0x0060
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#define SFC_ABLK3_MAP_OFFSET 24
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#define SFC_ABLK3_MAP_MASK 0x1F000000
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#define SFC_ABLK2_MAP_OFFSET 16
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#define SFC_ABLK2_MAP_MASK 0x001F0000
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#define SFC_ABLK1_MAP_OFFSET 8
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#define SFC_ABLK1_MAP_MASK 0x00001F00
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#define SFC_ABLK0_MAP_OFFSET 0
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#define SFC_ABLK0_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP1_ADDR 0x0064
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#define SFC_ABLK7_MAP_OFFSET 24
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#define SFC_ABLK7_MAP_MASK 0x1F000000
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#define SFC_ABLK6_MAP_OFFSET 16
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#define SFC_ABLK6_MAP_MASK 0x001F0000
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#define SFC_ABLK5_MAP_OFFSET 8
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#define SFC_ABLK5_MAP_MASK 0x00001F00
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#define SFC_ABLK4_MAP_OFFSET 0
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#define SFC_ABLK4_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP2_ADDR 0x0068
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#define SFC_ABLK11_MAP_OFFSET 24
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#define SFC_ABLK11_MAP_MASK 0x1F000000
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#define SFC_ABLK10_MAP_OFFSET 16
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#define SFC_ABLK10_MAP_MASK 0x001F0000
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#define SFC_ABLK9_MAP_OFFSET 8
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#define SFC_ABLK9_MAP_MASK 0x00001F00
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#define SFC_ABLK8_MAP_OFFSET 0
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#define SFC_ABLK8_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP3_ADDR 0x006c
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#define SFC_ABLK15_MAP_OFFSET 24
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#define SFC_ABLK15_MAP_MASK 0x1F000000
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#define SFC_ABLK14_MAP_OFFSET 16
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#define SFC_ABLK14_MAP_MASK 0x001F0000
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#define SFC_ABLK13_MAP_OFFSET 8
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#define SFC_ABLK13_MAP_MASK 0x00001F00
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#define SFC_ABLK12_MAP_OFFSET 0
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#define SFC_ABLK12_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP4_ADDR 0x0070
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#define SFC_ABLK19_MAP_OFFSET 24
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#define SFC_ABLK19_MAP_MASK 0x1F000000
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#define SFC_ABLK18_MAP_OFFSET 16
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#define SFC_ABLK18_MAP_MASK 0x001F0000
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#define SFC_ABLK17_MAP_OFFSET 8
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#define SFC_ABLK17_MAP_MASK 0x00001F00
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#define SFC_ABLK16_MAP_OFFSET 0
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#define SFC_ABLK16_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP5_ADDR 0x0074
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#define SFC_ABLK23_MAP_OFFSET 24
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#define SFC_ABLK23_MAP_MASK 0x1F000000
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#define SFC_ABLK22_MAP_OFFSET 16
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#define SFC_ABLK22_MAP_MASK 0x001F0000
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#define SFC_ABLK21_MAP_OFFSET 8
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#define SFC_ABLK21_MAP_MASK 0x00001F00
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#define SFC_ABLK20_MAP_OFFSET 0
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#define SFC_ABLK20_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP6_ADDR 0x0078
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#define SFC_ABLK27_MAP_OFFSET 24
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#define SFC_ABLK27_MAP_MASK 0x1F000000
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#define SFC_ABLK26_MAP_OFFSET 16
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#define SFC_ABLK26_MAP_MASK 0x001F0000
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#define SFC_ABLK25_MAP_OFFSET 8
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#define SFC_ABLK25_MAP_MASK 0x00001F00
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#define SFC_ABLK24_MAP_OFFSET 0
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#define SFC_ABLK24_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_AMAP7_ADDR 0x007c
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#define SFC_ABLK31_MAP_OFFSET 24
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#define SFC_ABLK31_MAP_MASK 0x1F000000
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#define SFC_ABLK30_MAP_OFFSET 16
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#define SFC_ABLK30_MAP_MASK 0x001F0000
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#define SFC_ABLK29_MAP_OFFSET 8
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#define SFC_ABLK29_MAP_MASK 0x00001F00
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#define SFC_ABLK28_MAP_OFFSET 0
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#define SFC_ABLK28_MAP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_SWM_CFG0_ADDR 0x0080
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#define CFG_SPI_WR_OFFSET 9
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#define CFG_SPI_WR_MASK 0x00000200
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#define CFG_SPI_RD_OFFSET 8
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#define CFG_SPI_RD_MASK 0x00000100
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#define CFG_CMD_DUAL_MODE_OFFSET 7
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#define CFG_CMD_DUAL_MODE_MASK 0x00000080
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#define CFG_CMD_QUAD_MODE_OFFSET 6
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#define CFG_CMD_QUAD_MODE_MASK 0x00000040
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#define CFG_ADDR_DUAL_MODE_OFFSET 5
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#define CFG_ADDR_DUAL_MODE_MASK 0x00000020
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#define CFG_ADDR_QUAD_MODE_OFFSET 4
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#define CFG_ADDR_QUAD_MODE_MASK 0x00000010
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#define CFG_CMODE_DUAL_MODE_OFFSET 3
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#define CFG_CMODE_DUAL_MODE_MASK 0x00000008
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#define CFG_CMODE_QUAD_MODE_OFFSET 2
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#define CFG_CMODE_QUAD_MODE_MASK 0x00000004
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#define CFG_DATA_DUAL_MODE_OFFSET 1
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#define CFG_DATA_DUAL_MODE_MASK 0x00000002
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#define CFG_DATA_QUAD_MODE_OFFSET 0
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#define CFG_DATA_QUAD_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_SWM_CFG1_ADDR 0x0084
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#define CFG_CMD_LEN_OFFSET 24
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#define CFG_CMD_LEN_MASK 0x1F000000
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#define CFG_ADDR_LEN_OFFSET 16
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#define CFG_ADDR_LEN_MASK 0x001F0000
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#define CFG_CMODE_LEN_OFFSET 8
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#define CFG_CMODE_LEN_MASK 0x00001F00
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#define CFG_DUMMY_LEN_OFFSET 0
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#define CFG_DUMMY_LEN_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_SWM_CFG2_ADDR 0x0088
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#define CFG_CACHE_CMD_OFFSET 24
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#define CFG_CACHE_CMD_MASK 0xFF000000
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#define CFG_WIP_CMD_OFFSET 16
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#define CFG_WIP_CMD_MASK 0x00FF0000
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#define CFG_RESUME_CMD_OFFSET 8
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#define CFG_RESUME_CMD_MASK 0x0000FF00
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#define CFG_SUS_CMD_OFFSET 0
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#define CFG_SUS_CMD_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SFC_CACHE_CFG0_ADDR 0x008c
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#define CACHE_SPI_WR_OFFSET 9
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#define CACHE_SPI_WR_MASK 0x00000200
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#define CACHE_SPI_RD_OFFSET 8
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#define CACHE_SPI_RD_MASK 0x00000100
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#define CACHE_CMD_DUAL_MODE_OFFSET 7
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#define CACHE_CMD_DUAL_MODE_MASK 0x00000080
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#define CACHE_CMD_QUAD_MODE_OFFSET 6
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#define CACHE_CMD_QUAD_MODE_MASK 0x00000040
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#define CACHE_ADDR_DUAL_MODE_OFFSET 5
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#define CACHE_ADDR_DUAL_MODE_MASK 0x00000020
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#define CACHE_ADDR_QUAD_MODE_OFFSET 4
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#define CACHE_ADDR_QUAD_MODE_MASK 0x00000010
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#define CACHE_CMODE_DUAL_MODE_OFFSET 3
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#define CACHE_CMODE_DUAL_MODE_MASK 0x00000008
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#define CACHE_CMODE_QUAD_MODE_OFFSET 2
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#define CACHE_CMODE_QUAD_MODE_MASK 0x00000004
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#define CACHE_DATA_DUAL_MODE_OFFSET 1
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#define CACHE_DATA_DUAL_MODE_MASK 0x00000002
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#define CACHE_DATA_QUAD_MODE_OFFSET 0
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#define CACHE_DATA_QUAD_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_CACHE_CFG1_ADDR 0x0090
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#define CACHE_CMD_LEN_OFFSET 24
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#define CACHE_CMD_LEN_MASK 0x1F000000
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#define CACHE_ADDR_LEN_OFFSET 16
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#define CACHE_ADDR_LEN_MASK 0x001F0000
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#define CACHE_CMODE_LEN_OFFSET 8
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#define CACHE_CMODE_LEN_MASK 0x00001F00
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#define CACHE_DUMMY_LEN_OFFSET 0
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#define CACHE_DUMMY_LEN_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_WIP_CFG0_ADDR 0x0094
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#define WIP_SPI_WR_OFFSET 9
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#define WIP_SPI_WR_MASK 0x00000200
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#define WIP_SPI_RD_OFFSET 8
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#define WIP_SPI_RD_MASK 0x00000100
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#define WIP_CMD_DUAL_MODE_OFFSET 7
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#define WIP_CMD_DUAL_MODE_MASK 0x00000080
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#define WIP_CMD_QUAD_MODE_OFFSET 6
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#define WIP_CMD_QUAD_MODE_MASK 0x00000040
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#define WIP_ADDR_DUAL_MODE_OFFSET 5
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#define WIP_ADDR_DUAL_MODE_MASK 0x00000020
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#define WIP_ADDR_QUAD_MODE_OFFSET 4
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#define WIP_ADDR_QUAD_MODE_MASK 0x00000010
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#define WIP_CMODE_DUAL_MODE_OFFSET 3
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#define WIP_CMODE_DUAL_MODE_MASK 0x00000008
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#define WIP_CMODE_QUAD_MODE_OFFSET 2
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#define WIP_CMODE_QUAD_MODE_MASK 0x00000004
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#define WIP_DATA_DUAL_MODE_OFFSET 1
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#define WIP_DATA_DUAL_MODE_MASK 0x00000002
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#define WIP_DATA_QUAD_MODE_OFFSET 0
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#define WIP_DATA_QUAD_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_WIP_CFG1_ADDR 0x0098
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#define WIP_CMD_LEN_OFFSET 24
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#define WIP_CMD_LEN_MASK 0x1F000000
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#define WIP_ADDR_LEN_OFFSET 16
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#define WIP_ADDR_LEN_MASK 0x001F0000
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#define WIP_CMODE_LEN_OFFSET 8
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#define WIP_CMODE_LEN_MASK 0x00001F00
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#define WIP_DUMMY_LEN_OFFSET 0
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#define WIP_DUMMY_LEN_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_RESUME_CFG0_ADDR 0x009c
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#define RESUME_SPI_WR_OFFSET 9
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#define RESUME_SPI_WR_MASK 0x00000200
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#define RESUME_SPI_RD_OFFSET 8
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#define RESUME_SPI_RD_MASK 0x00000100
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#define RESUME_CMD_DUAL_MODE_OFFSET 7
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#define RESUME_CMD_DUAL_MODE_MASK 0x00000080
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#define RESUME_CMD_QUAD_MODE_OFFSET 6
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#define RESUME_CMD_QUAD_MODE_MASK 0x00000040
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#define RESUME_ADDR_DUAL_MODE_OFFSET 5
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#define RESUME_ADDR_DUAL_MODE_MASK 0x00000020
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#define RESUME_ADDR_QUAD_MODE_OFFSET 4
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#define RESUME_ADDR_QUAD_MODE_MASK 0x00000010
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#define RESUME_CMODE_DUAL_MODE_OFFSET 3
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#define RESUME_CMODE_DUAL_MODE_MASK 0x00000008
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#define RESUME_CMODE_QUAD_MODE_OFFSET 2
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#define RESUME_CMODE_QUAD_MODE_MASK 0x00000004
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#define RESUME_DATA_DUAL_MODE_OFFSET 1
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#define RESUME_DATA_DUAL_MODE_MASK 0x00000002
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#define RESUME_DATA_QUAD_MODE_OFFSET 0
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#define RESUME_DATA_QUAD_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_RESUME_CFG1_ADDR 0x00a0
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#define RESUME_CMD_LEN_OFFSET 24
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#define RESUME_CMD_LEN_MASK 0x1F000000
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#define RESUME_ADDR_LEN_OFFSET 16
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#define RESUME_ADDR_LEN_MASK 0x001F0000
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#define RESUME_CMODE_LEN_OFFSET 8
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#define RESUME_CMODE_LEN_MASK 0x00001F00
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#define RESUME_DUMMY_LEN_OFFSET 0
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#define RESUME_DUMMY_LEN_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_SUS_CFG0_ADDR 0x00a4
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#define SUS_SPI_WR_OFFSET 9
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#define SUS_SPI_WR_MASK 0x00000200
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#define SUS_SPI_RD_OFFSET 8
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#define SUS_SPI_RD_MASK 0x00000100
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#define SUS_CMD_DUAL_MODE_OFFSET 7
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#define SUS_CMD_DUAL_MODE_MASK 0x00000080
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#define SUS_CMD_QUAD_MODE_OFFSET 6
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#define SUS_CMD_QUAD_MODE_MASK 0x00000040
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#define SUS_ADDR_DUAL_MODE_OFFSET 5
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#define SUS_ADDR_DUAL_MODE_MASK 0x00000020
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#define SUS_ADDR_QUAD_MODE_OFFSET 4
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#define SUS_ADDR_QUAD_MODE_MASK 0x00000010
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#define SUS_CMODE_DUAL_MODE_OFFSET 3
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#define SUS_CMODE_DUAL_MODE_MASK 0x00000008
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#define SUS_CMODE_QUAD_MODE_OFFSET 2
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#define SUS_CMODE_QUAD_MODE_MASK 0x00000004
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#define SUS_DATA_DUAL_MODE_OFFSET 1
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#define SUS_DATA_DUAL_MODE_MASK 0x00000002
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#define SUS_DATA_QUAD_MODE_OFFSET 0
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#define SUS_DATA_QUAD_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_SUS_CFG1_ADDR 0x00a8
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#define SUS_CMD_LEN_OFFSET 24
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#define SUS_CMD_LEN_MASK 0x1F000000
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#define SUS_ADDR_LEN_OFFSET 16
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#define SUS_ADDR_LEN_MASK 0x001F0000
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#define SUS_CMODE_LEN_OFFSET 8
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#define SUS_CMODE_LEN_MASK 0x00001F00
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#define SUS_DUMMY_LEN_OFFSET 0
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#define SUS_DUMMY_LEN_MASK 0x0000001F
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//-----------------------------------
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#define CFG_SFC_PE_PAUSE_CFG_ADDR 0x00ac
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#define PE_CMD_WAIT_TIME_OFFSET 16
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#define PE_CMD_WAIT_TIME_MASK 0xFFFF0000
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#define PAUSE_WAIT_TIME_OFFSET 0
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#define PAUSE_WAIT_TIME_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SFC_WIP_TIMEOUT_CFG_ADDR 0x00b0
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#define WIP_TIMEOUT_FLAG_OFFSET 16
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#define WIP_TIMEOUT_FLAG_MASK 0x00010000
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#define WIP_TIMEOUT_MAX_OFFSET 0
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#define WIP_TIMEOUT_MAX_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SFC_WIP_GAP_CFG_ADDR 0x00b4
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#define WIP_GAP_WAIT_TIME_OFFSET 0
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#define WIP_GAP_WAIT_TIME_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SFC_PE_WAIT_CNT_ADDR 0x00b8
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#define SFC_PE_WAIT_CNT_OFFSET 0
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#define SFC_PE_WAIT_CNT_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SFC_INT_STS_ADDR 0x00bc
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#define SFC_DONE_INT_ENA_OFFSET 1
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#define SFC_DONE_INT_ENA_MASK 0x00000002
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#define SFC_DONE_INT_RAW_OFFSET 0
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#define SFC_DONE_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_SFC_ARB_STS_ADDR 0x00c0
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#define SFC_ARB_STS_OFFSET 0
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#define SFC_ARB_STS_MASK 0x0000007F
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//-----------------------------------
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#define CFG_SFC_CACHE_DIS_TIMER_CTRL_ADDR 0x00c4
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#define SFC_CACHE_DIS_CNT_ENA_OFFSET 31
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#define SFC_CACHE_DIS_CNT_ENA_MASK 0x80000000
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#define SFC_CACHE_DIS_CNT_OFFSET 16
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#define SFC_CACHE_DIS_CNT_MASK 0x7FFF0000
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#define SFC_CACHE_DIS_CNT_MAX_OFFSET 0
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#define SFC_CACHE_DIS_CNT_MAX_MASK 0x00007FFF
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//HW module read/write macro
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#define SFC_READ_REG(addr) SOC_READ_REG(SFC_REG_BASEADDR + addr)
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#define SFC_WRITE_REG(addr,value) SOC_WRITE_REG(SFC_REG_BASEADDR + addr,value)
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