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kunlun/plc/halphy/hw/phy_ana.c
andy c756587541 初始提交
2024-09-28 14:24:04 +08:00

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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "ada_reg.h"
#include "phy_ana.h"
#include "ahb.h"
#include "hw_reg_api.h"
#include "phy_bb.h"
#include "phy_chn.h"
#include "phy_rxtd_reg.h"
#include "phy_rx_fd_reg.h"
#include "phy_dfe_reg.h"
#include "iot_io.h"
#include "hw_phy_api.h"
#include "phy_reg.h"
#include "phy_ana.h"
#include "phy_ana_hw.h"
#include "phy_txrx_pwr.h"
#include "phy_pm.h"
#if HW_PLATFORM > HW_PLATFORM_FPGA
#include "granite_reg.h"
#endif
extern uint32_t all_mask_gain_table[];
/* ada reg clk enable */
void enable_ada(uint32_t enable)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
if (enable) {
ahb_ada_enable();
} else {
ahb_ada_disable();
}
#else
(void)enable;
#endif
return;
}
/* ada rst */
void warm_rst_ada()
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
ahb_ada_reset();
#endif
return;
}
/* ada power on enable */
void phy_ada_enable(uint32_t enable)
{
if (enable) {
enable = 0x1;
}
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADA power on */
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADA_POWER_ON, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
#endif
return;
}
/***************************************DAC******************************************/
/* dac buf size conf */
void phy_dac_buf_size_cfg(uint32_t size)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* dac buf size */
tmp = ADA_READ_REG(CFG_DAC_CFG0_ADDR);
REG_FIELD_SET(DAC_BUF_SIZE, tmp, size);
ADA_WRITE_REG(CFG_DAC_CFG0_ADDR, tmp);
#else
(void)size;
#endif
return;
}
/* dac mux conf, 0-DA_B come from phy and DA_A come from tone, 1 reverse */
void phy_dac_mux_cfg(DA_B_PATH_CFG path)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* DAC mux */
tmp = ADA_READ_REG(CFG_DAC_CFG1_ADDR);
REG_FIELD_SET(DAC_MUX, tmp, path);
ADA_WRITE_REG(CFG_DAC_CFG1_ADDR, tmp);
#else
(void)path;
#endif
return;
}
/* dac clk inv en conf */
void phy_dac_clk_inv_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* DAC clk inv */
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(DAC_CLK_INV, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* dac enable conf */
void phy_dac_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* DAC en */
tmp = ADA_READ_REG(CFG_DAC_CFG0_ADDR);
REG_FIELD_SET(SOC_DAC_EN, tmp, enable);
ADA_WRITE_REG(CFG_DAC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* dac mux conf */
void phy_dac_tone_mode_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_DAC_CFG1_ADDR);
REG_FIELD_SET(TONE_MODE, tmp, enable);
ADA_WRITE_REG(CFG_DAC_CFG1_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* dac tone num conf */
void phy_dac_tone_num_cfg(uint32_t tone_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_DAC_CFG1_ADDR);
REG_FIELD_SET(TONE_NUMBER, tmp, tone_num);
ADA_WRITE_REG(CFG_DAC_CFG1_ADDR, tmp);
#else
(void)tone_num;
#endif
return;
}
/***************************************ADC******************************************/
/* adc enable conf */
void phy_adc_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADC en */
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(SOC_ADC_EN, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc mode conf */
void phy_adc_mode_cfg(ADC_MODE_CFG mode)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADC mode select */
if(mode == ADC_MODE_FORCE)
{
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_FORCE_MODE, tmp, true);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_AUTO_MODE, tmp, false);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
}
else
{
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_AUTO_MODE, tmp, true);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
}
#else
(void)mode;
#endif
return;
}
/* adc buf size conf */
void phy_adc_buf_size_cfg(uint32_t buf_size)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* buf size */
tmp = ADA_READ_REG(CFG_ADC_CFG1_ADDR);
REG_FIELD_SET(ADC_BUF_SIZE, tmp, buf_size);
ADA_WRITE_REG(CFG_ADC_CFG1_ADDR, tmp);
#else
(void)buf_size;
#endif
return;
}
/* adc sample size conf */
void phy_adc_sample_size_cfg(uint32_t sample_size)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* sample size */
tmp = ADA_READ_REG(CFG_ADC_CFG3_ADDR);
REG_FIELD_SET(ADC_SAMPLE_SIZE, tmp, sample_size);
ADA_WRITE_REG(CFG_ADC_CFG3_ADDR, tmp);
#else
(void)sample_size;
#endif
return;
}
/* adc threshhold conf */
void phy_adc_thrd_cfg(uint32_t thrd)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_THR_VAL, tmp, thrd);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
#else
(void)thrd;
#endif
return;
}
/* adc clk inv conf */
void phy_adc_clk_inv_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_CLK_INV, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc dmsb inv conf */
void phy_adc_dmsb_inv_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADC_DMSB_INV, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc sample done status */
bool_t phy_adc_is_sample_done()
{
bool_t is_done = 0;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
//sample done;
is_done = (tmp & ADC_SAMPLE_DONE_MASK)?1:0;
#endif
return is_done;
}
/* adc trig en */
void phy_adc_trig_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADC_TRIG, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc trig addr */
uint32_t phy_adc_trig_addr_get()
{
uint32_t trig_offset = 0;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
trig_offset = REG_FIELD_GET(ADC_TRIG_ADDR, ADA_READ_REG(CFG_ADC_STS0_ADDR));
#endif
return trig_offset;
}
/* get ada power */
uint32_t phy_ada_get_power_on()
{
uint32_t tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
return REG_FIELD_GET(ADA_POWER_ON, tmp);
}
/*************************************************************************************/
/* DAC cfg */
void phy_ada_tx_cfg(DaTxPara_t *tp)
{
/*clk enable*/
enable_ada(true);
//warm_rst_ada();
/* DAC buf size */
phy_dac_buf_size_cfg(tp->buf_size);
/* DAC mux */
phy_dac_mux_cfg(tp->path);
/* DAC clk inv */
phy_dac_clk_inv_cfg(tp->inv_en);
/* dac mux conf */
phy_dac_tone_mode_en_cfg(tp->tone_mode_en);
/* dac tone num conf */
phy_dac_tone_num_cfg(tp->tone_num);
/* DAC en */
phy_dac_en_cfg(false);//mode from phy
}
/* ADC cfg */
void phy_ada_rx_cfg(DaRxPara_t *rp)
{
/*clk enable*/
enable_ada(true);
/* adc mode select */
phy_adc_mode_cfg(rp->mode);
/* ADC buf size conf */
phy_adc_buf_size_cfg(rp->buf_size);
/* ADC sample size conf */
phy_adc_sample_size_cfg(rp->sample_size);
/* ADC threshhold conf */
phy_adc_thrd_cfg(rp->thrd);
/* ADC clk inv conf */
phy_adc_clk_inv_cfg(rp->clk_inv_en);
/* ADC dmsb inv conf */
phy_adc_dmsb_inv_cfg(rp->dmsb_inv_en);
/* ADC en */
phy_adc_en_cfg(true);
}
void phy_ana_tx_set(bool_t tx_en, bool_t dac_en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint8_t reg_id = 0;
uint32_t wdata = 0;
uint32_t wmask = 0;
reg_id = CFG_ANA_TOP_REG_ADDR;
wdata = tx_en << TOP_EN_TX_OFFSET | \
dac_en << TOP_EN_DAC_OFFSET;
wmask = TOP_EN_TX_MASK | TOP_EN_DAC_MASK;
phy_ana_i2c_write(reg_id,wdata,wmask);
#else
(void)tx_en;
(void)dac_en;
#endif
}
void phy_ana_rx_set(bool_t rx_en, bool_t adc_en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint8_t reg_id = 0;
uint32_t wdata = 0;
uint32_t wmask = 0;
reg_id = CFG_ANA_TOP_REG_ADDR;
wdata = rx_en << TOP_EN_RX_OFFSET | \
adc_en << TOP_EN_ADC_OFFSET;
wmask = TOP_EN_RX_MASK | TOP_EN_ADC_MASK;
phy_ana_i2c_write(reg_id,wdata,wmask);
#else
(void)rx_en;
(void)adc_en;
#endif
}
void phy_ana_sadc_enable(bool_t enable)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint8_t reg_id = 0;
uint8_t rodata = 0;
uint32_t rdata = 0;
uint32_t wdata = 0;
uint32_t wmask = 0;
/*init granite top reg */
reg_id = CFG_ANA_TOP_REG_ADDR;
if(enable) {
wdata = TOP_EN_SADC_MASK; //enable sadc
} else{
wdata = 0; //enable sadc
}
wmask = TOP_EN_SADC_MASK;
phy_ana_i2c_write(reg_id, wdata, wmask);
/* init granite sadc reg */
reg_id = CFG_ANA_SADC_REG_ADDR;
phy_ana_i2c_read(reg_id, &rdata, &rodata);
REG_FIELD_SET(SADC_EN, rdata, enable); //monitor sadc enable
//REG_FIELD_SET(SADC_EN_CAL, rdata, 0);//sadc dc offset calibration enables
phy_ana_i2c_write(reg_id, rdata, ~0);
#else
(void)enable;
#endif
}
/* bb ana tx/rx */
void phy_ana_dfe_init(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_ADDR);
REG_FIELD_SET(SW_TX_START_CFG_DATA, tmp, 0x20202);
PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_MASK_ADDR);
REG_FIELD_SET(SW_TX_START_CFG_DATA_MASK, tmp, 0x28303);
PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_MASK_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_END_CFG_ADDR);
REG_FIELD_SET(SW_TX_END_CFG_DATA, tmp, 0x0);
PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_END_CFG_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_END_CFG_MASK_ADDR);
REG_FIELD_SET(SW_TX_END_CFG_DATA_MASK, tmp, 0x28303);
PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_END_CFG_MASK_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_START_CFG_ADDR);
REG_FIELD_SET(SW_RX_START_CFG_DATA, tmp, 0x8101);
PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_CFG_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_START_CFG_MASK_ADDR);
REG_FIELD_SET(SW_RX_START_CFG_DATA_MASK, tmp, 0x28303);
PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_CFG_MASK_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_END_CFG_ADDR);
REG_FIELD_SET(SW_RX_END_CFG_DATA, tmp, 0x0);
PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_END_CFG_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_END_CFG_MASK_ADDR);
REG_FIELD_SET(SW_RX_END_CFG_DATA_MASK, tmp, 0x28303);
PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_END_CFG_MASK_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_ON_CFG_MASK_ADDR);
REG_FIELD_SET(SW_RX_ON_CFG_DATA_MASK, tmp, 0xe7ffc0ff);
PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_ON_CFG_MASK_ADDR, tmp);
#endif
}
/* wait until i2c is idle */
static inline void phy_wait_i2c_idle(uint32_t tmp)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
do{
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_REG_CTRL_ADDR);
}while(REG_FIELD_GET(ANA_I2C_BUSY, tmp) || \
REG_FIELD_GET(RX_I2C_BUSY, tmp) || \
REG_FIELD_GET(TOP_I2C_BUSY, tmp));
#else
(void)tmp;
#endif
}
void phy_ana_i2c_write(uint32_t reg_id, uint32_t wdata, uint32_t mask)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
uint8_t rodata = 0;
uint32_t rdata = 0;
uint32_t wmask = 0;
/* check mask valid */
if(!mask){
return;
}
/* poll idle */
phy_wait_i2c_idle(tmp);
/* cfg mask */
if((reg_id == CFG_ANA_TOP_REG_ADDR) || \
(reg_id == CFG_ANA_RX_REG_0_ADDR) || \
(~mask == 0))
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_REG_WDATA_MASK_ADDR);
REG_FIELD_SET(SW_ANA_REG_WDATA_MASK, tmp, mask);
PHY_DFE_WRITE_REG(CFG_BB_ANA_REG_WDATA_MASK_ADDR, tmp);
/* cfg wdata */
PHY_DFE_WRITE_REG(CFG_BB_ANA_REG_WDATA_ADDR, wdata);
}
else{
phy_ana_i2c_read(reg_id, &rdata, &rodata);
wmask = (rdata & (~mask)) | (wdata & mask);
/* cfg wdata */
PHY_DFE_WRITE_REG(CFG_BB_ANA_REG_WDATA_ADDR, wmask);
}
/* poll idle */
phy_wait_i2c_idle(tmp);
/* cfg reg id, start write */
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_REG_CTRL_ADDR);
REG_FIELD_SET(SW_ANA_REG_ADDR, tmp, reg_id);
REG_FIELD_SET(SW_ANA_REG_WR, tmp, 1);
REG_FIELD_SET(SW_ANA_REG_START, tmp, 1);
PHY_DFE_WRITE_REG(CFG_BB_ANA_REG_CTRL_ADDR, tmp);
/* poll idle */
phy_wait_i2c_idle(tmp);
#else
(void)reg_id;
(void)wdata;
(void)mask;
#endif
}
void phy_ana_i2c_read(uint32_t reg_id, uint32_t *rdata, uint8_t *rodata)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* poll idle */
phy_wait_i2c_idle(tmp);
/* cfg reg id, start write */
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_REG_CTRL_ADDR);
REG_FIELD_SET(SW_ANA_REG_ADDR, tmp, reg_id);
REG_FIELD_SET(SW_ANA_REG_WR, tmp, 0);
REG_FIELD_SET(SW_ANA_REG_START, tmp, 1);
PHY_DFE_WRITE_REG(CFG_BB_ANA_REG_CTRL_ADDR, tmp);
/* poll idle */
phy_wait_i2c_idle(tmp);
/* get ro-data */
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_REG_CTRL_ADDR);
*rodata = REG_FIELD_GET(SW_ANA_REG_RO_DATA, tmp);
/* get rdata */
*rdata = PHY_DFE_READ_REG(CFG_BB_ANA_REG_RDATA_ADDR);
#else
(void)reg_id;
(void)rdata;
(void)rodata;
#endif
}
void phy_ana_pga_gain_set(uint32_t val)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
phy_ana_i2c_write(CFG_ANA_TX_REG_ADDR, val << TX_GPGA_OFFSET, \
TX_GPGA_MASK);
#else
(void)val;
#endif
}
uint32_t phy_ana_pga_gain_get(void)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
uint32_t rdata;
uint8_t rodata;
phy_ana_i2c_read(CFG_ANA_TX_REG_ADDR, &rdata, &rodata);
return (uint32_t)REG_FIELD_GET(TX_GPGA, rdata);
#else
return 3;
#endif
}
void phy_ana_tx_en(bool_t en)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
phy_ana_i2c_write(CFG_ANA_TOP_REG_ADDR, \
(en << TOP_EN_DAC_OFFSET) | \
(en << TOP_EN_TX_OFFSET), \
TOP_EN_DAC_MASK | \
TOP_EN_TX_MASK);
#else
(void)en;
#endif
}
void phy_ana_rx_en(bool_t en)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
phy_ana_i2c_write(CFG_ANA_TOP_REG_ADDR, \
(en << TOP_EN_ADC_OFFSET) | \
(en << TOP_EN_RX_OFFSET), \
TOP_EN_ADC_MASK | \
TOP_EN_RX_MASK);
#else
(void)en;
#endif
}
void phy_ana_enlic_en(uint8_t val)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
phy_ana_i2c_write(CFG_ANA_TOP_REG_ADDR, \
(val << TOP_ENLIC_OFFSET), \
TOP_ENLIC_MASK);
#else
(void)val;
#endif
}
void phy_ana_filter_set(uint8_t val)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
phy_ana_i2c_write(CFG_ANA_RX_REG_0_ADDR, \
(val << RX_SELC_OFFSET), \
RX_SELC_MASK);
#else
(void)val;
#endif
}
void phy_ana_dbg_print()
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
uint8_t rodata = 0;
uint32_t rdata = 0;
phy_ana_i2c_read(CFG_ANA_RX_REG_0_ADDR, &rdata, &rodata);
iot_printf("Analog rx0:0x%x, ", rdata);
phy_ana_i2c_read(CFG_ANA_TX_REG_ADDR, &rdata, &rodata);
iot_printf("tx6:0x%x, ", rdata);
phy_ana_i2c_read(CFG_ANA_TOP_REG_ADDR, &rdata, &rodata);
iot_printf("top10:0x%x\n", rdata);
#endif
}
void phy_ana_set_filter_init(uint32_t band_id)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t wdata = 0;
/* bandwidth filter set if cal ok */
uint32_t tmp = 0;
uint32_t end_tone = 0;
/* get end tone */
tmp = PHY_READ_REG(CFG_BB_R0_B0_TONE_ADDR);
end_tone = REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp);
tmp = PHY_READ_REG(CFG_BB_R1_B0_TONE_ADDR);
if (end_tone < REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp)) {
end_tone = REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp);
}
/* TODO: get filter value from const table */
if (end_tone <= 120) {
wdata = 63;
} else if (end_tone <= 230) {
wdata = (g_phy_ctxt.dep.band_8m_cap_set > 0) ?
g_phy_ctxt.dep.band_8m_cap_set : 63;
} else if (end_tone <= 400) {
wdata = 23; /* rx safe with 12M */
} else if (end_tone <= 500) {
wdata = (g_phy_ctxt.dep.band_15m_cap_set > 0) ?
g_phy_ctxt.dep.band_15m_cap_set : 18;
} else if (end_tone <= 743) {
wdata = (g_phy_ctxt.dep.band_20m_cap_set > 0) ?
g_phy_ctxt.dep.band_20m_cap_set : 14;
} else if (end_tone <= 1256) {
wdata = 9; /* rx safe with 30M */
} else {
wdata = 7; /* rx safe with 38M */
}
if (band_id == IOT_SUPPORT_TONE_MULTI_BAND021) {
wdata = 57; /* opt 6m spur */
}
phy_ana_filter_set(wdata);
iot_printf("%s bandwidth filter set value: %d.\n", \
__FUNCTION__, wdata);
#else
(void)band_id;
#endif
}
void phy_ana_init(uint32_t band_id)
{
#if HW_PLATFORM == HW_PLATFORM_FPGA
DaTxPara_t tp = {0};
DaRxPara_t rp = {0};
/* ada soft reset */
warm_rst_ada();
/* turn ada on */
phy_ada_enable(true);
/* DAC cfg */
tp.buf_size = 100;
tp.inv_en = true;
tp.path = DA_B_PATH_TONE;
phy_ada_tx_cfg(&tp);
/* ADC cfg */
rp.buf_size = MAC_RX_BUF_SIZE;
rp.sample_size = MAC_RX_SAMPLE_SIZE;
rp.mode = ADC_MODE_FORCE;
rp.thrd = 500;
rp.clk_inv_en = false;
rp.dmsb_inv_en = true;
phy_ada_rx_cfg(&rp);
(void)band_id;
#elif HW_PLATFORM > HW_PLATFORM_FPGA
/* config default RX ON regsiter */
phy_agc_gain_adj_dis(0xE7FFC0FF);
/* ana filter init */
phy_ana_set_filter_init(band_id);
/* fix tx gain */
#if (IOT_DTEST_ONLY_SUPPORT == 0)
uint32_t tx_pwr_enable = 0;
tx_pwr_enable = phy_get_pwr_ctl_en();
if (g_phy_ctxt.indep.tx_pwr_psd_fix_db || tx_pwr_enable) {
phy_ana_i2c_write(CFG_ANA_TX_REG_ADDR, \
3 << TX_GPGA_OFFSET, \
TX_GPGA_MASK);
} else {
phy_ana_i2c_write(CFG_ANA_TX_REG_ADDR, \
g_phy_ctxt.indep.tx_pga << TX_GPGA_OFFSET, \
TX_GPGA_MASK);
iot_printf("tx pga:%d\n", g_phy_ctxt.indep.tx_pga);
}
#else
phy_ana_i2c_write(CFG_ANA_TX_REG_ADDR, \
3 << TX_GPGA_OFFSET, \
TX_GPGA_MASK);
#endif
/* en adc and rx, disable dac and tx */
phy_ana_i2c_write(CFG_ANA_TOP_REG_ADDR, \
(1 << TOP_EN_ADC_OFFSET) | \
(1 << TOP_ENLIC_OFFSET) | \
(1 << TOP_EN_RX_OFFSET), \
TOP_EN_DAC_MASK | \
TOP_EN_ADC_MASK | \
TOP_ENLIC_MASK | \
TOP_EN_TX_MASK | \
TOP_EN_RX_MASK);
/* enable sadc */
phy_ana_sadc_enable(1);
/* 1:select the sadc data; 0:select adc 16-downsampling data */
phy_adc_mon_sel_set(true);
phy_bias_init_lic_io();
#else
(void)band_id;
#endif
}
void phy_sadc_pt_init()
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t reg_id = 0;
uint8_t rodata = 0;
uint32_t rdata = 0;
uint32_t wdata = 0;
uint32_t wmask = 0;
/*init granite top reg */
reg_id = CFG_ANA_TOP_REG_ADDR;
wdata = TOP_EN_SADC_MASK;
wmask = TOP_EN_SADC_MASK | TOP_ATB2PAD_EN_MASK | TOP_EN_ADC_MASK | TOP_EN_RX_MASK;
phy_ana_i2c_write(reg_id, wdata, wmask);
/* init granite sadc reg */
reg_id = CFG_ANA_SADC_REG_ADDR;
phy_ana_i2c_read(reg_id, &rdata, &rodata);
REG_FIELD_SET(SADC_EN_CAL, rdata, 0);
REG_FIELD_SET(SADC_EN, rdata, 1); //sadc_en = 1
REG_FIELD_SET(SADC_SEL_SCL_MUX, rdata, 0); //SADC_SEL_SCL_MUX = 0
REG_FIELD_SET(SADC_METER2PAD_EN_OVR, rdata, 0); //set 0000
REG_FIELD_SET(SADC_F_H, rdata, 4); //set 100
REG_FIELD_SET(SADC_CFG_DLY, rdata, 4); //set 100
REG_FIELD_SET(SADC_SAMPLE_SEL, rdata, 0); //set 0
REG_FIELD_SET(SADC_TIMER_DLY, rdata, 14); //sadc_timer_dly[3:0] = 1110
phy_ana_i2c_write(reg_id, rdata, ~0);
/* init granite bias reg 2*/
reg_id = CFG_ANA_BIAS_REG_2_ADDR;
phy_ana_i2c_read(reg_id, &rdata, &rodata);
REG_FIELD_SET(BIAS_EN_ICAL, rdata, 0); //en_ical=1
REG_FIELD_SET(BIAS_SEL_IC_TEST, rdata, 0); //sel_ic_test[7:0] = 0000_0000
// REG_FIELD_SET(BIAS_CAL, rdata, 16); //cal[4:0] = 1_0000
REG_FIELD_SET(BIAS_TRIM_ADCREF, rdata, 3);
REG_FIELD_SET(BIAS_TRIM_DCDC, rdata, 3);
REG_FIELD_SET(BIAS_TEST_VBG, rdata, 0); //BIAS_TEST_VBG
phy_ana_i2c_write(reg_id, rdata, ~0);
/* init granite ADC reg */
reg_id = CFG_ANA_ADC_REG_ADDR;
phy_ana_i2c_read(reg_id, &rdata, &rodata);
REG_FIELD_SET(ADC_ATB_SEL, rdata, 0);
phy_ana_i2c_write(reg_id, rdata, ~0);
#endif
}
/* get the gain table */
void phy_pgf_bq_pga_gain_get(uint16_t gain_idx, \
volatile uint8_t *pgf, \
volatile uint8_t *bq, \
volatile uint8_t *pga, \
volatile uint8_t *lna, \
volatile uint8_t *byphpf, \
volatile uint8_t *enord2, \
volatile uint8_t *bq_qvalue)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
IOT_ASSERT(gain_idx < 170);
tmp = all_mask_gain_table[gain_idx];
*pgf = (tmp & RX_GPGF_MASK) >> RX_GPGF_OFFSET;
*bq = (tmp & RX_GBQ_MASK) >> RX_GBQ_OFFSET;
*pga = (tmp & RX_GPGA_MASK) >> RX_GPGA_OFFSET;
*lna = (tmp & PHY_GAIN_GLNA_MASK) >> PHY_GAIN_GLNA_OFFSET;
*byphpf = (tmp & PHY_GAIN_BYPHPF_MASK) >> PHY_GAIN_BYPHPF_OFFSET;
*enord2 = (tmp & PHY_GAIN_HPF_ENORD2_MASK) >> PHY_GAIN_HPF_ENORD2_OFFSET;
(void)bq_qvalue;
#else
(void)gain_idx;
(void)pgf;
(void)bq;
(void)pga;
(void)lna;
(void)byphpf;
(void)enord2;
(void)bq_qvalue;
#endif
}
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