474 lines
18 KiB
C
Executable File
474 lines
18 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "os_utils.h"
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/* common includes */
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#include "iot_io.h"
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#include "iot_config.h"
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/* driver includes */
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#include "iot_clock.h"
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#include "iot_uart.h"
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#include "iot_system.h"
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/* debug includes*/
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#include "dbg_io.h"
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#include "platform.h"
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#include "encoding.h"
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#include "hw_reg_api.h"
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#include "ahb.h"
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#include "cpu.h"
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#include "dtest_printf.h"
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#include "pmp.h"
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#include "mmon.h"
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typedef enum {
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EXCEPTION_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED = 0,
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EXCEPTION_CAUSE_INSTRUCTION_ACCESS_FAULT = 1,
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EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION = 2,
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EXCEPTION_CAUSE_BREAKPOINT = 3,
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EXCEPTION_CAUSE_LOAD_ADDRESS_MISALIGNED = 4,
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EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT = 5,
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EXCEPTION_CAUSE_STORE_AMO_ACCESS_MISALIGNED = 6,
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EXCEPTION_CAUSE_STORE_AMO_ACCESS_FAULT = 7,
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EXCEPTION_CAUSE_ENV_CALL_FROM_U_MODE = 8,
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EXCEPTION_CAUSE_ENV_CALL_FROM_S_MODE = 9,
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EXCEPTION_CAUSE_RESERVED_10 = 10,
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EXCEPTION_CAUSE_ENV_CALL_FROM_M_MODE = 11,
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EXCEPTION_CAUSE_INSTRUCTION_PAGE_FAULT = 12,
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EXCEPTION_CAUSE_LOAD_PAGE_FAULT = 13,
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EXCEPTION_CAUSE_RESERVED_14 = 14,
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EXCEPTION_CAUSE_STORE_AMO_PAGE_FAULT = 15,
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EXCEPTION_CAUSE_RESERVED = 16, // >= 16
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} riscv_exception_cause_t;
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#define DTEST_PMP_TEST_SIZE 32
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#define DTEST_PMP_ALIGIN_SIZE 1024
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_00[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_01[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_02[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_03[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_04[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_05[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_06[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_07[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_08[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_09[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_10[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_11[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_12[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_13[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_14[DTEST_PMP_TEST_SIZE] = {0};
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volatile __attribute__((aligned(DTEST_PMP_ALIGIN_SIZE))) uint32_t protected_mem_region_15[DTEST_PMP_TEST_SIZE] = {0};
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/* the mcause code will be test */
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volatile uintptr_t g_mcause_set = 0;
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/* the mcause code get from exception handler */
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volatile uintptr_t g_mcause_get = 0;
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/* set 1 if exception occer */
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volatile int g_exception_occer = 0;
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uint32_t g_intc_trigger_cnt = 0;
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extern void kl3_trap_entry();
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extern int platform_init();
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extern void intc_handler(uint32_t cpu);
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extern uintptr_t kl3_handle_trap(uintptr_t mcause, uintptr_t epc, saved_registers *reg);
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void kl3_exception_handler(uintptr_t mcause)
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{
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uint32_t mbadaddr = 0;
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//disble global interrupt;
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__asm volatile ( "csrc mstatus,8" );
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__asm volatile ( "csrr %0, mbadaddr" : "=r"(mbadaddr));
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switch(mcause) {
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case EXCEPTION_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED:
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dprintf("mcause: 0x%02x[Instruction address misaligned]\n",
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mcause);
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break;
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case 0x1:
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dprintf("mcause: 0x%02x[Instruction access fault]\n",
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mcause);
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break;
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case 0x2:
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dprintf("mcause: 0x%02x[Illegal instruction]\n", mcause);
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break;
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case 0x3:
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dprintf("mcause: 0x%02x[Breakpoint]\n", mcause);
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break;
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case 0x4:
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dprintf("mcause: 0x%02x[Load address misaligned]\n",
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mcause);
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break;
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case EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT:
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dprintf("mcause: 0x%02x[Load access fault]\n", mcause);
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break;
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case 0x6:
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dprintf("mcause: 0x%02x[Store address misaligned]\n",
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mcause);
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break;
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case 0x7:
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dprintf("mcase: 0x%02x[Store access fault]\n", mcause);
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break;
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default:
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dprintf("mcause: 0x%02x\n", mcause);
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break;
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}
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}
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uintptr_t kl3_handle_trap(uintptr_t mcause,
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uintptr_t epc, saved_registers *reg)
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{
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if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
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intc_handler(cpu_get_mhartid());
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g_intc_trigger_cnt++;
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} else {
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kl3_exception_handler(mcause);
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//extern void exception_reg_dump(saved_registers *regs);
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//exception_reg_dump(reg);
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g_exception_occer = 1;
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g_mcause_get = mcause;
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void exception_test_loop(void);
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void (*pgm_start)(void) = (void*)exception_test_loop;
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pgm_start();
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}
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return epc;
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}
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uint32_t pmp_exec_test(uint32_t arg)
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{
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dprintf("%s running, arg:%d\n", __FUNCTION__, arg);
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return arg;
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}
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static int32_t pmp_test(void)
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{
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static int test_case = -1;
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static uint8_t pmp_idx = 0;
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uint32_t addr;
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uint32_t temp = 0x12345678;
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test_case++;
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iot_printf("\n");
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dprintf("case index:%d\n", test_case);
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switch (test_case) {
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case 0:
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/* mmon_disable_address_access() function test */
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dprintf("mmon_disable_address_access api test, disable read, "
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"write and execute \n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_disable_address_access(pmp_idx, addr, 32*4);
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dprintf("read option, should trigger load access fault\n");
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g_mcause_set = EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT;
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dprintf("pmp test data:0x%08x\n", protected_mem_region_00[15]);
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break;
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case 1:
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dprintf("write option, should trigger store access fault\n");
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g_mcause_set = EXCEPTION_CAUSE_STORE_AMO_ACCESS_FAULT;
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protected_mem_region_00[15] = 0x12345678;
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break;
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case 2:
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dprintf("execute option, should trigger instruction access fault\n");
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g_mcause_set = EXCEPTION_CAUSE_INSTRUCTION_ACCESS_FAULT;
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void (*pgm_start_1)(void) = (void*)protected_mem_region_00;
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pgm_start_1();
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break;
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case 3:
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/* mmon_set_address_access() function test */
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dprintf("mmon_disable_address_access api test, enable read, "
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"write and execute \n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_address_access(addr, 32*4,
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MMON_PRV_READ | MMON_PRV_WRITE | MMON_PRV_EXEC);
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dprintf("write option(0x%08x), should be normal\n", temp);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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protected_mem_region_00[15] = temp;
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break;
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case 4:
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dprintf("read option, should be normal\n");
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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dprintf("pmp test data:0x%08x\n", protected_mem_region_00[15]);
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if (protected_mem_region_00[15] != temp) {
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dprintf("!!!!! read value is not equal to write value !!!!!!\n");
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while(1);
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}
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break;
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case 5:
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dprintf("execute option, should trigger illegal instruction\n");
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protected_mem_region_00[0] = temp;
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g_mcause_set = EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION;
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void (*pgm_start_2)(void) = (void*)((uint32_t)protected_mem_region_00 + 2);
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pgm_start_2();
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break;
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case 6:
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/* read option disable test */
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dprintf("read option disable, should trigger load access fault\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_WRITE | MMON_PRV_EXEC);
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g_mcause_set = EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT;
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dprintf("pmp test data:0x%08x\n", *(uint32_t *)addr);
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break;
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case 7:
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/* write option disable test */
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dprintf("write option disable, should trigger store access fault\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_READ | MMON_PRV_EXEC);
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g_mcause_set = EXCEPTION_CAUSE_STORE_AMO_ACCESS_FAULT;
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// protected_mem_region_00[0] = 0x12345678;
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*(uint32_t *)addr = 0x12345678;
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break;
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case 8:
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/* execute option disable test */
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dprintf("execute option disable, should trigger instruction access fault\n");
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addr = (uint32_t)pmp_exec_test;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_READ | MMON_PRV_WRITE);
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g_mcause_set = EXCEPTION_CAUSE_INSTRUCTION_ACCESS_FAULT;
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pmp_exec_test(1);
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break;
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case 9:
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/* read option enable test */
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dprintf("read option enable, should be normal\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_READ);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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dprintf("pmp test data:0x%08x\n", *(uint32_t *)addr);
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break;
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case 10:
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/* write option enable test */
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dprintf("write option enable(read enable), should be normal\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_WRITE | MMON_PRV_READ);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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// protected_mem_region_00[0] = 0x12345678;
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*(uint32_t *)addr = 0x12345678;
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break;
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case 11:
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/* write option enable test */
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dprintf("write option enable(read disable), should trigger store fault\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_WRITE);
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g_mcause_set = EXCEPTION_CAUSE_STORE_AMO_ACCESS_FAULT;
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// protected_mem_region_00[0] = 0x12345678;
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*(uint32_t *)addr = 0x12345678;
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break;
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case 12:
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/* execute option enable test */
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dprintf("execute option enable, should be normal\n");
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addr = (uint32_t)pmp_exec_test;
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mmon_set_mode_address_access(pmp_idx, PMP_NA4, addr, 0, MMON_PRV_EXEC);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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pmp_exec_test(2);
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break;
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case 13:
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/* address matching mode test - OFF */
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dprintf("address matching OFF mode test, should be normal\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_OFF, addr, 0, 0);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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dprintf("pmp test data:0x%08x\n", *(uint32_t *)addr);
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pmp_exec_test(3);
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break;
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case 14:
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/* address matching mode test - PMP_TOR */
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dprintf("address matching TOR mode test, should trigger load access fault\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_TOR, addr, addr + 128, 0);
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g_mcause_set = EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT;
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dprintf("pmp test data:0x%08x\n", *(uint32_t *)addr);
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break;
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case 15:
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/* address matching mode test - PMP_NA4 */
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dprintf("address matching NA4 mode test\n");
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dprintf("in the previous test items, PMP_NA4 mode is used\n");
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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break;
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case 16:
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/* address matching mode test - PMP_NAPOT */
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dprintf("address matching NA_TOR mode test, should trigger load access fault\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(pmp_idx, PMP_NAPOT, addr, 8, 0);
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g_mcause_set = EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT;
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dprintf("pmp test data:0x%08x\n", *(uint32_t *)addr);
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break;
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case 17:
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/* pmp entry lock or unlock test */
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/* However, when the l field is 1, the m, s, and u modes must follow
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* the permission settings in the configuration register. When the
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* l field is 0, any operation matching this PMP entry in the M mode
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* will succeed, while the permission settings in the configuration
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* register must be followed in the s and u modes.
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*/
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dprintf("pmp entry lock test\n");
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dprintf("in the previous test items, lock is used.\n");
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dprintf("driver code must be modified for manually test unlock function\n");
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dprintf("expect that the exception will not be triggered "
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"where the exception should be triggered\n");
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break;
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case 18:
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/* priotity and matching logic test */
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/* pmp entry have static priority. small numbers have higher priority */
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dprintf("priotity and matching logic test, should be normal\n");
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addr = (uint32_t)protected_mem_region_00;
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mmon_set_mode_address_access(0, PMP_NAPOT, addr, 8, MMON_PRV_READ);
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mmon_set_mode_address_access(1, PMP_NAPOT, addr, 8, 0);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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dprintf("pmp test data:0x%08x\n", *(uint32_t *)addr);
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break;
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case (19 + 0):
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case (19 + 1):
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case (19 + 2):
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case (19 + 3):
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case (19 + 4):
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case (19 + 5):
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case (19 + 6):
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case (19 + 7):
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case (19 + 8):
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case (19 + 9):
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case (19 + 10):
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case (19 + 11):
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case (19 + 12):
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case (19 + 13):
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case (19 + 14):
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case (19 + 15):
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/* pmp entry base function test, there are 16 pmp entrys */
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/* close all of the pmp entry, prevent mutual influence */
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if (pmp_idx == 0) {
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dprintf("close all of the pmp entry\n");
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for (uint8_t i = 0; i < 16; i++) {
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mmon_set_mode_address_access(i, PMP_OFF, 0, 0, 0);
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}
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}
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addr = (uint32_t)protected_mem_region_00 + (pmp_idx * DTEST_PMP_ALIGIN_SIZE);
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dprintf("pmp entry base test, index:%d, protect addr:0x%08x\n", pmp_idx, addr);
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dprintf("\tprotect off, write should be normal\n");
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mmon_set_mode_address_access(pmp_idx, PMP_OFF, addr, 0, 0);
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g_mcause_set = EXCEPTION_CAUSE_RESERVED;
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*(uint32_t *)addr = temp;
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dprintf("\tset %p value to 0x%08x, read 0x%08x\n", addr, temp, *(uint32_t *)addr);
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dprintf("\tprotect on, write should trigger load access fault\n");
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mmon_set_mode_address_access(pmp_idx, PMP_NAPOT, addr, 8, 0);
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g_mcause_set = EXCEPTION_CAUSE_LOAD_ADDRESS_FAULT;
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dprintf("\tpmp test data:0x%08x\n", *(uint32_t *)addr);
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pmp_idx++;
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break;
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case (19 + 16):
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/* test complete */
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dprintf("all of the case have been completed\n");
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return 2;
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break;
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}
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return 0;
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}
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void exception_test_loop()
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{
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static uint32_t case_failed_cnt = 0;
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/* if exception occer, need check exception code get is same as set */
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if (g_exception_occer) {
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g_exception_occer = 0;
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if (g_mcause_get == g_mcause_set) {
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dcase_success();
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} else {
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dcase_failed();
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case_failed_cnt++;
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}
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}
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for (;;) {
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int32_t test_case_result = pmp_test();
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if (0 == test_case_result) { //case succeed
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dcase_success();
|
|
} else if (1 == test_case_result) { //case failed
|
|
/* when exception occer, it will not run here */
|
|
dcase_failed();
|
|
case_failed_cnt++;
|
|
} else if (2 == test_case_result) { //case run complete
|
|
dprintf("intc trigger cnt:%d\n", g_intc_trigger_cnt);
|
|
dprintf("case failed cnt:%d, pmp test %s\n", case_failed_cnt,
|
|
case_failed_cnt ? "failed" : "succeed");
|
|
dend();
|
|
for (;;) {
|
|
iot_delay_us(10000);
|
|
}
|
|
} else {
|
|
dprintf("!!!! logic exception !!!!!\n");
|
|
while(1);
|
|
}
|
|
iot_delay_us(10000);
|
|
}
|
|
}
|
|
|
|
static void cache_init()
|
|
{
|
|
cache_enable(AHB_CACHE_D0);
|
|
cache_set_buffer_mode(AHB_CACHE_D0, 1);
|
|
cache_enable(AHB_CACHE_D1);
|
|
cache_set_buffer_mode(AHB_CACHE_D1, 1);
|
|
}
|
|
|
|
int main(void)
|
|
{
|
|
cache_init();
|
|
|
|
/*install trap entry*/
|
|
write_csr(mtvec, &kl3_trap_entry);
|
|
|
|
dbg_uart_init();
|
|
|
|
dconfig();
|
|
dstart();
|
|
dversion();
|
|
|
|
/* Prevent being optimized */
|
|
dprintf("test memory 0 addr:%p\n", protected_mem_region_00);
|
|
dprintf("test memory 1 addr:%p\n", protected_mem_region_01);
|
|
dprintf("test memory 2 addr:%p\n", protected_mem_region_02);
|
|
dprintf("test memory 3 addr:%p\n", protected_mem_region_03);
|
|
dprintf("test memory 4 addr:%p\n", protected_mem_region_04);
|
|
dprintf("test memory 5 addr:%p\n", protected_mem_region_05);
|
|
dprintf("test memory 6 addr:%p\n", protected_mem_region_06);
|
|
dprintf("test memory 7 addr:%p\n", protected_mem_region_07);
|
|
dprintf("test memory 8 addr:%p\n", protected_mem_region_08);
|
|
dprintf("test memory 9 addr:%p\n", protected_mem_region_09);
|
|
dprintf("test memory 10 addr:%p\n", protected_mem_region_10);
|
|
dprintf("test memory 11 addr:%p\n", protected_mem_region_11);
|
|
dprintf("test memory 12 addr:%p\n", protected_mem_region_12);
|
|
dprintf("test memory 13 addr:%p\n", protected_mem_region_13);
|
|
dprintf("test memory 14 addr:%p\n", protected_mem_region_14);
|
|
dprintf("test memory 15 addr:%p\n", protected_mem_region_15);
|
|
|
|
exception_test_loop();
|
|
|
|
return 0;
|
|
}
|
|
|