71 lines
3.5 KiB
C
71 lines
3.5 KiB
C
/****************************************************************************
|
|
|
|
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
|
|
|
|
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
|
|
be copied by any method or incorporated into another program without
|
|
the express written consent of Aerospace C.Power. This Information or any portion
|
|
thereof remains the property of Aerospace C.Power. The Information contained herein
|
|
is believed to be accurate and Aerospace C.Power assumes no responsibility or
|
|
liability for its use in any way and conveys no license or title under
|
|
any patent or copyright and makes no representation or warranty that this
|
|
Information is free from patent or copyright infringement.
|
|
|
|
****************************************************************************/
|
|
#ifndef __RF_MAC_BB_COMMON_H__
|
|
#define __RF_MAC_BB_COMMON_H__
|
|
|
|
#include "rf_mac_reg.h"
|
|
|
|
/* rf mac common interrupt group0 */
|
|
#define RF_MAC_COMM_IRQ_EN_0 CFG_RF_MAC_COMMON_INT_REG_0_ADDR
|
|
#define RF_BB_COMM_IRQ_EN_0 CFG_RF_MAC_COMMON_INT_REG_1_ADDR
|
|
#define RF_MAC_COMM_IRQ_SET_0 CFG_RF_MAC_COMMON_INT_REG_2_ADDR
|
|
#define RF_BB_COMM_IRQ_SET_0 CFG_RF_MAC_COMMON_INT_REG_3_ADDR
|
|
#define RF_MAC_COMM_IRQ_CLR_0 CFG_RF_MAC_COMMON_INT_REG_4_ADDR
|
|
#define RF_BB_COMM_IRQ_CLR_0 CFG_RF_MAC_COMMON_INT_REG_5_ADDR
|
|
#define RF_MAC_COMM_IRQ_INTR_0 CFG_RF_MAC_COMMON_INT_REG_6_ADDR
|
|
#define RF_BB_COMM_IRQ_INTR_0 CFG_RF_MAC_COMMON_INT_REG_7_ADDR
|
|
#define RF_MAC_COMM_IRQ_MASK_0 CFG_RF_MAC_COMMON_INT_REG_8_ADDR
|
|
#define RF_BB_COMM_IRQ_MASK_0 CFG_RF_MAC_COMMON_INT_REG_9_ADDR
|
|
/* rf mac common interrupt group1 */
|
|
#define RF_MAC_COMM_IRQ_EN_1 CFG_RF_MAC_COMMON_INT_REG_10_ADDR
|
|
#define RF_BB_COMM_IRQ_EN_1 CFG_RF_MAC_COMMON_INT_REG_11_ADDR
|
|
#define RF_MAC_COMM_IRQ_SET_1 CFG_RF_MAC_COMMON_INT_REG_12_ADDR
|
|
#define RF_BB_COMM_IRQ_SET_1 CFG_RF_MAC_COMMON_INT_REG_13_ADDR
|
|
#define RF_MAC_COMM_IRQ_CLR_1 CFG_RF_MAC_COMMON_INT_REG_14_ADDR
|
|
#define RF_BB_COMM_IRQ_CLR_1 CFG_RF_MAC_COMMON_INT_REG_15_ADDR
|
|
#define RF_MAC_COMM_IRQ_INTR_1 CFG_RF_MAC_COMMON_INT_REG_16_ADDR
|
|
#define RF_BB_COMM_IRQ_INTR_1 CFG_RF_MAC_COMMON_INT_REG_17_ADDR
|
|
#define RF_MAC_COMM_IRQ_MASK_1 CFG_RF_MAC_COMMON_INT_REG_18_ADDR
|
|
#define RF_BB_COMM_IRQ_MASK_1 CFG_RF_MAC_COMMON_INT_REG_19_ADDR
|
|
|
|
/* common timer can be executed correctly */
|
|
#define RF_MAC_TEST_COMMON_TIMER_ID 0
|
|
/* common irq can be executed correctly */
|
|
#define RF_MAC_TEST_COMMON_IRQ_ID 1
|
|
/* single CMD can be executed correctly */
|
|
#define RF_MAC_TEST_SCHE_CMD_ID 2
|
|
/* cmdlist can be executed correctly */
|
|
#define RF_MAC_TEST_SCHE_CMDLIST_ID 3
|
|
/* debug can be executed correctly */
|
|
#define RF_MAC_TEST_DEBUG_HWQ_ID 6
|
|
/* TDMA flow can be executed correctly */
|
|
#define RF_MAC_TEST_TDMA_FLOW_ID 7
|
|
/* CSMA flow can be executed correctly */
|
|
#define RF_MAC_TEST_CSMA_FLOW_ID 8
|
|
/* RX flow can be executed correctly */
|
|
#define RF_MAC_TEST_RX_FLOW_ID 9
|
|
/* NTB over wrap test case id */
|
|
#define MAC_NTB_OVER_WRAP_TEST_ID 10
|
|
/* mac zc dtest */
|
|
#define RF_MAC_TEST_HW_ZC_ID 11
|
|
|
|
/* test case id */
|
|
#define RF_MAC_TEST_CASE_ID RF_MAC_TEST_CSMA_FLOW_ID
|
|
|
|
/* rf mac cpu and rf bb cpu common isr test bitmap */
|
|
#define RF_MAC_BB_COMM_ISR_TEST_BM 0xFFFFFFFF
|
|
|
|
#endif
|