475 lines
14 KiB
C
475 lines
14 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "os_task.h"
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#include "os_utils.h"
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/* common includes */
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#include "iot_io.h"
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#include "iot_dbglog_api.h"
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#include "iot_config.h"
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#include "iot_errno_api.h"
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/* driver includes */
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#include "apb_dma.h"
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#include "dma_hw.h"
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/* debug includes*/
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#include "dbg_io.h"
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/* driver includes */
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#include "cpu.h"
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#include "iot_gpio_api.h"
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#include "hw_reg_api.h"
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#include "ahb.h"
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#include "iot_irq.h"
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#include "iot_bitops_api.h"
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#include "iot_utils_api.h"
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#include "mac_sys_reg.h"
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#include "mac_int.h"
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/* check mac zc ntb fifo enable */
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#define DTEST_MAC_ZC_CHK_NTB_FIFO_ENA 1
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/* check mac zc local fifo enable */
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#define DTEST_MAC_ZC_CHK_LOCAL_FIFO_ENA 1
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/* 0: poll, 1: interrupt */
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#define DTSET_MAC_ZC_CHK_IS_INTR 1
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/* mac zc hw cap id */
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#define DTEST_MAC_ZC_CAP0 0
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#define DTEST_MAC_ZC_CAP1 1
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#define DTEST_MAC_ZC_CAP2 2
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#define DTEST_MAC_ZC_CAP3 3
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#define DTEST_MAC_ZC_CAP4 4
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#define DTEST_MAC_ZC_CAP5 5
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#define DTEST_MAC_ZC_CAP_CNT 6
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/* cap hw fifo depth */
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#define DTEST_MAC_ZC_HW_FIFO_CNT 8
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/* cap latch ntb/local value wait cnt, uint: 75MHZ */
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#define DTEST_MAC_ZC_SOLID_HIGH_NUM 200
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#define DTEST_MAC_ZC_SOLID_LOW_NUM 200
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/* mac zc period jitter max, same as KL1 */
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#define DTEST_MAC_ZC_PERIOD_JITTER_NTB 12500
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/* 50HZ period cap */
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#define DTEST_MAC_ZC_PERIOD_GAP_NTB 500000 /* 20ms */
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typedef struct _dtest_mac_zc_cap_info {
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uint32_t isr_entry_cnt;
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uint32_t isr_entry_backup;
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uint32_t ntb_ts;
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uint32_t local_ts;
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} dtest_mac_zc_cap_info_t;
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/* global */
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os_task_h dtest_mac_zc_task_h;
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iot_irq_t dtest_mac_isr_h_ext3;
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dtest_mac_zc_cap_info_t g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP_CNT] = {0};
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void dtest_mac_zc_sw_loop_delay(uint32_t delay)
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{
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uint32_t cnt = 0;
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while(cnt++ < (delay * 100 * 1000)) {
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__asm volatile ("nop\n");
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}
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}
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void dtest_mac_zc_hw_cap_enable(uint8_t cap_id, uint8_t is_ena)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
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* cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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REG_FIELD_SET(CFG_ZC0_CAP_ENABLE, tmp, !!is_ena);
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RGF_MAC_WRITE_REG(reg_addr, tmp);
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}
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void dtest_mac_zc_hw_cap_intr_num_set(uint8_t cap_id, uint8_t num)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
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* cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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REG_FIELD_SET(CFG_ZC0_CAP_NUM, tmp, num);
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RGF_MAC_WRITE_REG(reg_addr, tmp);
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}
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void dtest_mac_zc_hw_cap_sample_num_set(uint8_t cap_id, uint8_t num)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
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* cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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REG_FIELD_SET(CFG_ZC0_CAP_INTERVAL, tmp, num);
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RGF_MAC_WRITE_REG(reg_addr, tmp);
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}
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/* in_sel: 0 - default, stability start point;
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* 1 - not use. stability start point + SOLID_TIME
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*/
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void dtest_mac_zc_hw_in_sel_set(uint8_t cap_id, uint8_t in_sel)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
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* cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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REG_FIELD_SET(CFG_ZC0_IN_SEL, tmp, !!in_sel);
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RGF_MAC_WRITE_REG(reg_addr, tmp);
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}
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void dtest_mac_zc_hw_cap_edge_set(uint8_t cap_id, uint8_t is_fall_edge)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
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* cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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if (is_fall_edge) {
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REG_FIELD_SET(CFG_ZC0_EDGE_SEL, tmp, 1);
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} else {
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REG_FIELD_SET(CFG_ZC0_EDGE_SEL, tmp, 0);
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}
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RGF_MAC_WRITE_REG(reg_addr, tmp);
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}
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void dtest_mac_zc_hw_filter_set(uint8_t cap_id, uint16_t high, uint16_t low)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_SOLID_ADDR - CFG_ZC0_CAP_SOLID_ADDR)
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* cap_id) + CFG_ZC0_CAP_SOLID_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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REG_FIELD_SET(CFG_ZC0_SOLID_HIGH_CNT, tmp, high);
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REG_FIELD_SET(CFG_ZC0_SOLID_LOW_CNT, tmp, low);
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RGF_MAC_WRITE_REG(reg_addr, tmp);
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}
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uint32_t dtest_mac_zc_hw_cap_data_num_get(uint32_t cap_id, uint8_t is_ntb)
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{
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uint32_t tmp;
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uint32_t reg_addr;
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reg_addr = ((CFG_ZC1_CAP_FIFO_STS_ADDR - CFG_ZC0_CAP_FIFO_STS_ADDR)
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* cap_id) + CFG_ZC0_CAP_FIFO_STS_ADDR;
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tmp = RGF_MAC_READ_REG(reg_addr);
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if (is_ntb) {
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return REG_FIELD_GET(CFG_RO_NTB_ZC0_FIFO_DATA_NUM, tmp);
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} else {
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return REG_FIELD_GET(CFG_RO_LOCAL_ZC0_FIFO_DATA_NUM, tmp);
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}
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}
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uint32_t dtest_mac_zc_hw_cap_read(uint8_t cap_id, uint8_t is_ntb, uint8_t num,
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uint32_t *buf)
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{
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uint32_t reg_addr;
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uint32_t valid_num;
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uint32_t idx;
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if (is_ntb) {
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reg_addr = ((CFG_NTB_ZC1_CAP_FIFO_DATA_ADDR
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- CFG_NTB_ZC0_CAP_FIFO_DATA_ADDR) * cap_id) +
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CFG_NTB_ZC0_CAP_FIFO_DATA_ADDR;
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} else {
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reg_addr = ((CFG_LOCAL_ZC1_CAP_FIFO_DATA_ADDR
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- CFG_LOCAL_ZC0_CAP_FIFO_DATA_ADDR) * cap_id) +
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CFG_LOCAL_ZC0_CAP_FIFO_DATA_ADDR;
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}
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valid_num = dtest_mac_zc_hw_cap_data_num_get(cap_id, is_ntb);
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for (idx = 0; idx < min(valid_num, num); idx++) {
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buf[idx] = RGF_MAC_READ_REG(reg_addr);;
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}
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//iot_printf("cap:%d num:%d-%d\n", cap_id, valid_num, num);
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return idx;
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}
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uint32_t dtest_mac_zc_isr_status_get(void)
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{
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return RGF_MAC_READ_REG(CFG_MAC_INT_EXT_3_STS_ADDR);
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}
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void dtest_mac_zc_isr_clr(uint32_t status)
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{
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RGF_MAC_WRITE_REG(CFG_MAC_INT_EXT_3_CLR_ADDR, status);
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}
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void dtest_mac_zc_isr_enable(uint8_t bitmap)
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{
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uint32_t tmp;
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tmp = ((1 << DTEST_MAC_ZC_CAP_CNT) - 1) & bitmap;
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RGF_MAC_WRITE_REG(CFG_MAC_INT_EXT_3_ENA_ADDR, tmp);
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}
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void dtest_mac_zc_isr_start(void)
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{
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iot_interrupt_unmask(dtest_mac_isr_h_ext3);
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}
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void dtest_mac_zc_isr_stop(void)
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{
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iot_interrupt_mask(dtest_mac_isr_h_ext3);
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}
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uint32_t dtest_mac_zc_isr_handle(uint32_t vector, iot_addrword_t data)
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{
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(void)vector;
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(void)data;
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uint32_t intr_status;
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intr_status = dtest_mac_zc_isr_status_get();
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dtest_mac_zc_isr_clr(intr_status);
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if (intr_status & (1 << DTEST_MAC_ZC_CAP0)) {
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g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP0].isr_entry_cnt++;
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}
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if (intr_status & (1 << DTEST_MAC_ZC_CAP1)) {
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g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP1].isr_entry_cnt++;
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}
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if (intr_status & (1 << DTEST_MAC_ZC_CAP2)) {
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g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP2].isr_entry_cnt++;
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}
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if (intr_status & (1 << DTEST_MAC_ZC_CAP3)) {
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g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP3].isr_entry_cnt++;
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}
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if (intr_status & (1 << DTEST_MAC_ZC_CAP4)) {
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g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP4].isr_entry_cnt++;
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}
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if (intr_status & (1 << DTEST_MAC_ZC_CAP5)) {
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g_dtest_mac_zc_info[DTEST_MAC_ZC_CAP5].isr_entry_cnt++;
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}
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return 0;
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}
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void dtest_mac_zc_isr_init(void)
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{
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/* disable mac zc interrupt */
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dtest_mac_zc_isr_enable(0);
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/* clear all interrupt */
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dtest_mac_zc_isr_clr(0xFFFFFFFF);
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dtest_mac_isr_h_ext3 = iot_interrupt_create(HAL_VECTOR_MAC_3,
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HAL_INTR_PRI_7, (iot_addrword_t)NULL, dtest_mac_zc_isr_handle);
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iot_interrupt_set_cpu(dtest_mac_isr_h_ext3, HAL_INTR_CPU_0);
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iot_interrupt_attach(dtest_mac_isr_h_ext3);
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/* enable mac zc interrupt */
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dtest_mac_zc_isr_enable((1 << 6) - 1);
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}
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void dtest_mac_zc_hw_init(void)
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{
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uint32_t id;
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ahb_mac_enable();
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ahb_mac_reg_enable();
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ahb_mac_reset();
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ahb_mac_reg_reset();
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/* disable all mac zc cap */
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for (id = 0; id < DTEST_MAC_ZC_CAP_CNT; id++) {
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dtest_mac_zc_hw_cap_enable(id, 0);
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}
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dtest_mac_zc_isr_init();
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dtest_mac_zc_isr_start();
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/* gpio to mac zc signal map */ //TODO: chip need add
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for (id = 0; id < DTEST_MAC_ZC_CAP_CNT; id++) {
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dtest_mac_zc_hw_filter_set(id, DTEST_MAC_ZC_SOLID_HIGH_NUM,
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DTEST_MAC_ZC_SOLID_LOW_NUM);
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dtest_mac_zc_hw_cap_intr_num_set(id, 1);
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dtest_mac_zc_hw_cap_sample_num_set(id, 1);
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dtest_mac_zc_hw_in_sel_set(id, 0);
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dtest_mac_zc_hw_cap_edge_set(id, 0);
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}
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/* enable all mac zc cap */
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for (id = 0; id < DTEST_MAC_ZC_CAP_CNT; id++) {
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dtest_mac_zc_hw_cap_enable(id, 1);
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}
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iot_printf("%s\n", __FUNCTION__);
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}
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uint32_t dtest_mac_zc_entry(uint32_t loop)
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{
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uint8_t i, j;
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uint8_t ret, error_cnt;
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uint32_t run_cnt;
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uint32_t ntb_cnt, local_cnt;
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uint32_t ntb_data, local_data;
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dtest_mac_zc_cap_info_t *cur_cap;
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uint32_t period_buf[DTEST_MAC_ZC_HW_FIFO_CNT];
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uint32_t start_ts, cur_ts;
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iot_printf("dtest_mac_zc start....\n");
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/* init mac zc */
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dtest_mac_zc_hw_init();
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ret = 0;
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run_cnt = 0;
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start_ts = RGF_MAC_READ_REG(CFG_RD_LOCAL_TMR_ADDR);
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for (;;) {
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for (i = 0; i < DTEST_MAC_ZC_CAP_CNT; i++) {
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cur_cap = &g_dtest_mac_zc_info[i];
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#if DTSET_MAC_ZC_CHK_IS_INTR
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if ((uint32_t)(cur_cap->isr_entry_cnt - cur_cap->isr_entry_backup)
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< (DTEST_MAC_ZC_HW_FIFO_CNT >> 1)) {
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cur_ts = RGF_MAC_READ_REG(CFG_RD_LOCAL_TMR_ADDR);
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if ((uint32_t)(cur_ts - start_ts) > (5 * 1000 * 1000 * 25)) {
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iot_printf("[WARN]long time not interrupt\n");
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ret = 1;
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goto out;
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}
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continue;
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}
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start_ts = RGF_MAC_READ_REG(CFG_RD_LOCAL_TMR_ADDR);
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#endif
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iot_printf("cap:%d isr_cnt %u -> %u\n",
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i, cur_cap->isr_entry_backup, cur_cap->isr_entry_cnt);
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cur_cap->isr_entry_backup = cur_cap->isr_entry_cnt;
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#if DTEST_MAC_ZC_CHK_NTB_FIFO_ENA
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/* get ntb cap data */
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ntb_cnt = dtest_mac_zc_hw_cap_data_num_get(i, 1);
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if (ntb_cnt) {
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iot_printf("ntb_cnt=%d: ", ntb_cnt);
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for (j = 0; j < ntb_cnt; j++) {
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dtest_mac_zc_hw_cap_read(i, 1, 1, &ntb_data);
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period_buf[j] = (uint32_t)(ntb_data - cur_cap->ntb_ts);
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iot_printf("%u, ", ntb_data);
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cur_cap->ntb_ts = ntb_data;
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}
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iot_printf("\n");
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error_cnt = 0;
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iot_printf("ntb_period: ");
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for (j = 0; j < ntb_cnt; j++) {
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iot_printf("%u, ", period_buf[j]);
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if (IOT_ABS((int32_t)(period_buf[j]
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- DTEST_MAC_ZC_PERIOD_GAP_NTB))
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> DTEST_MAC_ZC_PERIOD_JITTER_NTB) {
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error_cnt++;
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ret = 1;
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}
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}
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iot_printf("\n");
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if (error_cnt) {
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iot_printf("[WARN]ntb_period_err %u\n", error_cnt);
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}
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}
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#else
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(void)ntb_cnt;
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(void)ntb_data;
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#endif
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#if DTEST_MAC_ZC_CHK_LOCAL_FIFO_ENA
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/* get local cap data */
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local_cnt = dtest_mac_zc_hw_cap_data_num_get(i, 0);
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if (local_cnt) {
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iot_printf("local_cnt=%d, ", local_cnt);
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for (j = 0; j < local_cnt; j++) {
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dtest_mac_zc_hw_cap_read(i, 0, 1, &local_data);
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period_buf[j] = (uint32_t)(local_data - cur_cap->local_ts);
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iot_printf("%u, ", local_data);
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cur_cap->local_ts = local_data;
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}
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iot_printf("\n");
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error_cnt = 0;
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iot_printf("local_period: ");
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for (j = 0; j < local_cnt; j++) {
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iot_printf("%u, ", period_buf[j]);
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if (IOT_ABS((int32_t)(period_buf[j]
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- DTEST_MAC_ZC_PERIOD_GAP_NTB))
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> DTEST_MAC_ZC_PERIOD_JITTER_NTB) {
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error_cnt++;
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ret = 1;
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}
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}
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iot_printf("\n");
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if (error_cnt) {
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iot_printf("[WARN]local_period_err %u\n", error_cnt);
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}
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}
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#else
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(void)local_cnt;
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(void)local_data;
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#endif
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#if (DTEST_MAC_ZC_CHK_NTB_FIFO_ENA && DTEST_MAC_ZC_CHK_NTB_FIFO_ENA)
|
|
if (!ntb_cnt && !local_cnt) {
|
|
continue;
|
|
}
|
|
|
|
/* check ntb and local fifo count */
|
|
if (ntb_cnt != local_cnt) {
|
|
iot_printf("[WARN]cap%d ntb/local fifo cnt not match. "
|
|
"ntb_cnt:%u, local_cnt:%u\n",
|
|
i, ntb_cnt, local_cnt);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
run_cnt++;
|
|
#if !DTSET_MAC_ZC_CHK_IS_INTR
|
|
dtest_mac_zc_sw_loop_delay(2);
|
|
#endif
|
|
if (run_cnt >= loop) {
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
out:
|
|
iot_printf("dtest_mac_zc test %d\n", ret);
|
|
return ret;
|
|
}
|