989 lines
36 KiB
C
989 lines
36 KiB
C
/****************************************************************************
|
|
|
|
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
|
|
|
|
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
|
|
be copied by any method or incorporated into another program without
|
|
the express written consent of Aerospace C.Power. This Information or any portion
|
|
thereof remains the property of Aerospace C.Power. The Information contained herein
|
|
is believed to be accurate and Aerospace C.Power assumes no responsibility or
|
|
liability for its use in any way and conveys no license or title under
|
|
any patent or copyright and makes no representation or warranty that this
|
|
Information is free from patent or copyright infringement.
|
|
|
|
****************************************************************************/
|
|
#include "rf_mac_tx.h"
|
|
#include "iot_config.h"
|
|
#include "mpdu_frame.h"
|
|
#include "iot_io.h"
|
|
#include "hw_reg_api.h"
|
|
#include "rfplc_reg_base.h"
|
|
#include "rf_mac_reg.h"
|
|
#include "mac_sys_reg.h"
|
|
#include "ahb.h"
|
|
#include "iot_gptmr_api.h"
|
|
#include "command_list.h"
|
|
#include "iot_pkt.h"
|
|
#include "iot_irq.h"
|
|
#include "iot_clock.h"
|
|
#include "mac_rf_isr.h"
|
|
#include "mac_rf_sched_hw.h"
|
|
#include "mac_sched_hw.h"
|
|
#include "mac_rf_vdev.h"
|
|
#include "rf_mac_common.h"
|
|
#include "rf_mac_int.h"
|
|
#include "rf_mac_reg.h"
|
|
#include "phy_rf_chn.h"
|
|
#include "phy_rf_init.h"
|
|
#include "dbg_msg_pop.h"
|
|
#include "plc_protocol.h"
|
|
|
|
rf_tx_ctxt_t glb_rf_tx = { 0 };
|
|
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp1;
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp2;
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp3;
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp4;
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp5;
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp6;
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp7;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp1;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp2;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp3;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp4;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp5;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp6;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp7;
|
|
|
|
rf_tx_mpdu_start rf_mpdu_start_tmp;
|
|
rf_tx_mpdu_end rf_mpdu_end_tmp;
|
|
rf_tx_pb_start rf_pb_start_tmp;
|
|
rf_tx_dummy_node rf_dummy_tmp;
|
|
uint8_t rf_pb_buf[520] = { 0 };
|
|
iot_irq_t isr_rf_mac;
|
|
|
|
/* cmdlist */
|
|
#define CMDLIST_CMD_NUM 8
|
|
hw_sched_cmd_t cmd_list_1[CMDLIST_CMD_NUM] = { 0 };
|
|
hw_sched_cmd_t cmd_list_2[CMDLIST_CMD_NUM] = { 0 };
|
|
uint32_t g_cmd_num = 0;
|
|
uint8_t cmd_list_flag = 0;
|
|
uint32_t pb_period_1 = 0;
|
|
uint32_t pb_period_2 = 0;
|
|
uint32_t alert_cnt = 0, alert_sts = 0;
|
|
uint32_t tx_comp_irq_cnt = 0;
|
|
uint32_t tx_comp_irq_happen = 0;
|
|
uint32_t rx_comp_irq_cnt = 0;
|
|
uint32_t rx_comp_irq_happen = 0;
|
|
|
|
void rf_mac_cmdlist_cfg();
|
|
void mac_rf_sched_set_bp_ahead_alert(mac_rf_vdev_t *rf_vdev, uint16_t ahead_ms);
|
|
|
|
void rf_tx_ctxt_init()
|
|
{
|
|
glb_rf_tx.rf_mpdu_start = &rf_mpdu_start_tmp;
|
|
glb_rf_tx.rf_mpdu_end = &rf_mpdu_end_tmp;
|
|
glb_rf_tx.rf_pb_start = &rf_pb_start_tmp;
|
|
glb_rf_tx.rf_dummy = &rf_dummy_tmp;
|
|
|
|
glb_rf_tx.rf_mpdu_start1 = &rf_mpdu_start_tmp1;
|
|
glb_rf_tx.rf_mpdu_start2 = &rf_mpdu_start_tmp2;
|
|
glb_rf_tx.rf_mpdu_start3 = &rf_mpdu_start_tmp3;
|
|
glb_rf_tx.rf_mpdu_start4 = &rf_mpdu_start_tmp4;
|
|
glb_rf_tx.rf_mpdu_start5 = &rf_mpdu_start_tmp5;
|
|
glb_rf_tx.rf_mpdu_start6 = &rf_mpdu_start_tmp6;
|
|
glb_rf_tx.rf_mpdu_start7 = &rf_mpdu_start_tmp7;
|
|
|
|
glb_rf_tx.rf_mpdu_end1 = &rf_mpdu_end_tmp1;
|
|
glb_rf_tx.rf_mpdu_end2 = &rf_mpdu_end_tmp2;
|
|
glb_rf_tx.rf_mpdu_end3 = &rf_mpdu_end_tmp3;
|
|
glb_rf_tx.rf_mpdu_end4 = &rf_mpdu_end_tmp4;
|
|
glb_rf_tx.rf_mpdu_end5 = &rf_mpdu_end_tmp5;
|
|
glb_rf_tx.rf_mpdu_end6 = &rf_mpdu_end_tmp6;
|
|
glb_rf_tx.rf_mpdu_end7 = &rf_mpdu_end_tmp7;
|
|
}
|
|
|
|
uint32_t rf_mac_tx_isr(uint32_t vector, iot_addrword_t data)
|
|
{
|
|
// TODO: debug isr interrupt.
|
|
(void)vector;
|
|
(void)data;
|
|
uint32_t txrx_ctl, irq_sts, txq_map = 0, ring_map = 0;
|
|
uint32_t hw_sts = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_6_ADDR);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, hw_sts);
|
|
uint32_t sw_sts = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_26_ADDR);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_24_ADDR, sw_sts);
|
|
|
|
if (hw_sts & (1 << RF_MAC_ISR_BC_ALERT_ID)) {
|
|
alert_cnt++;
|
|
alert_sts = 1;
|
|
txrx_ctl = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
|
|
REG_FIELD_SET(RF_MAC_EARLY_STOP_START, txrx_ctl, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, txrx_ctl);
|
|
}
|
|
/* inside the alert interrupt, disable cmdList */
|
|
if (hw_sts & (1 << RF_MAC_ISR_EARLY_STOP_DONE_ID)) {
|
|
if (alert_sts) {
|
|
alert_sts = 0;
|
|
rf_mac_cmdlist_cfg();
|
|
}
|
|
}
|
|
|
|
if (sw_sts & (1 << RF_MAC_SW_ISR_TX_MPDU_COMPLETE)) {
|
|
irq_sts = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_16_ADDR);
|
|
txq_map = irq_sts & RF_MAC_INT_HWQ_BIT_MASK;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, txq_map);
|
|
tx_comp_irq_cnt++;
|
|
tx_comp_irq_happen = 1;
|
|
|
|
for (uint32_t hwq_id = 0; txq_map && hwq_id < 7; hwq_id++) {
|
|
if ((0x1 << hwq_id) & txq_map) {
|
|
if (hwq_id == 0) {
|
|
glb_rf_tx.rf_mpdu_start->tx_status->tx_done = 0;
|
|
glb_rf_tx.rf_mpdu_start->notify_hw_tx_done = 0;
|
|
} else if(hwq_id == 1) {
|
|
glb_rf_tx.rf_mpdu_start1->tx_status->tx_done = 0;
|
|
glb_rf_tx.rf_mpdu_start1->notify_hw_tx_done = 0;
|
|
} else if(hwq_id == 2) {
|
|
glb_rf_tx.rf_mpdu_start2->tx_status->tx_done = 0;
|
|
glb_rf_tx.rf_mpdu_start2->notify_hw_tx_done = 0;
|
|
} else if(hwq_id == 3) {
|
|
glb_rf_tx.rf_mpdu_start3->tx_status->tx_done = 0;
|
|
glb_rf_tx.rf_mpdu_start3->notify_hw_tx_done = 0;
|
|
} else if(hwq_id == 4) {
|
|
glb_rf_tx.rf_mpdu_start4->tx_status->tx_done = 0;
|
|
glb_rf_tx.rf_mpdu_start4->notify_hw_tx_done = 0;
|
|
} else if(hwq_id == 5) {
|
|
glb_rf_tx.rf_mpdu_start5->tx_status->tx_done = 0;
|
|
glb_rf_tx.rf_mpdu_start5->notify_hw_tx_done = 0;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (sw_sts & (1 << RF_MAC_SW_ISR_RX_MPDU_COMPLETE)) {
|
|
irq_sts = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_16_ADDR);
|
|
ring_map = irq_sts & RF_MAC_INT_RX_RING_BIT_MASK;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, ring_map);
|
|
rx_comp_irq_cnt++;
|
|
rx_comp_irq_happen = 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rf_mac_isr_start1(uint32_t irq_id)
|
|
{
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, 0);
|
|
|
|
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR);
|
|
tmp |= 1 << irq_id;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR, tmp);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR);
|
|
tmp |= 1 << irq_id;
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR, tmp);
|
|
}
|
|
|
|
void rf_mac_interrupt_init()
|
|
{
|
|
isr_rf_mac = iot_interrupt_create(HAL_VECTOR_RFMAC_INT0,
|
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, rf_mac_tx_isr);
|
|
iot_interrupt_attach(isr_rf_mac);
|
|
iot_interrupt_unmask(isr_rf_mac);
|
|
}
|
|
|
|
void rf_mac_init()
|
|
{
|
|
ahb_mac_enable();
|
|
ahb_mac_reg_enable();
|
|
ahb_rfmac_enable();
|
|
ahb_rfmac_reg_enable();
|
|
rf_mac_free_ntb_enable();
|
|
}
|
|
|
|
uint32_t rf_mac_tx_init()
|
|
{
|
|
/* init dbg msg */
|
|
dbg_msg_print_init();
|
|
phy_rf_band_info_init(PHY_RF_BAND_NSG);
|
|
rf_tx_ctxt_init();
|
|
rf_mac_init();
|
|
/* plccpu and bbcpu sync init, rf rxdc disable */
|
|
phy_rf_init(PLC_PROTO_TYPE_SG, PHY_RF_OPTION1_1M,
|
|
RF_CHANNEL_ID_1, 1, 0, 0);
|
|
return 0;
|
|
}
|
|
|
|
void rf_tx_common_init()
|
|
{
|
|
rf_mac_tx_init();
|
|
|
|
glb_rf_tx.rf_pb_start->pb_buf_addr = (uint32_t)rf_pb_buf;
|
|
|
|
#if SUPPORT_SMART_GRID
|
|
sg_sof_pb_hdr_t *hdr =
|
|
(sg_sof_pb_hdr_t *)&glb_rf_tx.rf_pb_start->sof_pb_header; //pb header
|
|
hdr->mac_frame_end = 1;
|
|
hdr->mac_frame_start = 1;
|
|
hdr->seq = 0;
|
|
#endif
|
|
/* init dummy */
|
|
glb_rf_tx.rf_dummy->desc_type = 2;
|
|
glb_rf_tx.rf_dummy->next = NULL;
|
|
|
|
glb_rf_tx.rf_mpdu_start->next = NULL;
|
|
glb_rf_tx.rf_mpdu_start->pb = glb_rf_tx.rf_pb_start;
|
|
glb_rf_tx.rf_mpdu_start->tx_status = glb_rf_tx.rf_mpdu_end;
|
|
}
|
|
|
|
uint32_t rf_mac_tx_mpdu_start(rf_tx_mpdu_start *rf_mpdu,
|
|
rf_mac_cfg_info_t *rf_tx_cfg)
|
|
{
|
|
rf_mpdu->desc_type = 0;
|
|
rf_mpdu->tx_fl = 2 * 25000; //2ms
|
|
rf_mpdu->notify_hw_tx_done = 0;
|
|
rf_mpdu->need_ack = 0;
|
|
|
|
rf_mpdu->next = NULL;
|
|
rf_mpdu->pb = glb_rf_tx.rf_pb_start;
|
|
rf_mpdu->tx_status = glb_rf_tx.rf_mpdu_end;
|
|
rf_mpdu->tx_status->tx_done = 0;
|
|
rf_mpdu->tx_status->tx_ok = 0;
|
|
|
|
rf_mpdu->phr_mcs = rf_tx_cfg->phr_mcs;
|
|
rf_mpdu->blkz = rf_tx_cfg->pld_blkz;
|
|
rf_mpdu->pld_mcs = rf_tx_cfg->pld_mcs;
|
|
rf_mpdu->option = rf_tx_cfg->option;
|
|
|
|
frame_control_t *phr = (frame_control_t *)&rf_mpdu->phr0;
|
|
phr->delimiter_type = rf_tx_cfg->delimiter;
|
|
phr->network_type = 0;
|
|
phr->nid = rf_tx_cfg->nid;
|
|
switch (rf_tx_cfg->delimiter) {
|
|
case FC_DELIM_BEACON:
|
|
{
|
|
phr->vf.rf_bcn.src_tei = 1;
|
|
phr->vf.rf_bcn.mcs = rf_tx_cfg->pld_mcs;
|
|
phr->vf.rf_bcn.pb_sz_idx = rf_tx_cfg->pld_blkz;
|
|
phr->vf.rf_bcn.resv0 = 0;
|
|
phr->vf.rf_bcn.version = 0;
|
|
phr->vf.rf_bcn.fccs = 0;
|
|
break;
|
|
}
|
|
case FC_DELIM_SOF:
|
|
{
|
|
phr->vf.rf_sof.src_tei = 1;
|
|
phr->vf.rf_sof.dst_tei = 2;
|
|
phr->vf.rf_sof.lid = 0;
|
|
phr->vf.rf_sof.frame_len = 0;
|
|
phr->vf.rf_sof.pb_sz_idx = rf_tx_cfg->pld_blkz;
|
|
phr->vf.rf_sof.resv0 = 0;
|
|
phr->vf.rf_sof.bcast = rf_tx_cfg->is_bcast & 0x1;
|
|
phr->vf.rf_sof.retry = 0;
|
|
phr->vf.rf_sof.encry = 0;
|
|
phr->vf.rf_sof.mcs = rf_tx_cfg->pld_mcs;
|
|
phr->vf.rf_sof.resv1 = 0;
|
|
phr->vf.rf_sof.version = 0;
|
|
phr->vf.rf_sof.fccs = 0;
|
|
break;
|
|
}
|
|
default:
|
|
IOT_ASSERT(0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
uint32_t rf_mac_common_timer_test()
|
|
{
|
|
uint32_t timer_start = 0, timer_end = 0, tmp = 0;
|
|
int64_t time_span = 0;
|
|
|
|
uint32_t timer_id = 0;
|
|
uint32_t rf_time_us = 5000;
|
|
/* clear all status */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_4_ADDR, 0xffffffff);
|
|
|
|
for (uint32_t i = 0; i < 32; i++) {
|
|
timer_id = i;
|
|
/* disable all common timer */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_0_ADDR, 0);
|
|
|
|
/* enable timer */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_TIMER_REG_0_ADDR);
|
|
tmp |= (1 << timer_id);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_0_ADDR, tmp);
|
|
|
|
/* mask timer */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_TIMER_REG_8_ADDR);
|
|
tmp |= (1 << timer_id);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_8_ADDR, tmp);
|
|
|
|
/* set time */
|
|
RF_MAC_WRITE_REG((CFG_RF_MAC_COMMON_TIMER_REG_10_ADDR + timer_id * 4),
|
|
(rf_time_us * 25));
|
|
|
|
/* start timer */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_TIMER_REG_2_ADDR);
|
|
tmp |= (1 << timer_id);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_2_ADDR, tmp);
|
|
timer_start = rf_mac_get_ntb();
|
|
|
|
do {
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_COMMON_TIMER_REG_6_ADDR);
|
|
} while (!tmp);
|
|
timer_end = rf_mac_get_ntb();
|
|
/* clear status */
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_4_ADDR, (1 << timer_id));
|
|
|
|
time_span = timer_end - timer_start;
|
|
if (time_span < 0) { // wrap around
|
|
time_span = (0x100000000LL) - timer_end + timer_start;
|
|
}
|
|
|
|
iot_printf("rf common timer id:%d, stats:0x%x, rftime:%lu/us, "
|
|
"ntb_dlt:%lu/ntb, ntb_us:%lu/us\n", timer_id, tmp, rf_time_us,
|
|
(uint32_t)time_span, ((uint32_t)time_span/25));
|
|
|
|
iot_delay_us(1000);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rf_mac_mem_dump(uint32_t *word_ptr, uint32_t word_cnt)
|
|
{
|
|
|
|
for (uint32_t j = 0; j < word_cnt; j++) {
|
|
iot_printf("0x%08x:", (uint32_t)(word_ptr + j));
|
|
iot_printf("0x%08x\n", (uint32_t)*(word_ptr + j));
|
|
}
|
|
return;
|
|
}
|
|
|
|
void rf_mac_print_reg(uint32_t addr, uint32_t val)
|
|
{
|
|
iot_printf("RF_MAC_WRITE_REG addr:0x%08x, val:0x%08x\n", \
|
|
(RF_MAC_BASEADDR + addr), val);
|
|
}
|
|
|
|
void rf_mac_write_reg(uint32_t addr, uint32_t val)
|
|
{
|
|
RF_MAC_WRITE_REG(addr, val);
|
|
rf_mac_print_reg(addr, val);
|
|
}
|
|
|
|
uint32_t rf_mac_cmd_test()
|
|
{
|
|
uint32_t tmp, cur_ntb, priend_ms = 0, cmd_time_ms = 300 * 25000;
|
|
hw_sched_cmd_t cmd[8] = { 0 };
|
|
uint32_t sel_bit_map, txq_bit_map, remain_time, cmd_cnt = 8;
|
|
|
|
/* init cmdlist */
|
|
for (uint32_t i = 0; i < cmd_cnt; i++) {
|
|
cmd[i].rf_tx_q_en_bm = 1 << i;
|
|
priend_ms += cmd_time_ms;
|
|
cmd[i].rf_end_t = priend_ms;
|
|
}
|
|
rf_mac_mem_dump((uint32_t *)cmd, 16);
|
|
/* set cmd num */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_CMD_NUM, tmp, cmd_cnt);
|
|
rf_mac_write_reg(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
|
|
/* alert time 60ms */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_BCN_ALERT_AHEAD_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_ALERT_TIME, tmp, 5 * 25000);
|
|
rf_mac_write_reg(CFG_RF_MAC_BCN_ALERT_AHEAD_ADDR, tmp);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHED_PTR_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_START_PTR, tmp, (uint32_t)cmd);
|
|
rf_mac_write_reg(CFG_RF_MAC_SCHED_PTR_ADDR, tmp);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_CMDLIST_LENGTH_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_LENGTH_CPU2, tmp, priend_ms);
|
|
rf_mac_write_reg(CFG_RF_MAC_CMDLIST_LENGTH_ADDR, tmp);
|
|
|
|
/* get current ntb */
|
|
cur_ntb = rf_mac_get_ntb();
|
|
|
|
/* set schedule start ntb */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_BCN_START_NTB_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_START_NTB, tmp, cur_ntb + 25000);
|
|
rf_mac_write_reg(CFG_RF_MAC_BCN_START_NTB_ADDR, tmp);
|
|
|
|
/* schedule enable */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CFG_SCH_EN, tmp, 1);
|
|
rf_mac_write_reg(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
|
|
/* schedule start */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CFG_SCH_START, tmp, 1);
|
|
rf_mac_write_reg(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
|
|
while(1) {
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
|
|
sel_bit_map = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
|
|
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
|
|
remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
|
|
iot_printf("sel_bitmap:0x%x, curbitmap:0x%x, remain time:%lu\n",
|
|
sel_bit_map, txq_bit_map, remain_time);
|
|
iot_delay_us(5);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rf_mac_sched_init(uint32_t cmd_num, uint32_t cmd_offset_ntb)
|
|
{
|
|
uint32_t i;
|
|
g_cmd_num = cmd_num;
|
|
pb_period_1 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
cmd_list_1[i].rf_tx_q_en_bm = 1 << i;
|
|
pb_period_1 += cmd_offset_ntb;
|
|
cmd_list_1[i].rf_end_t = pb_period_1;
|
|
iot_printf("cmdlist1 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_1[i].rf_tx_q_en_bm, cmd_list_1[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_1, 16);
|
|
pb_period_2 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
cmd_list_2[i].rf_tx_q_en_bm = 1 << i;
|
|
pb_period_2 += cmd_offset_ntb;
|
|
cmd_list_2[i].rf_end_t = pb_period_2;
|
|
iot_printf("cmdlist2 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_2[i].rf_tx_q_en_bm, cmd_list_2[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_2, 16);
|
|
}
|
|
|
|
void rf_mac_cmdlist_cfg()
|
|
{
|
|
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_BCN_ALERT_AHEAD_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_ALERT_TIME, tmp, MAC_MS_TO_NTB(60));
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_BCN_ALERT_AHEAD_ADDR, tmp);
|
|
|
|
if (cmd_list_flag == 0) {
|
|
cmd_list_flag = 1;
|
|
/* set cnt */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_CMD_NUM, tmp, g_cmd_num);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
|
|
/* set ptr */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHED_PTR_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_START_PTR, tmp, (uint32_t)cmd_list_1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SCHED_PTR_ADDR, tmp);
|
|
|
|
/* set length */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_CMDLIST_LENGTH_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_LENGTH_CPU2, tmp, pb_period_1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_CMDLIST_LENGTH_ADDR, tmp);
|
|
|
|
} else {
|
|
cmd_list_flag = 0;
|
|
/* set cnt */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_CMD_NUM, tmp, g_cmd_num);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
|
|
/* set ptr */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHED_PTR_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_START_PTR, tmp, (uint32_t)cmd_list_2);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SCHED_PTR_ADDR, tmp);
|
|
|
|
/* set length */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_CMDLIST_LENGTH_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_LENGTH_CPU2, tmp, pb_period_2);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_CMDLIST_LENGTH_ADDR, tmp);
|
|
}
|
|
|
|
/* get current ntb */
|
|
uint32_t cur_ntb = rf_mac_get_ntb();
|
|
/* set schedule start ntb */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_BCN_START_NTB_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CMDLIST_START_NTB, tmp, cur_ntb);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_BCN_START_NTB_ADDR, tmp);
|
|
|
|
iot_printf("%s, startntb:0x%x, flag:%d, alertcnt:%d\n",
|
|
__FUNCTION__, cur_ntb, cmd_list_flag, alert_cnt);
|
|
/* schedule enable */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CFG_SCH_EN, tmp, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
/* schedule start */
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SCHEDULE_ADDR);
|
|
REG_FIELD_SET(RF_MAC_CFG_SCH_START, tmp, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SCHEDULE_ADDR, tmp);
|
|
}
|
|
|
|
uint32_t rf_mac_cmdlist_test()
|
|
{
|
|
uint32_t tmp;
|
|
uint32_t sel_bit_map, txq_bit_map, remain_time;
|
|
uint32_t cmd_offset_ntb = 100 * 25000; // 100ms
|
|
|
|
/* init irq */
|
|
rf_mac_interrupt_init();
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_10_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_18_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_24_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_20_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_28_ADDR, 0xffffffff);
|
|
|
|
/* generate cmdlist */
|
|
rf_mac_sched_init(8, cmd_offset_ntb);
|
|
/* config cmdlist */
|
|
rf_mac_cmdlist_cfg();
|
|
|
|
while(1) {
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
|
|
sel_bit_map = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
|
|
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
|
|
remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
|
|
iot_printf("sel_bitmap:0x%x, curbitmap:0x%x, remain time:%lu, "
|
|
"alertcnt:%d\n", sel_bit_map, txq_bit_map, remain_time, alert_cnt);
|
|
iot_delay_us(5);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rf_mac_tdma_sched_init(uint32_t cmd_num, uint32_t cmd_offset_ntb)
|
|
{
|
|
uint32_t i;
|
|
g_cmd_num = cmd_num;
|
|
pb_period_1 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
if (0 == i) {
|
|
cmd_list_1[i].rf_tx_q_en_bm = 1 << i;
|
|
} else {
|
|
cmd_list_1[i].rf_tx_q_en_bm = 0;
|
|
}
|
|
pb_period_1 += cmd_offset_ntb;
|
|
cmd_list_1[i].rf_end_t = pb_period_1;
|
|
iot_printf("cmdlist1 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_1[i].rf_tx_q_en_bm, cmd_list_1[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_1, 16);
|
|
pb_period_2 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
if (0 == i) {
|
|
cmd_list_2[i].rf_tx_q_en_bm = 1 << i;
|
|
} else {
|
|
cmd_list_2[i].rf_tx_q_en_bm = 0;
|
|
}
|
|
pb_period_2 += cmd_offset_ntb;
|
|
cmd_list_2[i].rf_end_t = pb_period_2;
|
|
iot_printf("cmdlist2 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_2[i].rf_tx_q_en_bm, cmd_list_2[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_2, 16);
|
|
}
|
|
|
|
void rf_mac_tdma_flow_test(rf_mac_cfg_info_t *rf_mac_cfg)
|
|
{
|
|
uint32_t tmp, sel_bit_map, txq_bit_map, remain_time, ptr, cur_ntb;
|
|
uint32_t timer_start = 0, cur_time = 0;
|
|
int64_t time_span = 0;
|
|
|
|
uint32_t cmd_offset_ntb = 100LL * 1000 * 25000; // 100s
|
|
|
|
/* init irq */
|
|
rf_mac_interrupt_init();
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_10_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_18_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_24_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_20_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_28_ADDR, 0xffffffff);
|
|
|
|
/* init sched */
|
|
rf_mac_tdma_sched_init(2, cmd_offset_ntb);
|
|
|
|
/* init mpdu */
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ0_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXQ_ENABLE_LOAD_REG_ADDR);
|
|
REG_FIELD_SET(RF_MAC_TXQ_LOAD, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_TXQ_ENABLE, tmp, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ_ENABLE_LOAD_REG_ADDR, tmp);
|
|
|
|
/* start sched */
|
|
rf_mac_cmdlist_cfg();
|
|
|
|
for (;;) {
|
|
timer_start = rf_mac_get_ntb();
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
|
|
sel_bit_map = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
|
|
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
|
|
remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
|
|
ptr = RF_MAC_READ_REG(CFG_RF_MAC_CUR_TX_PTR_ADDR);
|
|
cur_ntb = rf_mac_get_ntb();
|
|
iot_printf("sel_bitmap:0x%x, curbitmap:0x%x, remain time:%lu, "
|
|
"alertcnt:%d, ptr:0x%x, curntb:%lu, irq_sts1:0x%x, irq_sts2:0x%x\n",
|
|
sel_bit_map, txq_bit_map,
|
|
remain_time, alert_cnt, ptr, cur_ntb,
|
|
RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_6_ADDR),
|
|
RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_7_ADDR));
|
|
|
|
do {
|
|
cur_time = rf_mac_get_ntb();
|
|
time_span = cur_time - timer_start;
|
|
if (time_span < 0) { // wrap around
|
|
time_span = (0x100000000LL) - timer_start + cur_time;
|
|
}
|
|
} while (!tx_comp_irq_happen
|
|
|| ((uint64_t)time_span < 250000));
|
|
|
|
tx_comp_irq_happen = 0;
|
|
|
|
iot_printf("rf mac tx done, happen:%d\n", tx_comp_irq_cnt);
|
|
}
|
|
}
|
|
|
|
void rf_mac_csma_sched_init(uint32_t cmd_num, uint32_t cmd_offset_ntb)
|
|
{
|
|
uint32_t i;
|
|
g_cmd_num = cmd_num;
|
|
pb_period_1 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
if (i == 0) {
|
|
cmd_list_1[i].rf_tx_q_en_bm = 0;
|
|
} else {
|
|
cmd_list_1[i].rf_tx_q_en_bm = 0x3e;
|
|
}
|
|
pb_period_1 += cmd_offset_ntb;
|
|
cmd_list_1[i].rf_end_t = pb_period_1;
|
|
iot_printf("cmdlist1 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_1[i].rf_tx_q_en_bm, cmd_list_1[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_1, CMDLIST_CMD_NUM*2);
|
|
pb_period_2 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
if (i == 0) {
|
|
cmd_list_2[i].rf_tx_q_en_bm = 0;
|
|
} else {
|
|
cmd_list_2[i].rf_tx_q_en_bm = 0x3e;
|
|
}
|
|
pb_period_2 += cmd_offset_ntb;
|
|
cmd_list_2[i].rf_end_t = pb_period_2;
|
|
iot_printf("cmdlist2 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_2[i].rf_tx_q_en_bm, cmd_list_2[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_2, CMDLIST_CMD_NUM*2);
|
|
}
|
|
|
|
void rf_mac_csma_flow_test(rf_mac_cfg_info_t *rf_mac_cfg)
|
|
{
|
|
uint32_t tmp, sel_bit_map, txq_bit_map, remain_time, ptr, cur_ntb;
|
|
uint32_t timer_start = 0, cur_time = 0;
|
|
int64_t time_span = 0;
|
|
|
|
uint32_t cmd_offset_ntb = 1000 * 25000; //2LL * 1000 * 25000; // 100s
|
|
|
|
/* init irq */
|
|
rf_mac_interrupt_init();
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_10_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_18_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_24_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_20_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_28_ADDR, 0xffffffff);
|
|
|
|
/* init sched */
|
|
rf_mac_csma_sched_init(2, cmd_offset_ntb);
|
|
|
|
#define RF_OFDM_US 154
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_SLOT_TIME_12_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_SLOT_TIMER_1, tmp, (RF_OFDM_US * 10));
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_SLOT_TIME_12_ADDR, tmp);
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_SLOT_TIME_12_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_SLOT_TIMER_2, tmp, (RF_OFDM_US * 8));
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_SLOT_TIME_12_ADDR, tmp);
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_SLOT_TIME_34_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_SLOT_TIMER_3, tmp, (RF_OFDM_US * 6));
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_SLOT_TIME_34_ADDR, tmp);
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_SLOT_TIME_34_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_SLOT_TIMER_4, tmp, (RF_OFDM_US * 4));
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_SLOT_TIME_34_ADDR, tmp);
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_SLOT_TIME_56_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_SLOT_TIMER_5, tmp, (RF_OFDM_US * 10));
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_SLOT_TIME_56_ADDR, tmp);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_BACKOFF_2_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_BACKOFF_PE_1, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_SG_BACKOFF_PE_2, tmp, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_BACKOFF_2_ADDR, tmp);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SG_BACKOFF_3_ADDR);
|
|
REG_FIELD_SET(RF_MAC_SG_BACKOFF_PE_3, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_SG_BACKOFF_PE_4, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_SG_BACKOFF_PE_5, tmp, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SG_BACKOFF_3_ADDR, tmp);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_SEED_CTL_1_ADDR);
|
|
REG_FIELD_SET(RF_MAC_LOAD_SEED_1, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_LOAD_SEED_2, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_LOAD_SEED_3, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_LOAD_SEED_4, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_LOAD_SEED_5, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_LOAD_SEED_6, tmp, 1);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_SEED_CTL_1_ADDR, tmp);
|
|
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ0_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start);
|
|
|
|
/* init mpdu */
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start1, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ1_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start1);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start2, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ2_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start2);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start3, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ3_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start3);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start4, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ4_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start4);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start5, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ5_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start5);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXQ_ENABLE_LOAD_REG_ADDR);
|
|
REG_FIELD_SET(RF_MAC_TXQ_LOAD, tmp, 0x3E);
|
|
REG_FIELD_SET(RF_MAC_TXQ_ENABLE, tmp, 0x3E);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ_ENABLE_LOAD_REG_ADDR, tmp);
|
|
|
|
/* start sched */
|
|
rf_mac_cmdlist_cfg();
|
|
|
|
for (;;) {
|
|
timer_start = rf_mac_get_ntb();
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
|
|
sel_bit_map = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
|
|
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
|
|
remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
|
|
ptr = RF_MAC_READ_REG(CFG_RF_MAC_CUR_TX_PTR_ADDR);
|
|
cur_ntb = rf_mac_get_ntb();
|
|
iot_printf("sel_bitmap:0x%x, curbitmap:0x%x, remain time:%lu, "
|
|
"alertcnt:%d, ptr:0x%x, curntb:%lu, alertts:%lu\n",
|
|
sel_bit_map, txq_bit_map,
|
|
remain_time, alert_cnt, ptr, cur_ntb,
|
|
RF_MAC_READ_REG(CFG_RF_MAC_BCN_ALERT_AHEAD_ADDR));
|
|
|
|
do {
|
|
cur_time = rf_mac_get_ntb();
|
|
time_span = cur_time - timer_start;
|
|
if (time_span < 0) { // wrap around
|
|
time_span = (0x100000000LL) - timer_start + cur_time;
|
|
}
|
|
} while (!tx_comp_irq_happen
|
|
|| ((uint64_t)time_span < 250000));
|
|
|
|
tx_comp_irq_happen = 0;
|
|
|
|
iot_printf("rf mac tx done, happen:%d\n", tx_comp_irq_cnt);
|
|
}
|
|
}
|
|
|
|
void rf_mac_rx_only_sched_init(uint32_t cmd_num, uint32_t cmd_offset_ntb)
|
|
{
|
|
uint32_t i;
|
|
g_cmd_num = cmd_num;
|
|
pb_period_1 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
cmd_list_1[i].rf_tx_q_en_bm = 0;
|
|
pb_period_1 += cmd_offset_ntb;
|
|
cmd_list_1[i].rf_end_t = pb_period_1;
|
|
iot_printf("cmdlist1 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_1[i].rf_tx_q_en_bm, cmd_list_1[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_1, 16);
|
|
pb_period_2 = 0;
|
|
/* init cmdlist */
|
|
for (i = 0; i < g_cmd_num; i++) {
|
|
cmd_list_2[i].rf_tx_q_en_bm = 0;
|
|
pb_period_2 += cmd_offset_ntb;
|
|
cmd_list_2[i].rf_end_t = pb_period_2;
|
|
iot_printf("cmdlist2 i:%d, bitmap:0x%x, offset:%lu\n",
|
|
i, cmd_list_2[i].rf_tx_q_en_bm, cmd_list_2[i].rf_end_t);
|
|
}
|
|
//rf_mac_mem_dump((uint32_t *)cmd_list_2, 16);
|
|
}
|
|
|
|
void rf_mac_rx_flow_test(rf_mac_cfg_info_t *rf_mac_cfg)
|
|
{
|
|
uint32_t tmp, sel_bit_map, txq_bit_map, remain_time, ptr, cur_ntb;
|
|
uint32_t timer_start = 0, cur_time = 0;
|
|
int64_t time_span = 0;
|
|
|
|
uint32_t cmd_offset_ntb = 100LL * 1000 * 25000; // 100s
|
|
|
|
/* init irq */
|
|
rf_mac_interrupt_init();
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_10_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_18_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_24_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_20_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_28_ADDR, 0xffffffff);
|
|
|
|
/* init sched */
|
|
rf_mac_rx_only_sched_init(2, cmd_offset_ntb);
|
|
|
|
/* init mpdu */
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start, rf_mac_cfg);
|
|
|
|
/* start sched */
|
|
rf_mac_cmdlist_cfg();
|
|
|
|
for (;;) {
|
|
timer_start = rf_mac_get_ntb();
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
|
|
sel_bit_map = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
|
|
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
|
|
remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
|
|
ptr = RF_MAC_READ_REG(CFG_RF_MAC_CUR_TX_PTR_ADDR);
|
|
cur_ntb = rf_mac_get_ntb();
|
|
iot_printf("sel_bitmap:0x%x, curbitmap:0x%x, remain time:%lu, "
|
|
"alertcnt:%d, ptr:0x%x, curntb:%lu, irq_sts1:0x%x, irq_sts2:0x%x\n",
|
|
sel_bit_map, txq_bit_map,
|
|
remain_time, alert_cnt, ptr, cur_ntb,
|
|
RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_6_ADDR),
|
|
RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_7_ADDR));
|
|
|
|
do {
|
|
cur_time = rf_mac_get_ntb();
|
|
time_span = cur_time - timer_start;
|
|
if (time_span < 0) { // wrap around
|
|
time_span = (0x100000000LL) - timer_start + cur_time;
|
|
}
|
|
} while (!rx_comp_irq_happen
|
|
|| ((uint64_t)time_span < 250000));
|
|
|
|
rx_comp_irq_happen = 0;
|
|
|
|
iot_printf("rx happen:%d\n", rx_comp_irq_cnt);
|
|
}
|
|
}
|
|
|
|
void rf_mac_debug_hwq_flow_test(rf_mac_cfg_info_t *rf_mac_cfg)
|
|
{
|
|
uint32_t tmp, sel_bit_map, txq_bit_map, remain_time, ptr, cur_ntb;
|
|
uint32_t timer_start = 0, cur_time = 0;
|
|
int64_t time_span = 0;
|
|
uint8_t hwq = 1;
|
|
/* init irq */
|
|
rf_mac_interrupt_init();
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_4_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_0_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_8_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_14_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_10_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_18_ADDR, 0xffffffff);
|
|
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_24_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_20_ADDR, 0xffffffff);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_28_ADDR, 0xffffffff);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_CFG_ADDR);
|
|
REG_FIELD_SET(RF_MAC_DEBUG_EN, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_DEBUG_START, tmp, 1);
|
|
REG_FIELD_SET(RF_MAC_DEBUG_TXQ_BITMAP, tmp, 1 << hwq);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_DEBUG_CFG_ADDR, tmp);
|
|
|
|
/* init mpdu */
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ0_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start);
|
|
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start1, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ1_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start1);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start2, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ2_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start2);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start3, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ3_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start3);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start4, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ4_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start4);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start5, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ5_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start5);
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start6, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ6_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start6);
|
|
|
|
rf_mac_tx_mpdu_start(glb_rf_tx.rf_mpdu_start7, rf_mac_cfg);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ7_PTR_ADDR, (uint32_t)glb_rf_tx.rf_mpdu_start7);
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXQ_ENABLE_LOAD_REG_ADDR);
|
|
REG_FIELD_SET(RF_MAC_TXQ_LOAD, tmp, 1 << hwq);
|
|
REG_FIELD_SET(RF_MAC_TXQ_ENABLE, tmp, 1 << hwq);
|
|
RF_MAC_WRITE_REG(CFG_RF_MAC_TXQ_ENABLE_LOAD_REG_ADDR, tmp);
|
|
|
|
for (;;) {
|
|
timer_start = rf_mac_get_ntb();
|
|
|
|
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
|
|
sel_bit_map = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
|
|
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
|
|
remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
|
|
ptr = RF_MAC_READ_REG(CFG_RF_MAC_CUR_TX_PTR_ADDR);
|
|
cur_ntb = rf_mac_get_ntb();
|
|
iot_printf("sel_bitmap:0x%x, curbitmap:0x%x, remain time:%lu, "
|
|
"alertcnt:%d, ptr:0x%x, curntb:%lu, irq_sts1:0x%x, irq_sts2:0x%x\n",
|
|
sel_bit_map, txq_bit_map,
|
|
remain_time, alert_cnt, ptr, cur_ntb,
|
|
RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_6_ADDR),
|
|
RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_7_ADDR));
|
|
|
|
do {
|
|
cur_time = rf_mac_get_ntb();
|
|
time_span = cur_time - timer_start;
|
|
if (time_span < 0) { // wrap around
|
|
time_span = (0x100000000LL) - timer_start + cur_time;
|
|
}
|
|
} while (!tx_comp_irq_happen
|
|
|| ((uint64_t)time_span < 250000));
|
|
|
|
tx_comp_irq_happen = 0;
|
|
|
|
iot_printf("rf mac tx done, happen:%d\n", tx_comp_irq_cnt);
|
|
}
|
|
}
|
|
|