732 lines
25 KiB
C
732 lines
25 KiB
C
/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "os_task.h"
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#include "os_utils.h"
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/* common includes */
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#include "iot_io.h"
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#include "iot_bitops.h"
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#include "iot_pkt.h"
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#include "iot_ipc.h"
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#include "iot_plc_lib.h"
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#include "iot_dbglog_api.h"
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#include "iot_config.h"
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/* driver includes */
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#include "iot_clock.h"
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#include "iot_uart.h"
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/* cli includes */
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#include "iot_cli.h"
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#include "iot_uart_h.h"
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/* debug includes*/
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#include "dbg_io.h"
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#include "hw_reg_api.h"
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#include "uart.h"
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#include "apb_dma.h"
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#include "dma_hw.h"
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#include "hw_sadc.h"
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#include "sadc0_reg.h"
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#include "sadc1_reg.h"
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#include "sadc.h"
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#include "ahb_rf.h"
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#include "granite_reg.h"
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#include "ana.h"
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#include "apb_glb_reg.h"
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#include "phy_dfe_reg.h"
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#include "adc.h"
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#include "pmu_hw.h"
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desc_t *pdesc_rx=NULL;
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desc_t *pdesc_tx=NULL;
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desc_t *pdesc_rx_end=NULL;
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desc_t *pdesc_tx_end=NULL;
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void dma_desc_tail_exchange(desc_t*desc0, desc_t*desc1)
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{
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volatile unsigned int tail;
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tail = desc0->tail_lable[0];
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desc0->tail_lable[0] = desc1->tail_lable[0];
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desc1->tail_lable[0] = tail;
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}
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int int_stack[0x20];
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void sadc_dma_handler(int device, int status)
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{
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desc_t *st, *end, *pnt;
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iot_pkt_t **pkt;
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static int int_stack_index=0;
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int_stack[(int_stack_index++)&0x1F] = status;
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if(DMA_INT_IN_SUC_EOF&status)
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{
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end = st = pdesc_rx_end;
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while((end->n_ptr != st) && (end->n_ptr->owner != DESC_OWNER_DMA)) end = end->n_ptr;
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pdesc_rx_end = end->n_ptr;
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pnt = pdesc_tx;
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while(st != end->n_ptr)
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{
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/* prepare pkt before exchange */
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pkt = (iot_pkt_t**)EXTEN_POINTER(st);
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iot_pkt_set_tail(*pkt, (*pkt)->data + st->length);
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pkt = (iot_pkt_t**)EXTEN_POINTER(pnt);
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iot_pkt_set_data(*pkt, (*pkt)->head);
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iot_pkt_set_tail(*pkt, (*pkt)->head);
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dma_desc_tail_exchange(pnt, st);
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pkt = (iot_pkt_t**)EXTEN_POINTER(st);
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DMA_MAKE_DESC(st, (*pkt)->data, TEST_BUF_SIZE, 0, 0, 0, 0, DESC_OWNER_DMA);
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/* send pkt recieved */
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pkt = (iot_pkt_t**)EXTEN_POINTER(pnt);
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DMA_MAKE_DESC(pnt, (*pkt)->data, TEST_BUF_SIZE, iot_pkt_block_len(*pkt, IOT_PKT_BLOCK_DATA),\
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0, 0, 0, DESC_OWNER_DMA);
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st = st->n_ptr;
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pnt = pnt->n_ptr;
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}
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end = pnt->l_ptr;
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end->n_ptr = NULL;
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pdesc_tx_end->n_ptr = pdesc_tx;
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if(DESC_OWNER_CPU == pdesc_tx_end->owner)
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{
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dma_hw_start_send(DMA_TEST_DEVICE, pdesc_tx);
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}
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pdesc_tx = pnt;
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pdesc_tx_end = end;
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}
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return ;
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}
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#if DT_SADC_POLLING_EN
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/* 7 phase data */
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uint32_t chn_data[DT_SADC_SAMPLE_PHASE_NUM][DT_SADC_SAMPLE_QUANTITY] = {0};
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#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
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uint32_t chn_data1[DT_SADC_SAMPLE_PHASE_NUM - 1][DT_SADC_SAMPLE_QUANTITY] = {0};
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#endif
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void sadc_data_polling()
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{
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uint32_t count0 = 0, count1 = 0, count2 = 0, \
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count30 = 0, count31 = 0, count32 = 0, count33 = 0;
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while(1)
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{
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if (count0<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, SADC_PHASE0)) {
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chn_data[0][count0] = sadc_data_get(ANA_SADC0, SADC_PHASE0);
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sadc_data_vld_clr(ANA_SADC0, SADC_PHASE0);
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count0++;
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}
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}
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if (count1<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, SADC_PHASE1)) {
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chn_data[1][count1] = sadc_data_get(ANA_SADC0, SADC_PHASE1);
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sadc_data_vld_clr(ANA_SADC0, SADC_PHASE1);
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count1++;
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}
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}
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if (count2<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, SADC_PHASE2)) {
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chn_data[2][count2] = sadc_data_get(ANA_SADC0, SADC_PHASE2);
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sadc_data_vld_clr(ANA_SADC0, SADC_PHASE2);
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count2++;
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}
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}
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if (count30<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, ID_PHASE3P0)) {
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chn_data[3][count30] = sadc_data_get(ANA_SADC0, ID_PHASE3P0);
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sadc_data_vld_clr(ANA_SADC0, ID_PHASE3P0);
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count30++;
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}
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}
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if (count31<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, SADC_PHASE3_1)) {
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chn_data[4][count31] = sadc_data_get(ANA_SADC0, SADC_PHASE3_1);
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sadc_data_vld_clr(ANA_SADC0, SADC_PHASE3_1);
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count31++;
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}
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}
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if (count32<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, SADC_PHASE3_2)) {
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chn_data[5][count32] = sadc_data_get(ANA_SADC0, SADC_PHASE3_2);
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sadc_data_vld_clr(ANA_SADC0, SADC_PHASE3_2);
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count32++;
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}
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}
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if (count33<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC0, ID_PHASE3P3)) {
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chn_data[6][count33] = sadc_data_get(ANA_SADC0, ID_PHASE3P3);
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sadc_data_vld_clr(ANA_SADC0, ID_PHASE3P3);
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count33++;
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}
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}
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if ((count0 == DT_SADC_SAMPLE_QUANTITY) && (count1 == DT_SADC_SAMPLE_QUANTITY) && \
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(count2 == DT_SADC_SAMPLE_QUANTITY) && (count30 == DT_SADC_SAMPLE_QUANTITY) && \
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(count31 == DT_SADC_SAMPLE_QUANTITY) && (count32 == DT_SADC_SAMPLE_QUANTITY) && \
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(count33 == DT_SADC_SAMPLE_QUANTITY)) {
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iot_printf("count:%d dump complete!\n", DT_SADC_SAMPLE_QUANTITY);
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break;
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}
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}
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}
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#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
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void sadc1_data_polling()
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{
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uint32_t count0 = 0, count1 = 0, count2 = 0, \
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count30 = 0, count31 = 0, count32 = 0;
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while(1)
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{
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if (count0<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC1, SADC_PHASE0)) {
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chn_data1[0][count0] = sadc_data_get(ANA_SADC1, SADC_PHASE0);
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sadc_data_vld_clr(ANA_SADC1, SADC_PHASE0);
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count0++;
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}
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}
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if (count1<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC1, SADC_PHASE1)) {
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chn_data1[1][count1] = sadc_data_get(ANA_SADC1, SADC_PHASE1);
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sadc_data_vld_clr(ANA_SADC1, SADC_PHASE1);
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count1++;
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}
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}
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if (count2<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC1, SADC_PHASE2)) {
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chn_data1[2][count2] = sadc_data_get(ANA_SADC1, SADC_PHASE2);
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sadc_data_vld_clr(ANA_SADC1, SADC_PHASE2);
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count2++;
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}
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}
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if (count30<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC1, ID_PHASE3P0)) {
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chn_data1[3][count30] = sadc_data_get(ANA_SADC1, ID_PHASE3P0);
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sadc_data_vld_clr(ANA_SADC1, ID_PHASE3P0);
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count30++;
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}
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}
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if (count31<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC1, SADC_PHASE3_1)) {
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chn_data1[4][count31] = sadc_data_get(ANA_SADC1, SADC_PHASE3_1);
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sadc_data_vld_clr(ANA_SADC1, SADC_PHASE3_1);
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count31++;
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}
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}
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if (count32<DT_SADC_SAMPLE_QUANTITY) {
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if (sadc_check_data_vld(ANA_SADC1, SADC_PHASE3_2)) {
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chn_data1[5][count32] = sadc_data_get(ANA_SADC1, SADC_PHASE3_2);
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sadc_data_vld_clr(ANA_SADC1, SADC_PHASE3_2);
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count32++;
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}
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}
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if ((count0 == DT_SADC_SAMPLE_QUANTITY) && (count1 == DT_SADC_SAMPLE_QUANTITY) && \
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(count2 == DT_SADC_SAMPLE_QUANTITY) && (count30 == DT_SADC_SAMPLE_QUANTITY) && \
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(count31 == DT_SADC_SAMPLE_QUANTITY) && (count32 == DT_SADC_SAMPLE_QUANTITY)) {
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iot_printf("count1:%d dump complete!\n", DT_SADC_SAMPLE_QUANTITY);
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break;
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}
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}
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}
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#endif
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void sadc_reg_dump_dbg()
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{
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iot_printf("dump sadc register:\n");
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iot_printf("CFG_SADC0_CHN_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_CHN_CFG_ADDR));
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iot_printf("CFG_SADC0_CHN_MUX_SEL_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_CHN_MUX_SEL_CFG_ADDR));
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iot_printf("CFG_SADC0_CHN_SAMPLE_TIME_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_CHN_SAMPLE_TIME_ADDR));
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iot_printf("CFG_SADC0_CHN_FILTER_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_CHN_FILTER_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE0_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE0_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE1_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE1_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE2_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE2_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE3_0_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE3_0_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE3_1_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE3_1_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE3_2_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE3_2_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_PHASE3_3_THRS_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE3_3_THRS_CFG_ADDR));
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iot_printf("CFG_SADC0_MTR_SEL_MUX_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_MTR_SEL_MUX_CFG_ADDR));
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iot_printf("CFG_SADC0_VCM_CH1_SEL_MUX_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_VCM_CH1_SEL_MUX_ADDR));
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iot_printf("CFG_SADC0_RST_CH1_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_RST_CH1_ADDR));
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iot_printf("CFG_SADC0_IFRED_CH1_EN_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_IFRED_CH1_EN_ADDR));
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iot_printf("CFG_SADC0_MTR2PAD_EN_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_MTR2PAD_EN_ADDR));
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iot_printf("CFG_SADC0_MTR2PAD_EN_NEG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_MTR2PAD_EN_NEG_ADDR));
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iot_printf("CFG_SADC0_MTR3PAD_EN_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_MTR3PAD_EN_ADDR));
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iot_printf("CFG_SADC0_ATB2PAD_EN_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_ATB2PAD_EN_ADDR));
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iot_printf("CFG_SADC0_SCLR_CTRL_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_SCLR_CTRL_ADDR));
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iot_printf("CFG_SADC0_SUB_DC_THRS_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_SUB_DC_THRS_ADDR));
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iot_printf("CFG_SADC0_DBG_BUS0_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_DBG_BUS0_ADDR));
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iot_printf("CFG_SADC0_SUB_DC_THRS_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_SUB_DC_THRS_ADDR));
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iot_printf("CFG_SADC0_TSW_SENS_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_TSW_SENS_ADDR));
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iot_printf("CFG_SADC0_TSW_PD_PGA_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_TSW_PD_PGA_ADDR));
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iot_printf("CFG_SADC0_TSW_METER_PGA_GAIN_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_TSW_METER_PGA_GAIN_ADDR));
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iot_printf("CFG_SADC0_INT_RAW_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_INT_RAW_ADDR));
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iot_printf("CFG_SADC0_INT_ST_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_INT_ST_ADDR));
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iot_printf("CFG_SADC0_INT_ENA_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_INT_ENA_ADDR));
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iot_printf("CFG_SADC0_PHASE_EXTHRS_SEL_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE_EXTHRS_SEL_ADDR));
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iot_printf("CFG_SADC0_PHASE_DMA_OUT_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_PHASE_DMA_OUT_CFG_ADDR));
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iot_printf("CFG_SADC0_CHN_CFG1_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_CHN_CFG1_ADDR));
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iot_printf("CFG_SADC0_DBG_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC0_DBG_CFG_ADDR));
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iot_printf("CFG_SADC_COMMON_CFG_ADDR: 0x%x\n", SADC0_READ_REG(CFG_SADC_COMMON_CFG_ADDR));
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}
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void sadc_dual_mode_test()
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{
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/* 0:32k 1:8m 2:25m */
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pmu_clk_set(2);
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//step1:sadc working basic configuration
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC0, true);
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC1, true);
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC2, true);
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC3, true);
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC4, true);
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC5, true);
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sadc_phase_raw_regdata_en(ANA_SADC0, CHNL_NUM_ADC6, true);
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/* clr auto */
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC0, false);
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC1, false);
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC2, false);
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC3, false);
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC4, false);
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC5, false);
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sadc_phase_clr_auto_en(ANA_SADC0, CHNL_NUM_ADC6, false);
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#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC0, true);
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC1, true);
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC2, true);
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC3, true);
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC4, true);
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC5, true);
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sadc_phase_raw_regdata_en(ANA_SADC1, CHNL_NUM_ADC6, true);
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/* clr auto */
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sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC0, false);
|
|
sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC1, false);
|
|
sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC2, false);
|
|
sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC3, false);
|
|
sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC4, false);
|
|
sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC5, false);
|
|
sadc_phase_clr_auto_en(ANA_SADC1, CHNL_NUM_ADC6, false);
|
|
#endif
|
|
|
|
/* 7phase mode */
|
|
sadc_phase_mode_set(ANA_SADC0, 1);
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
sadc_phase_mode_set(ANA_SADC1, 1);
|
|
#endif
|
|
|
|
//step2: config analog info according to requirement
|
|
/* enable ch2 and ch3 pad */
|
|
sadc_chn2_pad_en(SADC_PHASE2, true);//single
|
|
sadc_mtr2pad_en_neg(SADC_PHASE2, false);//diff
|
|
sadc_mtr3pad_en(SADC_PHASE3_0, true);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE0, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_SING_CH0);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE1, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE1, SADC_TSW_SEL_SCL_MUX_SING_CH1);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE2, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE2, SADC_TSW_SEL_SCL_MUX_SING_CH2);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE3_0, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE3_0, SADC_TSW_SEL_SCL_MUX_SING_CH3);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE3_1, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE3_1, SADC_TSW_SEL_SCL_MUX_SING_CH4);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE3_2, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE3_2, SADC_TSW_SEL_SCL_MUX_SING_CH5);
|
|
|
|
sadc_mtr_sel_scl_mux(SADC_PHASE3_3, 0x0);
|
|
sadc_phase_sel_scl_mux(SADC_PHASE3_3, SADC_TSW_SEL_SCL_MUX_SING_CH6);
|
|
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
sadc1_phase_sel_scl_mux(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_SING_CH0);
|
|
sadc1_phase_sel_scl_mux(SADC_PHASE1, SADC_TSW_SEL_SCL_MUX_SING_CH1);
|
|
sadc1_phase_sel_scl_mux(SADC_PHASE2, SADC_TSW_SEL_SCL_MUX_SING_CH2);
|
|
sadc1_phase_sel_scl_mux(SADC_PHASE3_0, SADC_TSW_SEL_SCL_MUX_SING_CH3);
|
|
sadc1_phase_sel_scl_mux(SADC_PHASE3_1, SADC_TSW_SEL_SCL_MUX_SING_CH4);
|
|
sadc1_phase_sel_scl_mux(SADC_PHASE3_2, SADC_TSW_SEL_SCL_MUX_SING_CH5);
|
|
#endif
|
|
|
|
//step3:
|
|
sadc_start_en(ANA_SADC0, true);
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
sadc_start_en(ANA_SADC1, true);
|
|
#endif
|
|
|
|
//step4: polling 7 phase data
|
|
sadc_data_polling();
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
sadc1_data_polling();
|
|
#endif
|
|
iot_printf("start dump data phase data:\n");
|
|
|
|
for(uint32_t i = 0; i < DT_SADC_SAMPLE_QUANTITY; i++)
|
|
{
|
|
for(uint32_t phase_idx = 0; phase_idx < 7; phase_idx++)
|
|
{
|
|
chn_data[phase_idx][i] = (chn_data[phase_idx][i]) & 0xfffff;
|
|
if ((chn_data[phase_idx][i]) & 0x80000) {
|
|
chn_data[phase_idx][i] = (chn_data[phase_idx][i]) - 0x100000;
|
|
}
|
|
}
|
|
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
for(uint32_t phase_idx1 = 0; phase_idx1 < 6; phase_idx1++)
|
|
{
|
|
chn_data1[phase_idx1][i] = (chn_data1[phase_idx1][i]) & 0xfffff;
|
|
if ((chn_data1[phase_idx1][i]) & 0x80000) {
|
|
chn_data1[phase_idx1][i] = (chn_data1[phase_idx1][i]) - 0x100000;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
iot_printf("%d,%d,%d,%d,%d,%d,%d %d,%d,%d,%d,%d,%d\n", \
|
|
chn_data[0][i], chn_data[1][i], chn_data[2][i], \
|
|
chn_data[3][i], chn_data[4][i], chn_data[5][i], chn_data[6][i], \
|
|
chn_data1[0][i], chn_data1[1][i], chn_data1[2][i], \
|
|
chn_data1[3][i], chn_data1[4][i], chn_data1[5][i]);
|
|
#else
|
|
iot_printf("%d,%d,%d,%d,%d,%d,%d\n", \
|
|
chn_data[0][i], chn_data[1][i], chn_data[2][i], \
|
|
chn_data[3][i], chn_data[4][i], chn_data[5][i], chn_data[6][i]);
|
|
#endif
|
|
}
|
|
|
|
#if DT_SADC_DBG_EN
|
|
sadc_reg_dump_dbg();
|
|
#endif
|
|
|
|
while(1);
|
|
}
|
|
|
|
void sadc_multi_phase_test()
|
|
{
|
|
/* adc init */
|
|
sadc_init(ANA_SADC0, NULL);
|
|
|
|
/* mtr sel scl from Meter or vtemp/vcm */
|
|
#if DT_SADC_MTR_SEL_SCL_EN == 1
|
|
sadc_mtr_sel_scl_mux(0, 0x7);
|
|
#else
|
|
sadc_mtr_sel_scl_mux(0, 0x0);
|
|
#endif
|
|
|
|
/* init discard number for crosstalk */
|
|
sadc_discard_num_set(ANA_SADC0, 0, 6);
|
|
|
|
/* dual sadc mode */
|
|
sadc_dual_mode_test();
|
|
}
|
|
|
|
void sadc_single_phase_test()
|
|
{
|
|
uint32_t sample_data = 0;
|
|
int32_t sample_tmp =0, sum_data = 0;
|
|
uint8_t err_num = 0;
|
|
uint32_t sum_cnt = 0;
|
|
float current_factor = \
|
|
(DT_SADC_REF_VOL_V * DT_SADC_CT_RATIO * DT_SADC_DIV_SQRT_2)/\
|
|
(DT_SADC_REF_SUM_DATA * DT_SADC_CURR_OHM_VAL);
|
|
#if !DT_VOL_TRANSFORMER_SUPPORT
|
|
float vol_factor = (DT_SADC_REF_VOL_V * DT_SADC_DIV_SQRT_2 *\
|
|
(DT_SADC_VOL_R_NUM * DT_SADC_COL_R_CAL + DT_SADC_VOL_R_SHARE))/\
|
|
(DT_SADC_REF_SUM_DATA * DT_SADC_VOL_R_SHARE);
|
|
#else
|
|
float vol_factor = (DT_SADC_REF_VOL_V * DT_SADC_DIV_SQRT_2 *\
|
|
(DT_SADC_VOL_R_NUM * DT_SADC_COL_R_CAL))/\
|
|
(DT_SADC_REF_SUM_DATA * DT_SADC_VOL_R_SHARE);
|
|
#endif
|
|
|
|
iot_printf("start sadc dump:\n");
|
|
|
|
/* adc init */
|
|
sadc_init(ANA_SADC0, NULL);
|
|
|
|
/* channel and phase init */
|
|
/* 1 phase mode, only phase 0*/
|
|
sadc_phase_mode_set(ANA_SADC0, 0);
|
|
sadc_phase_sel(ANA_SADC0, 0);
|
|
sadc_phase_sel_scl_mux(0, 0 + SADC_CHANNEL_EXT);
|
|
sadc_adc_gain_set(0, 0);
|
|
|
|
/* mtr sel scl from Meter or vtemp/vcm */
|
|
#if DT_SADC_MTR_SEL_SCL_EN == 1
|
|
sadc_mtr_sel_scl_mux(0, 0x7);
|
|
#else
|
|
sadc_mtr_sel_scl_mux(0, 0x0);
|
|
#endif
|
|
|
|
/* start en */
|
|
sadc_start_en(ANA_SADC0, 1);
|
|
|
|
/* init discard number for crosstalk */
|
|
sadc_discard_num_set(ANA_SADC0, 0, 6);
|
|
|
|
/* sel scl */
|
|
#if DT_SADC_TEST_MODE == DT_SADC_VOL_MODE
|
|
|
|
#if !DT_VOL_TRANSFORMER_SUPPORT
|
|
/* ref vcm to gnd */
|
|
sadc_vcm_sel_mux_set(ANA_SADC0, SADC_PHASE0, ANA_SADC_VCM_SEL_GND);
|
|
/* ADC 500mV */
|
|
sadc_rst_ch_ext_set(ANA_SADC0, SADC_PHASE0, ANA_SADC_ADC_SEL_500MV);
|
|
/* input 0 and inner raise input to 500mV for PGA */
|
|
sadc_tsw_sens_set(ANA_SADC0, SADC_PHASE0, ANA_SADC_TSW_PGA_500MV);
|
|
#endif
|
|
|
|
/* bond phase and channel */
|
|
sadc_phase_sel_scl_mux(0, SADC_TSW_SEL_SCL_MUX_SING_CH0);
|
|
#else
|
|
sadc_phase_sel_scl_mux(0, SADC_TSW_SEL_SCL_MUX_DIFF_CH10);
|
|
#endif
|
|
|
|
while(1)
|
|
{
|
|
sample_data = sadc_poll_data_start(0, 0, 0, &err_num);
|
|
if (1 == err_num) {
|
|
iot_printf("sadc_sum_get time out!\n");
|
|
} else {
|
|
sample_data = sample_data & 0xfffff;
|
|
if (sample_data & 0x80000) {
|
|
sample_tmp = sample_data - 0x100000;
|
|
} else {
|
|
sample_tmp = sample_data;
|
|
}
|
|
}
|
|
|
|
#if 1
|
|
if (sum_cnt < DT_SADC_SUM_NUM) {
|
|
sum_data += sample_tmp;
|
|
sum_cnt++;
|
|
} else {
|
|
#if DT_SADC_TEST_MODE == DT_SADC_VOL_MODE
|
|
iot_printf("%d, %f\n", sum_data, (float)sum_data * vol_factor);
|
|
(void)current_factor;
|
|
#elif DT_SADC_TEST_MODE == DT_SADC_CURRENT_MODE
|
|
iot_printf("%d, %f\n", sum_data, (float)sum_data * current_factor);
|
|
(void)vol_factor;
|
|
#else
|
|
iot_printf("%d\n", sum_data);
|
|
(void)current_factor;
|
|
(void)vol_factor;
|
|
#endif
|
|
(void)current_factor;
|
|
sum_data = sample_tmp;
|
|
sum_cnt= 1;
|
|
}
|
|
//while(dly_cnt--);
|
|
#else
|
|
iot_printf("%d,\n", sample_tmp);
|
|
(void)sum_data;
|
|
(void)sum_cnt;
|
|
(void)current_factor;
|
|
(void)vol_factor;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void sadc_test_task(void)
|
|
{
|
|
/* sadc0 soft reset */
|
|
pmu_soft_reset(SADC_CH1_SOFT_RST_OFFSET);
|
|
#if DT_SADC_TEST_MODE == DT_SADC_DUAL_13PHASE_MODE
|
|
/* sadc1 soft reset */
|
|
pmu_soft_reset(SADC_CH2_SOFT_RST_OFFSET);
|
|
#endif
|
|
|
|
#if DT_SADC_TEST_MODE >= DT_SADC_DUAL_7PHASE_MODE
|
|
sadc_multi_phase_test();
|
|
#else
|
|
/* voltage or current mode */
|
|
sadc_single_phase_test();
|
|
#endif
|
|
}
|
|
#else
|
|
#include "dma_hw_rf.h"
|
|
#include "apb.h"
|
|
|
|
extern void dma_hw_rst();
|
|
extern void dma_hw_fsm_rst();
|
|
|
|
void sadc_desc_data_process(
|
|
uint32_t desc_addr, uint32_t buf_addr, bool_t loop_en)
|
|
{
|
|
volatile uint32_t tmp = 0;
|
|
volatile bool_t done_flag = false;
|
|
volatile int32_t sample_tmp = 0;
|
|
volatile uint32_t i = 0;
|
|
|
|
/* wait desc1 done */
|
|
do {
|
|
tmp = SOC_READ_REG(desc_addr) & 0x40000000;
|
|
done_flag = tmp >> 30;
|
|
} while (done_flag == 0);
|
|
|
|
if (loop_en) {
|
|
/* clr owner */
|
|
SOC_WRITE_REG(desc_addr, \
|
|
(1 << 31) | \
|
|
(0 << 24) | \
|
|
(0xFFC << 12) | \
|
|
(0xFFC << 0));
|
|
}
|
|
|
|
for (i = 0; i < (0xFFC >> 2); i++)
|
|
{
|
|
tmp = SOC_READ_REG(buf_addr + (i << 2)) & 0xfffff;
|
|
if (tmp & 0x80000) {
|
|
sample_tmp = tmp - 0x100000;
|
|
} else {
|
|
sample_tmp = tmp;
|
|
}
|
|
|
|
/* print will block dma */
|
|
if (!loop_en) {
|
|
iot_printf("%d\n", sample_tmp);
|
|
}
|
|
}
|
|
iot_printf("%d\n", 2500);
|
|
}
|
|
|
|
void sadc_test_task(void)
|
|
{
|
|
volatile uint32_t tmp = 0;
|
|
volatile bool_t loop_flag = false;
|
|
int cnt = 0;
|
|
desc_t *rx = NULL;
|
|
const int desc_size = sizeof(desc_t);
|
|
|
|
/* apb enable */
|
|
apb_enable(APB_DMA_HW);
|
|
|
|
/* dma reset */
|
|
dma_hw_rst();
|
|
dma_hw_fsm_rst();
|
|
|
|
/* adc init */
|
|
sadc_init(ANA_SADC0, NULL);
|
|
|
|
/* channel and phase init */
|
|
/* 1 phase mode, only phase 0*/
|
|
sadc_phase_mode_set(ANA_SADC0, 0);
|
|
sadc_phase_sel(ANA_SADC0, 0);
|
|
sadc_phase_sel_scl_mux(0, 0 + SADC_CHANNEL_EXT);
|
|
sadc_adc_gain_set(0, 0);
|
|
|
|
/* mtr sel scl from Meter or vtemp/vcm */
|
|
sadc_mtr_sel_scl_mux(0, 0);
|
|
|
|
/* start en */
|
|
sadc_start_en(ANA_SADC0, 1);
|
|
|
|
/* sel scl */
|
|
sadc_phase_sel_scl_mux(0, SADC_TSW_SEL_SCL_MUX_DIFF_CH10);
|
|
|
|
/* enable AI ram */
|
|
tmp = SOC_READ_REG(0x50000008);
|
|
SOC_WRITE_REG(0x50000008, tmp | 0x80);
|
|
|
|
/* alloc mem for desc */
|
|
pdesc_rx = (desc_t *)os_mem_malloc(0, TEST_DESC_NUM * desc_size);
|
|
/* check alloc result */
|
|
if (NULL == pdesc_rx) {
|
|
return ;
|
|
}
|
|
|
|
rx = pdesc_rx;
|
|
|
|
/* To fill descriptors */
|
|
for(cnt = 0; cnt < TEST_DESC_NUM; cnt++)
|
|
{
|
|
/* for RX */
|
|
DMA_MAKE_DESC(rx, \
|
|
0x73fd0000 + cnt * 0x10000, \
|
|
0xFFC, \
|
|
0xFFC, \
|
|
0, \
|
|
0, \
|
|
0, \
|
|
DESC_OWNER_DMA);
|
|
rx->n_ptr = (desc_t*)((int)rx + desc_size);
|
|
rx->l_ptr = (desc_t*)((int)rx - desc_size);
|
|
|
|
rx = (desc_t*)((int)rx + desc_size);
|
|
}
|
|
rx = (desc_t*)((int)pdesc_rx + desc_size*(TEST_DESC_NUM-1));
|
|
|
|
pdesc_rx->l_ptr = rx;
|
|
rx->n_ptr = pdesc_rx;
|
|
|
|
pdesc_rx_end = pdesc_rx;
|
|
|
|
/* soc rx link */
|
|
DMA_HW_RF_WRITE_REG(CFG_DMA_HW_RX_CHN12_CFG0_ADDR, (uint32_t)pdesc_rx);
|
|
|
|
/* start */
|
|
tmp = DMA_HW_RF_READ_REG(CFG_DMA_HW_RX_CHN12_CFG1_ADDR);
|
|
REG_FIELD_SET(CHN12_RX_START, tmp, 1);
|
|
DMA_HW_RF_WRITE_REG(CFG_DMA_HW_RX_CHN12_CFG1_ADDR, tmp);
|
|
|
|
while(1)
|
|
{
|
|
for(cnt = 0; cnt < TEST_DESC_NUM; cnt++)
|
|
{
|
|
/* data process */
|
|
sadc_desc_data_process( \
|
|
(uint32_t)pdesc_rx, \
|
|
0x73fd0000 + cnt * 0x10000, \
|
|
loop_flag);
|
|
}
|
|
|
|
while(!loop_flag);
|
|
}
|
|
|
|
}
|
|
#endif
|
|
|