208 lines
6.9 KiB
C
208 lines
6.9 KiB
C
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//-----------------------------------
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#define CFG_BB_PKT_RATIO_ADDR 0x0000
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#define SW_AC_STEP_1K_OFFSET 24
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#define SW_AC_STEP_1K_MASK 0x07000000
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#define SW_PKT_DET_RATIO_1K_OFFSET 16
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#define SW_PKT_DET_RATIO_1K_MASK 0x00FF0000
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#define SW_AC_STEP_384_OFFSET 8
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#define SW_AC_STEP_384_MASK 0x00000700
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#define SW_PKT_DET_RATIO_384_OFFSET 0
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#define SW_PKT_DET_RATIO_384_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_PKT_RATIO_MINUS_ADDR 0x0004
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#define SW_PKT_DET_RATIO_1K_MINUS_OFFSET 16
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#define SW_PKT_DET_RATIO_1K_MINUS_MASK 0x00FF0000
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#define SW_PKT_DET_RATIO_384_MINUS_OFFSET 0
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#define SW_PKT_DET_RATIO_384_MINUS_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_THRESHOLD_ADDR 0x0008
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#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_1K_OFFSET 16
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#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_1K_MASK 0x0FFF0000
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#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_384_OFFSET 0
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#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_384_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_BB_PKT_TIME_OUT_ADDR 0x000C
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#define SW_PKT_DET_TIME_OUT_OFFSET 0
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#define SW_PKT_DET_TIME_OUT_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_ADC_TIME_OUT_ADDR 0x0010
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#define SW_ADC_PWR_FALL_TIME_OUT_OFFSET 0
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#define SW_ADC_PWR_FALL_TIME_OUT_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_CORR_TIME_OUT_384_ADDR 0x0014
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#define SW_SELF_CORR_LOWEST_TIME_OUT_384_OFFSET 0
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#define SW_SELF_CORR_LOWEST_TIME_OUT_384_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_CORR_TIME_OUT_1K_ADDR 0x0018
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#define SW_SELF_CORR_LOWEST_TIME_OUT_1K_OFFSET 0
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#define SW_SELF_CORR_LOWEST_TIME_OUT_1K_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_OFFSET_FROM_CORR_ADDR 0x001C
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#define SW_OFFSET_FROM_LOWEST_CORR_OFFSET 16
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#define SW_OFFSET_FROM_LOWEST_CORR_MASK 0x000F0000
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#define SW_PACKET_SYNC_MODE_OFFSET 9
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#define SW_PACKET_SYNC_MODE_MASK 0x00000200
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#define SW_TUNE_SKIP_FOR_FC_OFFSET 0
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#define SW_TUNE_SKIP_FOR_FC_MASK 0x000001FF
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//-----------------------------------
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#define CFG_BB_STOP_FFT_ENGINE_ADDR 0x0020
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#define SW_PKT_DET_1K_STEP_OFFSET 28
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#define SW_PKT_DET_1K_STEP_MASK 0xF0000000
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#define SW_THRESHOLD_STOP_FFT_3K_OFFSET 16
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#define SW_THRESHOLD_STOP_FFT_3K_MASK 0x0FFF0000
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#define SW_PKT_DET_384_STEP_OFFSET 12
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#define SW_PKT_DET_384_STEP_MASK 0x0000F000
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#define SW_THRESHOLD_STOP_FFT_384_OFFSET 0
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#define SW_THRESHOLD_STOP_FFT_384_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_BB_PKT_TIME_OUT_1_ADDR 0x0024
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#define SW_AVE_THETA_TIME_OUT_OFFSET 0
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#define SW_AVE_THETA_TIME_OUT_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_RX_TD_PKT_CNT_ADDR 0x0028
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#define SW_RO_PACKET_NUM_OFFSET 0
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#define SW_RO_PACKET_NUM_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_TD_PKT_CNT_RST_ADDR 0x002C
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#define SW_RESET_PACKET_NUM_OFFSET 0
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#define SW_RESET_PACKET_NUM_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_SELF_CORR_CTRL_ADDR 0x0030
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#define SW_ADJ_CORR_THETA_3K_OFFSET 20
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#define SW_ADJ_CORR_THETA_3K_MASK 0xFFF00000
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#define SW_ADJ_CORR_THETA_384_OFFSET 8
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#define SW_ADJ_CORR_THETA_384_MASK 0x000FFF00
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#define SW_SC_EN_3K_OFFSET 1
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#define SW_SC_EN_3K_MASK 0x00000002
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#define SW_SC_EN_384_OFFSET 0
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#define SW_SC_EN_384_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_WAIT_AGC_ADDR 0x0034
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#define SW_RD_FSM_TIMEOUT_OFFSET 0
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#define SW_RD_FSM_TIMEOUT_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_MINUS_PRE_TIME_OUT_384_ADDR 0x0038
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#define SW_FIND_MINUS_PREAM_TIME_OUT_384_OFFSET 0
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#define SW_FIND_MINUS_PREAM_TIME_OUT_384_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_MINUS_PRE_TIME_OUT_3K_ADDR 0x003C
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#define SW_FIND_MINUS_PREAM_TIME_OUT_3K_OFFSET 0
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#define SW_FIND_MINUS_PREAM_TIME_OUT_3K_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_BB_AGC_WK_TO_ST_TH_ADDR 0x0400
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#define SW_WK_TO_ST_TH_OFFSET 0
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#define SW_WK_TO_ST_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_ST_RCV_LO_TH_ADDR 0x0404
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#define SW_ST_RCV_LO_TH_OFFSET 0
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#define SW_ST_RCV_LO_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_ST_RCV_HI_TH_ADDR 0x0408
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#define SW_ST_RCV_HI_TH_OFFSET 0
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#define SW_ST_RCV_HI_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_ST_RCV_TGT_ADDR 0x040C
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#define SW_ST_RCV_TGT_OFFSET 0
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#define SW_ST_RCV_TGT_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_WK_RCV_LO_TH_ADDR 0x0410
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#define SW_WK_RCV_LO_TH_OFFSET 0
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#define SW_WK_RCV_LO_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_WK_RCV_HI_TH_ADDR 0x0414
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#define SW_WK_RCV_HI_TH_OFFSET 0
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#define SW_WK_RCV_HI_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_WK_RCV_TGT_ADDR 0x0418
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#define SW_WK_RCV_TGT_OFFSET 0
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#define SW_WK_RCV_TGT_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_WK_DET_LO_TH_ADDR 0x041C
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#define SW_WK_DET_LO_TH_OFFSET 0
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#define SW_WK_DET_LO_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_WK_DET_HI_TH_ADDR 0x0420
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#define SW_WK_DET_HI_TH_OFFSET 0
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#define SW_WK_DET_HI_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_WK_DET_TGT_ADDR 0x0424
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#define SW_WK_DET_TGT_OFFSET 0
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#define SW_WK_DET_TGT_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_RAMUP_TH_ADDR 0x0428
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#define SW_RAMPUP_TH_OFFSET 0
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#define SW_RAMPUP_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_DROP_TH_ADDR 0x042C
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#define SW_DROP_TH_OFFSET 0
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#define SW_DROP_TH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_GAIN_DLY_ADDR 0x0430
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#define SW_GAIN_DLY_OFFSET 0
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#define SW_GAIN_DLY_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_AGC_GAIN_LOOP_ADDR 0x0434
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#define SW_GAIN_LOOP_OFFSET 0
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#define SW_GAIN_LOOP_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_GAIN_LEVEL_ADDR 0x0438
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#define SW_FIX_GAIN_EN_OFFSET 31
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#define SW_FIX_GAIN_EN_MASK 0x80000000
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#define SW_MAX_GAIN_OFFSET 16
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#define SW_MAX_GAIN_MASK 0x00FF0000
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#define SW_MIN_GAIN_OFFSET 8
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#define SW_MIN_GAIN_MASK 0x0000FF00
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#define SW_INI_GAIN_OFFSET 0
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#define SW_INI_GAIN_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_AGC_SAT_TH_ADDR 0x043C
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#define SW_SAT_ATTEN_DB_OFFSET 24
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#define SW_SAT_ATTEN_DB_MASK 0xFF000000
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#define SW_PWR_SAT_JUG_CNT_OFFSET 16
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#define SW_PWR_SAT_JUG_CNT_MASK 0x00FF0000
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#define SW_PWR_SAT_DLY_LEN_OFFSET 12
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#define SW_PWR_SAT_DLY_LEN_MASK 0x0000F000
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#define SW_PWR_SAT_TH_OFFSET 0
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#define SW_PWR_SAT_TH_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_AGC_ACC_STEP_ADDR 0x0440
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#define SW_AGC_ACC_STEP_OFFSET 0
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#define SW_AGC_ACC_STEP_MASK 0x00000001
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//HW module read/write macro
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#define PHY_RXTD_READ_REG(addr) SOC_READ_REG(PHY_RXTD_BASEADDR + addr)
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#define PHY_RXTD_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_RXTD_BASEADDR + addr,value)
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