Files
kunlun/inc/hw/reg/cm3/11/phy_tx_reg.h
2024-09-28 14:24:04 +08:00

20 lines
662 B
C

//-----------------------------------
#define CFG_BB_TEST_ONLY_ADDR 0x0000
//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_ADDR 0x0004
#define SW_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_DB_UP_AMP_PARA_INT_MASK 0x000000FC
#define SW_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_DB_UP_AMP_PARA_FRAC_MASK 0x00000003
//-----------------------------------
#define CFG_BB_TX_IFFT_CTRL_ADDR 0x0008
#define SW_IFFT_TD_BIT_SEL_OFFSET 0
#define SW_IFFT_TD_BIT_SEL_MASK 0x00000007
//HW module read/write macro
#define PHY_TX_READ_REG(addr) SOC_READ_REG(PHY_TX_BASEADDR + addr)
#define PHY_TX_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_TX_BASEADDR + addr,value)