364 lines
12 KiB
C
Executable File
364 lines
12 KiB
C
Executable File
|
|
//-----------------------------------
|
|
#define CFG_SFC_RVER_ADDR 0x0000
|
|
#define SFC_RF_VER_OFFSET 0
|
|
#define SFC_RF_VER_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CMD0_ADDR 0x0004
|
|
#define SW_SFC_ENA_OFFSET 31
|
|
#define SW_SFC_ENA_MASK 0x80000000
|
|
#define SW_SFC_DLEN_OFFSET 16
|
|
#define SW_SFC_DLEN_MASK 0x01FF0000
|
|
#define SW_SFC_CMODE_OFFSET 8
|
|
#define SW_SFC_CMODE_MASK 0x0000FF00
|
|
#define SW_SFC_MODE_OFFSET 0
|
|
#define SW_SFC_MODE_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CMD1_ADDR 0x0008
|
|
#define SW_SFC_CMD_OFFSET 24
|
|
#define SW_SFC_CMD_MASK 0xFF000000
|
|
#define SW_SFC_ADDR_OFFSET 0
|
|
#define SW_SFC_ADDR_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CTRL0_ADDR 0x000c
|
|
#define SFC_SW_FORCE_MODE_OFFSET 31
|
|
#define SFC_SW_FORCE_MODE_MASK 0x80000000
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CFG0_ADDR 0x0030
|
|
#define SFC_DUMMY_NUM_OFFSET 12
|
|
#define SFC_DUMMY_NUM_MASK 0x00003000
|
|
#define SFC_PROG_SUS_ENA_OFFSET 8
|
|
#define SFC_PROG_SUS_ENA_MASK 0x00000100
|
|
#define SPI_1P8V_OFFSET 5
|
|
#define SPI_1P8V_MASK 0x00000020
|
|
#define SFC_CRYPT_MODE_OFFSET 4
|
|
#define SFC_CRYPT_MODE_MASK 0x00000010
|
|
#define SFC_CACHE_RD_MODE_OFFSET 0
|
|
#define SFC_CACHE_RD_MODE_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CLK0_ADDR 0x0034
|
|
#define CLK_SPI_SFC_ENA_OFFSET 4
|
|
#define CLK_SPI_SFC_ENA_MASK 0x00000010
|
|
#define CLK_SPI_SFC_DIV_OFFSET 0
|
|
#define CLK_SPI_SFC_DIV_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CFG1_ADDR 0x0040
|
|
#define PE_WAIT_TIME_OFFSET 0
|
|
#define PE_WAIT_TIME_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CFG2_ADDR 0x00044
|
|
#define RESUME_WAIT_TIME_OFFSET 16
|
|
#define RESUME_WAIT_TIME_MASK 0x03FF0000
|
|
#define SUS_WAIT_TIME_OFFSET 0
|
|
#define SUS_WAIT_TIME_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_STS0_ADDR 0x0048
|
|
#define SFC_CTRL_FSM_STATE_OFFSET 4
|
|
#define SFC_CTRL_FSM_STATE_MASK 0x000000F0
|
|
#define SFC_SPI_FSM_STATE_OFFSET 0
|
|
#define SFC_SPI_FSM_STATE_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_RDATA_ADDR 0x004c
|
|
#define SW_SFC_RDATA_OFFSET 0
|
|
#define SW_SFC_RDATA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_WDATA_ADDR 0x0050
|
|
#define SW_SFC_WDATA_OFFSET 0
|
|
#define SW_SFC_WDATA_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_DBG_ADDR 0x0054
|
|
#define SFC_TX_EDGE_SEL_OFFSET 4
|
|
#define SFC_TX_EDGE_SEL_MASK 0x00000010
|
|
#define SFC_ADDR_MAP_MODE_OFFSET 3
|
|
#define SFC_ADDR_MAP_MODE_MASK 0x00000008
|
|
#define SFC_ADDR_MAP_ENA_OFFSET 2
|
|
#define SFC_ADDR_MAP_ENA_MASK 0x00000004
|
|
#define SFC_RX_EDGE_SEL_OFFSET 1
|
|
#define SFC_RX_EDGE_SEL_MASK 0x00000002
|
|
#define SFC_CLK_FORCE_OUT_OFFSET 0
|
|
#define SFC_CLK_FORCE_OUT_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP0_ADDR 0x0060
|
|
#define SFC_ABLK3_MAP_OFFSET 24
|
|
#define SFC_ABLK3_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK2_MAP_OFFSET 16
|
|
#define SFC_ABLK2_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK1_MAP_OFFSET 8
|
|
#define SFC_ABLK1_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK0_MAP_OFFSET 0
|
|
#define SFC_ABLK0_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP1_ADDR 0x0064
|
|
#define SFC_ABLK7_MAP_OFFSET 24
|
|
#define SFC_ABLK7_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK6_MAP_OFFSET 16
|
|
#define SFC_ABLK6_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK5_MAP_OFFSET 8
|
|
#define SFC_ABLK5_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK4_MAP_OFFSET 0
|
|
#define SFC_ABLK4_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP2_ADDR 0x0068
|
|
#define SFC_ABLK11_MAP_OFFSET 24
|
|
#define SFC_ABLK11_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK10_MAP_OFFSET 16
|
|
#define SFC_ABLK10_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK9_MAP_OFFSET 8
|
|
#define SFC_ABLK9_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK8_MAP_OFFSET 0
|
|
#define SFC_ABLK8_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP3_ADDR 0x006c
|
|
#define SFC_ABLK15_MAP_OFFSET 24
|
|
#define SFC_ABLK15_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK14_MAP_OFFSET 16
|
|
#define SFC_ABLK14_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK13_MAP_OFFSET 8
|
|
#define SFC_ABLK13_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK12_MAP_OFFSET 0
|
|
#define SFC_ABLK12_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP4_ADDR 0x0070
|
|
#define SFC_ABLK19_MAP_OFFSET 24
|
|
#define SFC_ABLK19_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK18_MAP_OFFSET 16
|
|
#define SFC_ABLK18_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK17_MAP_OFFSET 8
|
|
#define SFC_ABLK17_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK16_MAP_OFFSET 0
|
|
#define SFC_ABLK16_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP5_ADDR 0x0074
|
|
#define SFC_ABLK23_MAP_OFFSET 24
|
|
#define SFC_ABLK23_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK22_MAP_OFFSET 16
|
|
#define SFC_ABLK22_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK21_MAP_OFFSET 8
|
|
#define SFC_ABLK21_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK20_MAP_OFFSET 0
|
|
#define SFC_ABLK20_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP6_ADDR 0x0078
|
|
#define SFC_ABLK27_MAP_OFFSET 24
|
|
#define SFC_ABLK27_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK26_MAP_OFFSET 16
|
|
#define SFC_ABLK26_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK25_MAP_OFFSET 8
|
|
#define SFC_ABLK25_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK24_MAP_OFFSET 0
|
|
#define SFC_ABLK24_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_AMAP7_ADDR 0x007c
|
|
#define SFC_ABLK31_MAP_OFFSET 24
|
|
#define SFC_ABLK31_MAP_MASK 0x1F000000
|
|
#define SFC_ABLK30_MAP_OFFSET 16
|
|
#define SFC_ABLK30_MAP_MASK 0x001F0000
|
|
#define SFC_ABLK29_MAP_OFFSET 8
|
|
#define SFC_ABLK29_MAP_MASK 0x00001F00
|
|
#define SFC_ABLK28_MAP_OFFSET 0
|
|
#define SFC_ABLK28_MAP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_SWM_CFG0_ADDR 0x0080
|
|
#define CFG_SPI_WR_OFFSET 9
|
|
#define CFG_SPI_WR_MASK 0x00000200
|
|
#define CFG_SPI_RD_OFFSET 8
|
|
#define CFG_SPI_RD_MASK 0x00000100
|
|
#define CFG_CMD_DUAL_MODE_OFFSET 7
|
|
#define CFG_CMD_DUAL_MODE_MASK 0x00000080
|
|
#define CFG_CMD_QUAD_MODE_OFFSET 6
|
|
#define CFG_CMD_QUAD_MODE_MASK 0x00000040
|
|
#define CFG_ADDR_DUAL_MODE_OFFSET 5
|
|
#define CFG_ADDR_DUAL_MODE_MASK 0x00000020
|
|
#define CFG_ADDR_QUAD_MODE_OFFSET 4
|
|
#define CFG_ADDR_QUAD_MODE_MASK 0x00000010
|
|
#define CFG_CMODE_DUAL_MODE_OFFSET 3
|
|
#define CFG_CMODE_DUAL_MODE_MASK 0x00000008
|
|
#define CFG_CMODE_QUAD_MODE_OFFSET 2
|
|
#define CFG_CMODE_QUAD_MODE_MASK 0x00000004
|
|
#define CFG_DATA_DUAL_MODE_OFFSET 1
|
|
#define CFG_DATA_DUAL_MODE_MASK 0x00000002
|
|
#define CFG_DATA_QUAD_MODE_OFFSET 0
|
|
#define CFG_DATA_QUAD_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_SWM_CFG1_ADDR 0x0084
|
|
#define CFG_CMD_LEN_OFFSET 24
|
|
#define CFG_CMD_LEN_MASK 0x1F000000
|
|
#define CFG_ADDR_LEN_OFFSET 16
|
|
#define CFG_ADDR_LEN_MASK 0x001F0000
|
|
#define CFG_CMODE_LEN_OFFSET 8
|
|
#define CFG_CMODE_LEN_MASK 0x00001F00
|
|
#define CFG_DUMMY_LEN_OFFSET 0
|
|
#define CFG_DUMMY_LEN_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_SWM_CFG2_ADDR 0x0088
|
|
#define CFG_CACHE_CMD_OFFSET 24
|
|
#define CFG_CACHE_CMD_MASK 0xFF000000
|
|
#define CFG_WIP_CMD_OFFSET 16
|
|
#define CFG_WIP_CMD_MASK 0x00FF0000
|
|
#define CFG_RESUME_CMD_OFFSET 8
|
|
#define CFG_RESUME_CMD_MASK 0x0000FF00
|
|
#define CFG_SUS_CMD_OFFSET 0
|
|
#define CFG_SUS_CMD_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CACHE_CFG0_ADDR 0x008c
|
|
#define CACHE_SPI_WR_OFFSET 9
|
|
#define CACHE_SPI_WR_MASK 0x00000200
|
|
#define CACHE_SPI_RD_OFFSET 8
|
|
#define CACHE_SPI_RD_MASK 0x00000100
|
|
#define CACHE_CMD_DUAL_MODE_OFFSET 7
|
|
#define CACHE_CMD_DUAL_MODE_MASK 0x00000080
|
|
#define CACHE_CMD_QUAD_MODE_OFFSET 6
|
|
#define CACHE_CMD_QUAD_MODE_MASK 0x00000040
|
|
#define CACHE_ADDR_DUAL_MODE_OFFSET 5
|
|
#define CACHE_ADDR_DUAL_MODE_MASK 0x00000020
|
|
#define CACHE_ADDR_QUAD_MODE_OFFSET 4
|
|
#define CACHE_ADDR_QUAD_MODE_MASK 0x00000010
|
|
#define CACHE_CMODE_DUAL_MODE_OFFSET 3
|
|
#define CACHE_CMODE_DUAL_MODE_MASK 0x00000008
|
|
#define CACHE_CMODE_QUAD_MODE_OFFSET 2
|
|
#define CACHE_CMODE_QUAD_MODE_MASK 0x00000004
|
|
#define CACHE_DATA_DUAL_MODE_OFFSET 1
|
|
#define CACHE_DATA_DUAL_MODE_MASK 0x00000002
|
|
#define CACHE_DATA_QUAD_MODE_OFFSET 0
|
|
#define CACHE_DATA_QUAD_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_CACHE_CFG1_ADDR 0x0090
|
|
#define CACHE_CMD_LEN_OFFSET 24
|
|
#define CACHE_CMD_LEN_MASK 0x1F000000
|
|
#define CACHE_ADDR_LEN_OFFSET 16
|
|
#define CACHE_ADDR_LEN_MASK 0x001F0000
|
|
#define CACHE_CMODE_LEN_OFFSET 8
|
|
#define CACHE_CMODE_LEN_MASK 0x00001F00
|
|
#define CACHE_DUMMY_LEN_OFFSET 0
|
|
#define CACHE_DUMMY_LEN_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_WIP_CFG0_ADDR 0x0094
|
|
#define WIP_SPI_WR_OFFSET 9
|
|
#define WIP_SPI_WR_MASK 0x00000200
|
|
#define WIP_SPI_RD_OFFSET 8
|
|
#define WIP_SPI_RD_MASK 0x00000100
|
|
#define WIP_CMD_DUAL_MODE_OFFSET 7
|
|
#define WIP_CMD_DUAL_MODE_MASK 0x00000080
|
|
#define WIP_CMD_QUAD_MODE_OFFSET 6
|
|
#define WIP_CMD_QUAD_MODE_MASK 0x00000040
|
|
#define WIP_ADDR_DUAL_MODE_OFFSET 5
|
|
#define WIP_ADDR_DUAL_MODE_MASK 0x00000020
|
|
#define WIP_ADDR_QUAD_MODE_OFFSET 4
|
|
#define WIP_ADDR_QUAD_MODE_MASK 0x00000010
|
|
#define WIP_CMODE_DUAL_MODE_OFFSET 3
|
|
#define WIP_CMODE_DUAL_MODE_MASK 0x00000008
|
|
#define WIP_CMODE_QUAD_MODE_OFFSET 2
|
|
#define WIP_CMODE_QUAD_MODE_MASK 0x00000004
|
|
#define WIP_DATA_DUAL_MODE_OFFSET 1
|
|
#define WIP_DATA_DUAL_MODE_MASK 0x00000002
|
|
#define WIP_DATA_QUAD_MODE_OFFSET 0
|
|
#define WIP_DATA_QUAD_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_WIP_CFG1_ADDR 0x0098
|
|
#define WIP_CMD_LEN_OFFSET 24
|
|
#define WIP_CMD_LEN_MASK 0x1F000000
|
|
#define WIP_ADDR_LEN_OFFSET 16
|
|
#define WIP_ADDR_LEN_MASK 0x001F0000
|
|
#define WIP_CMODE_LEN_OFFSET 8
|
|
#define WIP_CMODE_LEN_MASK 0x00001F00
|
|
#define WIP_DUMMY_LEN_OFFSET 0
|
|
#define WIP_DUMMY_LEN_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_RESUME_CFG0_ADDR 0x009c
|
|
#define RESUME_SPI_WR_OFFSET 9
|
|
#define RESUME_SPI_WR_MASK 0x00000200
|
|
#define RESUME_SPI_RD_OFFSET 8
|
|
#define RESUME_SPI_RD_MASK 0x00000100
|
|
#define RESUME_CMD_DUAL_MODE_OFFSET 7
|
|
#define RESUME_CMD_DUAL_MODE_MASK 0x00000080
|
|
#define RESUME_CMD_QUAD_MODE_OFFSET 6
|
|
#define RESUME_CMD_QUAD_MODE_MASK 0x00000040
|
|
#define RESUME_ADDR_DUAL_MODE_OFFSET 5
|
|
#define RESUME_ADDR_DUAL_MODE_MASK 0x00000020
|
|
#define RESUME_ADDR_QUAD_MODE_OFFSET 4
|
|
#define RESUME_ADDR_QUAD_MODE_MASK 0x00000010
|
|
#define RESUME_CMODE_DUAL_MODE_OFFSET 3
|
|
#define RESUME_CMODE_DUAL_MODE_MASK 0x00000008
|
|
#define RESUME_CMODE_QUAD_MODE_OFFSET 2
|
|
#define RESUME_CMODE_QUAD_MODE_MASK 0x00000004
|
|
#define RESUME_DATA_DUAL_MODE_OFFSET 1
|
|
#define RESUME_DATA_DUAL_MODE_MASK 0x00000002
|
|
#define RESUME_DATA_QUAD_MODE_OFFSET 0
|
|
#define RESUME_DATA_QUAD_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_RESUME_CFG1_ADDR 0x00a0
|
|
#define RESUME_CMD_LEN_OFFSET 24
|
|
#define RESUME_CMD_LEN_MASK 0x1F000000
|
|
#define RESUME_ADDR_LEN_OFFSET 16
|
|
#define RESUME_ADDR_LEN_MASK 0x001F0000
|
|
#define RESUME_CMODE_LEN_OFFSET 8
|
|
#define RESUME_CMODE_LEN_MASK 0x00001F00
|
|
#define RESUME_DUMMY_LEN_OFFSET 0
|
|
#define RESUME_DUMMY_LEN_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_SUS_CFG0_ADDR 0x00a4
|
|
#define SUS_SPI_WR_OFFSET 9
|
|
#define SUS_SPI_WR_MASK 0x00000200
|
|
#define SUS_SPI_RD_OFFSET 8
|
|
#define SUS_SPI_RD_MASK 0x00000100
|
|
#define SUS_CMD_DUAL_MODE_OFFSET 7
|
|
#define SUS_CMD_DUAL_MODE_MASK 0x00000080
|
|
#define SUS_CMD_QUAD_MODE_OFFSET 6
|
|
#define SUS_CMD_QUAD_MODE_MASK 0x00000040
|
|
#define SUS_ADDR_DUAL_MODE_OFFSET 5
|
|
#define SUS_ADDR_DUAL_MODE_MASK 0x00000020
|
|
#define SUS_ADDR_QUAD_MODE_OFFSET 4
|
|
#define SUS_ADDR_QUAD_MODE_MASK 0x00000010
|
|
#define SUS_CMODE_DUAL_MODE_OFFSET 3
|
|
#define SUS_CMODE_DUAL_MODE_MASK 0x00000008
|
|
#define SUS_CMODE_QUAD_MODE_OFFSET 2
|
|
#define SUS_CMODE_QUAD_MODE_MASK 0x00000004
|
|
#define SUS_DATA_DUAL_MODE_OFFSET 1
|
|
#define SUS_DATA_DUAL_MODE_MASK 0x00000002
|
|
#define SUS_DATA_QUAD_MODE_OFFSET 0
|
|
#define SUS_DATA_QUAD_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SFC_SUS_CFG1_ADDR 0x00a8
|
|
#define SUS_CMD_LEN_OFFSET 24
|
|
#define SUS_CMD_LEN_MASK 0x1F000000
|
|
#define SUS_ADDR_LEN_OFFSET 16
|
|
#define SUS_ADDR_LEN_MASK 0x001F0000
|
|
#define SUS_CMODE_LEN_OFFSET 8
|
|
#define SUS_CMODE_LEN_MASK 0x00001F00
|
|
#define SUS_DUMMY_LEN_OFFSET 0
|
|
#define SUS_DUMMY_LEN_MASK 0x0000001F
|
|
|
|
//HW module read/write macro
|
|
#define SFC_RF_READ_REG(addr) SOC_READ_REG(SFC_RF_BASEADDR + addr)
|
|
#define SFC_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SFC_RF_BASEADDR + addr,value)
|