1102 lines
39 KiB
C
1102 lines
39 KiB
C
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//-----------------------------------
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#define CFG_HWQ_DUMMY0_ADDR 0x0000
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#define CFG_DUMMY0_OFFSET 0
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#define CFG_DUMMY0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ_DUMMY1_ADDR 0x0004
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#define CFG_DUMMY1_OFFSET 0
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#define CFG_DUMMY1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_END_DESC_TIMEOUT_ADDR 0x0008
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#define CFG_END_DESC_TIMEOUT_EN_OFFSET 16
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#define CFG_END_DESC_TIMEOUT_EN_MASK 0x00010000
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#define CFG_END_DESC_TIMEOUT_OFFSET 0
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#define CFG_END_DESC_TIMEOUT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_START_DESC_TIMEOUT_ADDR 0x000C
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#define CFG_START_DESC_TIMEOUT_EN_OFFSET 16
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#define CFG_START_DESC_TIMEOUT_EN_MASK 0x00010000
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#define CFG_START_DESC_TIMEOUT_OFFSET 0
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#define CFG_START_DESC_TIMEOUT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SCH_ADDR 0x0010
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#define CFG_HWQ_DBG_MODE_OFFSET 0
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#define CFG_HWQ_DBG_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_HWQ0_ADDR 0x0014
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#define CFG_DBG_HWQ0_START_END_VLD_OFFSET 6
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#define CFG_DBG_HWQ0_START_END_VLD_MASK 0x00000040
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#define CFG_DBG_HWQ0_POLL_CLR_OFFSET 5
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#define CFG_DBG_HWQ0_POLL_CLR_MASK 0x00000020
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#define CFG_DBG_HWQ0_RDY_OFFSET 4
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#define CFG_DBG_HWQ0_RDY_MASK 0x00000010
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#define CFG_DBG_HWQ0_EN_OFFSET 3
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#define CFG_DBG_HWQ0_EN_MASK 0x00000008
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#define CFG_DBG_HWQ0_CAP_OFFSET 1
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#define CFG_DBG_HWQ0_CAP_MASK 0x00000006
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#define CFG_DBG_HWQ0_TYPE_OFFSET 0
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#define CFG_DBG_HWQ0_TYPE_MASK 0x00000001
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//-----------------------------------
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#define CFG_HWQ0_PTR_ADDR 0x0018
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#define CFG_DBG_HWQ0_PTR_OFFSET 0
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#define CFG_DBG_HWQ0_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ0_START_ADDR 0x001C
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#define CFG_DBG_HWQ0_START_OFFSET 0
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#define CFG_DBG_HWQ0_START_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ0_END_ADDR 0x0020
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#define CFG_DBG_HWQ0_END_OFFSET 0
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#define CFG_DBG_HWQ0_END_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ0_RAND_ADDR 0x0024
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#define CFG_HWQ0_LOAD_SEED_OFFSET 8
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#define CFG_HWQ0_LOAD_SEED_MASK 0x00000100
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#define CFG_HWQ0_RND_SEED_OFFSET 0
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#define CFG_HWQ0_RND_SEED_MASK 0x000000FF
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//-----------------------------------
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#define CFG_HWQ1_ADDR 0x0028
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#define CFG_DBG_HWQ1_START_END_VLD_OFFSET 6
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#define CFG_DBG_HWQ1_START_END_VLD_MASK 0x00000040
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#define CFG_DBG_HWQ1_POLL_CLR_OFFSET 5
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#define CFG_DBG_HWQ1_POLL_CLR_MASK 0x00000020
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#define CFG_DBG_HWQ1_RDY_OFFSET 4
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#define CFG_DBG_HWQ1_RDY_MASK 0x00000010
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#define CFG_DBG_HWQ1_EN_OFFSET 3
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#define CFG_DBG_HWQ1_EN_MASK 0x00000008
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#define CFG_DBG_HWQ1_CAP_OFFSET 1
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#define CFG_DBG_HWQ1_CAP_MASK 0x00000006
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#define CFG_DBG_HWQ1_TYPE_OFFSET 0
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#define CFG_DBG_HWQ1_TYPE_MASK 0x00000001
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//-----------------------------------
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#define CFG_HWQ1_PTR_ADDR 0x002C
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#define CFG_DBG_HWQ1_PTR_OFFSET 0
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#define CFG_DBG_HWQ1_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ1_START_ADDR 0x0030
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#define CFG_DBG_HWQ1_START_OFFSET 0
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#define CFG_DBG_HWQ1_START_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ1_END_ADDR 0x0034
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#define CFG_DBG_HWQ1_END_OFFSET 0
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#define CFG_DBG_HWQ1_END_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ1_RAND_ADDR 0x0038
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#define CFG_HWQ1_LOAD_SEED_OFFSET 8
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#define CFG_HWQ1_LOAD_SEED_MASK 0x00000100
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#define CFG_HWQ1_RND_SEED_OFFSET 0
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#define CFG_HWQ1_RND_SEED_MASK 0x000000FF
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//-----------------------------------
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#define CFG_HWQ2_ADDR 0x003C
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#define CFG_DBG_HWQ2_START_END_VLD_OFFSET 6
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#define CFG_DBG_HWQ2_START_END_VLD_MASK 0x00000040
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#define CFG_DBG_HWQ2_POLL_CLR_OFFSET 5
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#define CFG_DBG_HWQ2_POLL_CLR_MASK 0x00000020
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#define CFG_DBG_HWQ2_RDY_OFFSET 4
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#define CFG_DBG_HWQ2_RDY_MASK 0x00000010
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#define CFG_DBG_HWQ2_EN_OFFSET 3
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#define CFG_DBG_HWQ2_EN_MASK 0x00000008
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#define CFG_DBG_HWQ2_CAP_OFFSET 1
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#define CFG_DBG_HWQ2_CAP_MASK 0x00000006
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#define CFG_DBG_HWQ2_TYPE_OFFSET 0
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#define CFG_DBG_HWQ2_TYPE_MASK 0x00000001
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//-----------------------------------
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#define CFG_HWQ2_PTR_ADDR 0x0040
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#define CFG_DBG_HWQ2_PTR_OFFSET 0
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#define CFG_DBG_HWQ2_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ2_START_ADDR 0x0044
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#define CFG_DBG_HWQ2_START_OFFSET 0
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#define CFG_DBG_HWQ2_START_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ2_END_ADDR 0x0048
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#define CFG_DBG_HWQ2_END_OFFSET 0
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#define CFG_DBG_HWQ2_END_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ2_RAND_ADDR 0x004C
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#define CFG_HWQ2_LOAD_SEED_OFFSET 8
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#define CFG_HWQ2_LOAD_SEED_MASK 0x00000100
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#define CFG_HWQ2_RND_SEED_OFFSET 0
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#define CFG_HWQ2_RND_SEED_MASK 0x000000FF
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//-----------------------------------
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#define CFG_HWQ3_ADDR 0x0050
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#define CFG_DBG_HWQ3_START_END_VLD_OFFSET 6
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#define CFG_DBG_HWQ3_START_END_VLD_MASK 0x00000040
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#define CFG_DBG_HWQ3_POLL_CLR_OFFSET 5
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#define CFG_DBG_HWQ3_POLL_CLR_MASK 0x00000020
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#define CFG_DBG_HWQ3_RDY_OFFSET 4
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#define CFG_DBG_HWQ3_RDY_MASK 0x00000010
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#define CFG_DBG_HWQ3_EN_OFFSET 3
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#define CFG_DBG_HWQ3_EN_MASK 0x00000008
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#define CFG_DBG_HWQ3_CAP_OFFSET 1
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#define CFG_DBG_HWQ3_CAP_MASK 0x00000006
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#define CFG_DBG_HWQ3_TYPE_OFFSET 0
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#define CFG_DBG_HWQ3_TYPE_MASK 0x00000001
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//-----------------------------------
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#define CFG_HWQ3_PTR_ADDR 0x0054
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#define CFG_DBG_HWQ3_PTR_OFFSET 0
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#define CFG_DBG_HWQ3_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ3_START_ADDR 0x0058
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#define CFG_DBG_HWQ3_START_OFFSET 0
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#define CFG_DBG_HWQ3_START_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ3_END_ADDR 0x005C
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#define CFG_DBG_HWQ3_END_OFFSET 0
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#define CFG_DBG_HWQ3_END_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ3_RAND_ADDR 0x0060
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#define CFG_HWQ3_LOAD_SEED_OFFSET 8
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#define CFG_HWQ3_LOAD_SEED_MASK 0x00000100
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#define CFG_HWQ3_RND_SEED_OFFSET 0
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#define CFG_HWQ3_RND_SEED_MASK 0x000000FF
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//-----------------------------------
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#define CFG_HWQ4_ADDR 0x0064
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#define CFG_DBG_HWQ4_START_END_VLD_OFFSET 6
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#define CFG_DBG_HWQ4_START_END_VLD_MASK 0x00000040
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#define CFG_DBG_HWQ4_POLL_CLR_OFFSET 5
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#define CFG_DBG_HWQ4_POLL_CLR_MASK 0x00000020
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#define CFG_DBG_HWQ4_RDY_OFFSET 4
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#define CFG_DBG_HWQ4_RDY_MASK 0x00000010
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#define CFG_DBG_HWQ4_EN_OFFSET 3
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#define CFG_DBG_HWQ4_EN_MASK 0x00000008
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#define CFG_DBG_HWQ4_CAP_OFFSET 1
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#define CFG_DBG_HWQ4_CAP_MASK 0x00000006
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#define CFG_DBG_HWQ4_TYPE_OFFSET 0
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#define CFG_DBG_HWQ4_TYPE_MASK 0x00000001
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//-----------------------------------
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#define CFG_HWQ4_PTR_ADDR 0x0068
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#define CFG_DBG_HWQ4_PTR_OFFSET 0
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#define CFG_DBG_HWQ4_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ4_START_ADDR 0x006C
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#define CFG_DBG_HWQ4_START_OFFSET 0
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#define CFG_DBG_HWQ4_START_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ4_END_ADDR 0x0070
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#define CFG_DBG_HWQ4_END_OFFSET 0
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#define CFG_DBG_HWQ4_END_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_HWQ4_RAND_ADDR 0x0074
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#define CFG_HWQ4_LOAD_SEED_OFFSET 8
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#define CFG_HWQ4_LOAD_SEED_MASK 0x00000100
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#define CFG_HWQ4_RND_SEED_OFFSET 0
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#define CFG_HWQ4_RND_SEED_MASK 0x000000FF
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//-----------------------------------
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#define CFG_Q0_PTR_ADDR 0x0078
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#define CFG_Q0_PTR_OFFSET 0
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#define CFG_Q0_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q1_PTR_ADDR 0x007C
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#define CFG_Q1_PTR_OFFSET 0
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#define CFG_Q1_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q2_PTR_ADDR 0x0080
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#define CFG_Q2_PTR_OFFSET 0
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#define CFG_Q2_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q3_PTR_ADDR 0x0084
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#define CFG_Q3_PTR_OFFSET 0
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#define CFG_Q3_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q4_PTR_ADDR 0x0088
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#define CFG_Q4_PTR_OFFSET 0
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#define CFG_Q4_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q5_PTR_ADDR 0x008c
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#define CFG_Q5_PTR_OFFSET 0
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#define CFG_Q5_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q6_PTR_ADDR 0x0090
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#define CFG_Q6_PTR_OFFSET 0
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#define CFG_Q6_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q7_PTR_ADDR 0x0094
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#define CFG_Q7_PTR_OFFSET 0
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#define CFG_Q7_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q8_PTR_ADDR 0x0098
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#define CFG_Q8_PTR_OFFSET 0
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#define CFG_Q8_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q9_PTR_ADDR 0x009c
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#define CFG_Q9_PTR_OFFSET 0
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#define CFG_Q9_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q10_PTR_ADDR 0x00a0
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#define CFG_Q10_PTR_OFFSET 0
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#define CFG_Q10_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q11_PTR_ADDR 0x00a4
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#define CFG_Q11_PTR_OFFSET 0
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#define CFG_Q11_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q12_PTR_ADDR 0x00a8
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#define CFG_Q12_PTR_OFFSET 0
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#define CFG_Q12_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q13_PTR_ADDR 0x00ac
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#define CFG_Q13_PTR_OFFSET 0
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#define CFG_Q13_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q14_PTR_ADDR 0x00b0
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#define CFG_Q14_PTR_OFFSET 0
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#define CFG_Q14_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q15_PTR_ADDR 0x00b4
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#define CFG_Q15_PTR_OFFSET 0
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#define CFG_Q15_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q16_PTR_ADDR 0x00b8
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#define CFG_Q16_PTR_OFFSET 0
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#define CFG_Q16_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q17_PTR_ADDR 0x00bc
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#define CFG_Q17_PTR_OFFSET 0
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#define CFG_Q17_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q18_PTR_ADDR 0x00c0
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#define CFG_Q18_PTR_OFFSET 0
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#define CFG_Q18_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q19_PTR_ADDR 0x00c4
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#define CFG_Q19_PTR_OFFSET 0
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#define CFG_Q19_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q20_PTR_ADDR 0x00c8
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#define CFG_Q20_PTR_OFFSET 0
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#define CFG_Q20_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q21_PTR_ADDR 0x00cc
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#define CFG_Q21_PTR_OFFSET 0
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#define CFG_Q21_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q22_PTR_ADDR 0x00d0
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#define CFG_Q22_PTR_OFFSET 0
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#define CFG_Q22_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q23_PTR_ADDR 0x00d4
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#define CFG_Q23_PTR_OFFSET 0
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#define CFG_Q23_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_Q_ENA_ADDR 0x00d8
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#define CFG_QUEUE23_ENA_OFFSET 23
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#define CFG_QUEUE23_ENA_MASK 0x00800000
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#define CFG_QUEUE22_ENA_OFFSET 22
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#define CFG_QUEUE22_ENA_MASK 0x00400000
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#define CFG_QUEUE21_ENA_OFFSET 21
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#define CFG_QUEUE21_ENA_MASK 0x00200000
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#define CFG_QUEUE20_ENA_OFFSET 20
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#define CFG_QUEUE20_ENA_MASK 0x00100000
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#define CFG_QUEUE19_ENA_OFFSET 19
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#define CFG_QUEUE19_ENA_MASK 0x00080000
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#define CFG_QUEUE18_ENA_OFFSET 18
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#define CFG_QUEUE18_ENA_MASK 0x00040000
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#define CFG_QUEUE17_ENA_OFFSET 17
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#define CFG_QUEUE17_ENA_MASK 0x00020000
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#define CFG_QUEUE16_ENA_OFFSET 16
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#define CFG_QUEUE16_ENA_MASK 0x00010000
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#define CFG_QUEUE15_ENA_OFFSET 15
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#define CFG_QUEUE15_ENA_MASK 0x00008000
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#define CFG_QUEUE14_ENA_OFFSET 14
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#define CFG_QUEUE14_ENA_MASK 0x00004000
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#define CFG_QUEUE13_ENA_OFFSET 13
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#define CFG_QUEUE13_ENA_MASK 0x00002000
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#define CFG_QUEUE12_ENA_OFFSET 12
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#define CFG_QUEUE12_ENA_MASK 0x00001000
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#define CFG_QUEUE11_ENA_OFFSET 11
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#define CFG_QUEUE11_ENA_MASK 0x00000800
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#define CFG_QUEUE10_ENA_OFFSET 10
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#define CFG_QUEUE10_ENA_MASK 0x00000400
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#define CFG_QUEUE9_ENA_OFFSET 9
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#define CFG_QUEUE9_ENA_MASK 0x00000200
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#define CFG_QUEUE8_ENA_OFFSET 8
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#define CFG_QUEUE8_ENA_MASK 0x00000100
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#define CFG_QUEUE7_ENA_OFFSET 7
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#define CFG_QUEUE7_ENA_MASK 0x00000080
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#define CFG_QUEUE6_ENA_OFFSET 6
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#define CFG_QUEUE6_ENA_MASK 0x00000040
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#define CFG_QUEUE5_ENA_OFFSET 5
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#define CFG_QUEUE5_ENA_MASK 0x00000020
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#define CFG_QUEUE4_ENA_OFFSET 4
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#define CFG_QUEUE4_ENA_MASK 0x00000010
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#define CFG_QUEUE3_ENA_OFFSET 3
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#define CFG_QUEUE3_ENA_MASK 0x00000008
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#define CFG_QUEUE2_ENA_OFFSET 2
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#define CFG_QUEUE2_ENA_MASK 0x00000004
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#define CFG_QUEUE1_ENA_OFFSET 1
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#define CFG_QUEUE1_ENA_MASK 0x00000002
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#define CFG_QUEUE0_ENA_OFFSET 0
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#define CFG_QUEUE0_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_Q11_Q0_CAP_ADDR 0x00dc
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#define CFG_Q11_CAP_OFFSET 22
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#define CFG_Q11_CAP_MASK 0x00C00000
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#define CFG_Q10_CAP_OFFSET 20
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#define CFG_Q10_CAP_MASK 0x00300000
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#define CFG_Q9_CAP_OFFSET 18
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#define CFG_Q9_CAP_MASK 0x000C0000
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#define CFG_Q8_CAP_OFFSET 16
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#define CFG_Q8_CAP_MASK 0x00030000
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#define CFG_Q7_CAP_OFFSET 14
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#define CFG_Q7_CAP_MASK 0x0000C000
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#define CFG_Q6_CAP_OFFSET 12
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#define CFG_Q6_CAP_MASK 0x00003000
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#define CFG_Q5_CAP_OFFSET 10
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#define CFG_Q5_CAP_MASK 0x00000C00
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#define CFG_Q4_CAP_OFFSET 8
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#define CFG_Q4_CAP_MASK 0x00000300
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#define CFG_Q3_CAP_OFFSET 6
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#define CFG_Q3_CAP_MASK 0x000000C0
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#define CFG_Q2_CAP_OFFSET 4
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#define CFG_Q2_CAP_MASK 0x00000030
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#define CFG_Q1_CAP_OFFSET 2
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#define CFG_Q1_CAP_MASK 0x0000000C
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#define CFG_Q0_CAP_OFFSET 0
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#define CFG_Q0_CAP_MASK 0x00000003
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//-----------------------------------
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#define CFG_Q23_Q12_CAP_ADDR 0x00e0
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#define CFG_Q23_CAP_OFFSET 22
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#define CFG_Q23_CAP_MASK 0x00C00000
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#define CFG_Q22_CAP_OFFSET 20
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#define CFG_Q22_CAP_MASK 0x00300000
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#define CFG_Q21_CAP_OFFSET 18
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#define CFG_Q21_CAP_MASK 0x000C0000
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#define CFG_Q20_CAP_OFFSET 16
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#define CFG_Q20_CAP_MASK 0x00030000
|
|
#define CFG_Q19_CAP_OFFSET 14
|
|
#define CFG_Q19_CAP_MASK 0x0000C000
|
|
#define CFG_Q18_CAP_OFFSET 12
|
|
#define CFG_Q18_CAP_MASK 0x00003000
|
|
#define CFG_Q17_CAP_OFFSET 10
|
|
#define CFG_Q17_CAP_MASK 0x00000C00
|
|
#define CFG_Q16_CAP_OFFSET 8
|
|
#define CFG_Q16_CAP_MASK 0x00000300
|
|
#define CFG_Q15_CAP_OFFSET 6
|
|
#define CFG_Q15_CAP_MASK 0x000000C0
|
|
#define CFG_Q14_CAP_OFFSET 4
|
|
#define CFG_Q14_CAP_MASK 0x00000030
|
|
#define CFG_Q13_CAP_OFFSET 2
|
|
#define CFG_Q13_CAP_MASK 0x0000000C
|
|
#define CFG_Q12_CAP_OFFSET 0
|
|
#define CFG_Q12_CAP_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_Q_TYPE_ADDR 0x00e4
|
|
#define CFG_QUEUE23_TYPE_OFFSET 23
|
|
#define CFG_QUEUE23_TYPE_MASK 0x00800000
|
|
#define CFG_QUEUE22_TYPE_OFFSET 22
|
|
#define CFG_QUEUE22_TYPE_MASK 0x00400000
|
|
#define CFG_QUEUE21_TYPE_OFFSET 21
|
|
#define CFG_QUEUE21_TYPE_MASK 0x00200000
|
|
#define CFG_QUEUE20_TYPE_OFFSET 20
|
|
#define CFG_QUEUE20_TYPE_MASK 0x00100000
|
|
#define CFG_QUEUE19_TYPE_OFFSET 19
|
|
#define CFG_QUEUE19_TYPE_MASK 0x00080000
|
|
#define CFG_QUEUE18_TYPE_OFFSET 18
|
|
#define CFG_QUEUE18_TYPE_MASK 0x00040000
|
|
#define CFG_QUEUE17_TYPE_OFFSET 17
|
|
#define CFG_QUEUE17_TYPE_MASK 0x00020000
|
|
#define CFG_QUEUE16_TYPE_OFFSET 16
|
|
#define CFG_QUEUE16_TYPE_MASK 0x00010000
|
|
#define CFG_QUEUE15_TYPE_OFFSET 15
|
|
#define CFG_QUEUE15_TYPE_MASK 0x00008000
|
|
#define CFG_QUEUE14_TYPE_OFFSET 14
|
|
#define CFG_QUEUE14_TYPE_MASK 0x00004000
|
|
#define CFG_QUEUE13_TYPE_OFFSET 13
|
|
#define CFG_QUEUE13_TYPE_MASK 0x00002000
|
|
#define CFG_QUEUE12_TYPE_OFFSET 12
|
|
#define CFG_QUEUE12_TYPE_MASK 0x00001000
|
|
#define CFG_QUEUE11_TYPE_OFFSET 11
|
|
#define CFG_QUEUE11_TYPE_MASK 0x00000800
|
|
#define CFG_QUEUE10_TYPE_OFFSET 10
|
|
#define CFG_QUEUE10_TYPE_MASK 0x00000400
|
|
#define CFG_QUEUE9_TYPE_OFFSET 9
|
|
#define CFG_QUEUE9_TYPE_MASK 0x00000200
|
|
#define CFG_QUEUE8_TYPE_OFFSET 8
|
|
#define CFG_QUEUE8_TYPE_MASK 0x00000100
|
|
#define CFG_QUEUE7_TYPE_OFFSET 7
|
|
#define CFG_QUEUE7_TYPE_MASK 0x00000080
|
|
#define CFG_QUEUE6_TYPE_OFFSET 6
|
|
#define CFG_QUEUE6_TYPE_MASK 0x00000040
|
|
#define CFG_QUEUE5_TYPE_OFFSET 5
|
|
#define CFG_QUEUE5_TYPE_MASK 0x00000020
|
|
#define CFG_QUEUE4_TYPE_OFFSET 4
|
|
#define CFG_QUEUE4_TYPE_MASK 0x00000010
|
|
#define CFG_QUEUE3_TYPE_OFFSET 3
|
|
#define CFG_QUEUE3_TYPE_MASK 0x00000008
|
|
#define CFG_QUEUE2_TYPE_OFFSET 2
|
|
#define CFG_QUEUE2_TYPE_MASK 0x00000004
|
|
#define CFG_QUEUE1_TYPE_OFFSET 1
|
|
#define CFG_QUEUE1_TYPE_MASK 0x00000002
|
|
#define CFG_QUEUE0_TYPE_OFFSET 0
|
|
#define CFG_QUEUE0_TYPE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_Q_STATUS_ADDR 0x00e8
|
|
#define QUEUE_23_STATUS_OFFSET 23
|
|
#define QUEUE_23_STATUS_MASK 0x00800000
|
|
#define QUEUE_22_STATUS_OFFSET 22
|
|
#define QUEUE_22_STATUS_MASK 0x00400000
|
|
#define QUEUE_21_STATUS_OFFSET 21
|
|
#define QUEUE_21_STATUS_MASK 0x00200000
|
|
#define QUEUE_20_STATUS_OFFSET 20
|
|
#define QUEUE_20_STATUS_MASK 0x00100000
|
|
#define QUEUE_19_STATUS_OFFSET 19
|
|
#define QUEUE_19_STATUS_MASK 0x00080000
|
|
#define QUEUE_18_STATUS_OFFSET 18
|
|
#define QUEUE_18_STATUS_MASK 0x00040000
|
|
#define QUEUE_17_STATUS_OFFSET 17
|
|
#define QUEUE_17_STATUS_MASK 0x00020000
|
|
#define QUEUE_16_STATUS_OFFSET 16
|
|
#define QUEUE_16_STATUS_MASK 0x00010000
|
|
#define QUEUE_15_STATUS_OFFSET 15
|
|
#define QUEUE_15_STATUS_MASK 0x00008000
|
|
#define QUEUE_14_STATUS_OFFSET 14
|
|
#define QUEUE_14_STATUS_MASK 0x00004000
|
|
#define QUEUE_13_STATUS_OFFSET 13
|
|
#define QUEUE_13_STATUS_MASK 0x00002000
|
|
#define QUEUE_12_STATUS_OFFSET 12
|
|
#define QUEUE_12_STATUS_MASK 0x00001000
|
|
#define QUEUE_11_STATUS_OFFSET 11
|
|
#define QUEUE_11_STATUS_MASK 0x00000800
|
|
#define QUEUE_10_STATUS_OFFSET 10
|
|
#define QUEUE_10_STATUS_MASK 0x00000400
|
|
#define QUEUE_9_STATUS_OFFSET 9
|
|
#define QUEUE_9_STATUS_MASK 0x00000200
|
|
#define QUEUE_8_STATUS_OFFSET 8
|
|
#define QUEUE_8_STATUS_MASK 0x00000100
|
|
#define QUEUE_7_STATUS_OFFSET 7
|
|
#define QUEUE_7_STATUS_MASK 0x00000080
|
|
#define QUEUE_6_STATUS_OFFSET 6
|
|
#define QUEUE_6_STATUS_MASK 0x00000040
|
|
#define QUEUE_5_STATUS_OFFSET 5
|
|
#define QUEUE_5_STATUS_MASK 0x00000020
|
|
#define QUEUE_4_STATUS_OFFSET 4
|
|
#define QUEUE_4_STATUS_MASK 0x00000010
|
|
#define QUEUE_3_STATUS_OFFSET 3
|
|
#define QUEUE_3_STATUS_MASK 0x00000008
|
|
#define QUEUE_2_STATUS_OFFSET 2
|
|
#define QUEUE_2_STATUS_MASK 0x00000004
|
|
#define QUEUE_1_STATUS_OFFSET 1
|
|
#define QUEUE_1_STATUS_MASK 0x00000002
|
|
#define QUEUE_0_STATUS_OFFSET 0
|
|
#define QUEUE_0_STATUS_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCHEDULE_ADDR 0x00ec
|
|
#define CFG_SCH_EN_OFFSET 31
|
|
#define CFG_SCH_EN_MASK 0x80000000
|
|
#define CFG_SCH_CMD_NUM_OFFSET 19
|
|
#define CFG_SCH_CMD_NUM_MASK 0x7FF80000
|
|
#define CFG_SCH_WR_TRIG_OFFSET 18
|
|
#define CFG_SCH_WR_TRIG_MASK 0x00040000
|
|
#define CFG_SCH_SELF_RECUR_EN_OFFSET 17
|
|
#define CFG_SCH_SELF_RECUR_EN_MASK 0x00020000
|
|
#define SCH_STATUS_OFFSET 16
|
|
#define SCH_STATUS_MASK 0x00010000
|
|
#define SCH_WR_TRIG_ENABLE_OFFSET 15
|
|
#define SCH_WR_TRIG_ENABLE_MASK 0x00008000
|
|
#define CFG_SCH_CLR_OFFSET 14
|
|
#define CFG_SCH_CLR_MASK 0x00004000
|
|
#define CFG_SCH_UNIT_SEL_OFFSET 2
|
|
#define CFG_SCH_UNIT_SEL_MASK 0x00000004
|
|
#define SCH_CUR_NUM_OFFSET 0
|
|
#define SCH_CUR_NUM_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCH_PTR_ADDR 0x00f0
|
|
#define CFG_SCH_PTR_OFFSET 0
|
|
#define CFG_SCH_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_NULL_POLL_ADDR 0x00f4
|
|
#define CFG_HWQ_EMP_SEL_OFFSET 10
|
|
#define CFG_HWQ_EMP_SEL_MASK 0x00000400
|
|
#define CFG_POLL_INTERVAL_OFFSET 0
|
|
#define CFG_POLL_INTERVAL_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_POLL_CLR_ADDR 0x00f8
|
|
#define CFG_POLL_CLR_23_OFFSET 23
|
|
#define CFG_POLL_CLR_23_MASK 0x00800000
|
|
#define CFG_POLL_CLR_22_OFFSET 22
|
|
#define CFG_POLL_CLR_22_MASK 0x00400000
|
|
#define CFG_POLL_CLR_21_OFFSET 21
|
|
#define CFG_POLL_CLR_21_MASK 0x00200000
|
|
#define CFG_POLL_CLR_20_OFFSET 20
|
|
#define CFG_POLL_CLR_20_MASK 0x00100000
|
|
#define CFG_POLL_CLR_19_OFFSET 19
|
|
#define CFG_POLL_CLR_19_MASK 0x00080000
|
|
#define CFG_POLL_CLR_18_OFFSET 18
|
|
#define CFG_POLL_CLR_18_MASK 0x00040000
|
|
#define CFG_POLL_CLR_17_OFFSET 17
|
|
#define CFG_POLL_CLR_17_MASK 0x00020000
|
|
#define CFG_POLL_CLR_16_OFFSET 16
|
|
#define CFG_POLL_CLR_16_MASK 0x00010000
|
|
#define CFG_POLL_CLR_15_OFFSET 15
|
|
#define CFG_POLL_CLR_15_MASK 0x00008000
|
|
#define CFG_POLL_CLR_14_OFFSET 14
|
|
#define CFG_POLL_CLR_14_MASK 0x00004000
|
|
#define CFG_POLL_CLR_13_OFFSET 13
|
|
#define CFG_POLL_CLR_13_MASK 0x00002000
|
|
#define CFG_POLL_CLR_12_OFFSET 12
|
|
#define CFG_POLL_CLR_12_MASK 0x00001000
|
|
#define CFG_POLL_CLR_11_OFFSET 11
|
|
#define CFG_POLL_CLR_11_MASK 0x00000800
|
|
#define CFG_POLL_CLR_10_OFFSET 10
|
|
#define CFG_POLL_CLR_10_MASK 0x00000400
|
|
#define CFG_POLL_CLR_9_OFFSET 9
|
|
#define CFG_POLL_CLR_9_MASK 0x00000200
|
|
#define CFG_POLL_CLR_8_OFFSET 8
|
|
#define CFG_POLL_CLR_8_MASK 0x00000100
|
|
#define CFG_POLL_CLR_7_OFFSET 7
|
|
#define CFG_POLL_CLR_7_MASK 0x00000080
|
|
#define CFG_POLL_CLR_6_OFFSET 6
|
|
#define CFG_POLL_CLR_6_MASK 0x00000040
|
|
#define CFG_POLL_CLR_5_OFFSET 5
|
|
#define CFG_POLL_CLR_5_MASK 0x00000020
|
|
#define CFG_POLL_CLR_4_OFFSET 4
|
|
#define CFG_POLL_CLR_4_MASK 0x00000010
|
|
#define CFG_POLL_CLR_3_OFFSET 3
|
|
#define CFG_POLL_CLR_3_MASK 0x00000008
|
|
#define CFG_POLL_CLR_2_OFFSET 2
|
|
#define CFG_POLL_CLR_2_MASK 0x00000004
|
|
#define CFG_POLL_CLR_1_OFFSET 1
|
|
#define CFG_POLL_CLR_1_MASK 0x00000002
|
|
#define CFG_POLL_CLR_0_OFFSET 0
|
|
#define CFG_POLL_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BKOFF_DC_ADDR 0x00fc
|
|
#define CFG_BPC0_DC_OFFSET 24
|
|
#define CFG_BPC0_DC_MASK 0xFF000000
|
|
#define CFG_BPC1_DC_OFFSET 16
|
|
#define CFG_BPC1_DC_MASK 0x00FF0000
|
|
#define CFG_BPC2_DC_OFFSET 8
|
|
#define CFG_BPC2_DC_MASK 0x0000FF00
|
|
#define CFG_BPC3_DC_OFFSET 0
|
|
#define CFG_BPC3_DC_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BKOFF_CA23_CW_ADDR 0x0100
|
|
#define CFG_BPC0_CA23_CW_OFFSET 24
|
|
#define CFG_BPC0_CA23_CW_MASK 0xFF000000
|
|
#define CFG_BPC1_CA23_CW_OFFSET 16
|
|
#define CFG_BPC1_CA23_CW_MASK 0x00FF0000
|
|
#define CFG_BPC2_CA23_CW_OFFSET 8
|
|
#define CFG_BPC2_CA23_CW_MASK 0x0000FF00
|
|
#define CFG_BPC3_CA23_CW_OFFSET 0
|
|
#define CFG_BPC3_CA23_CW_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BKOFF_CA01_CW_ADDR 0x0104
|
|
#define CFG_BPC0_CA01_CW_OFFSET 24
|
|
#define CFG_BPC0_CA01_CW_MASK 0xFF000000
|
|
#define CFG_BPC1_CA01_CW_OFFSET 16
|
|
#define CFG_BPC1_CA01_CW_MASK 0x00FF0000
|
|
#define CFG_BPC2_CA01_CW_OFFSET 8
|
|
#define CFG_BPC2_CA01_CW_MASK 0x0000FF00
|
|
#define CFG_BPC3_CA01_CW_OFFSET 0
|
|
#define CFG_BPC3_CA01_CW_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCH_CUR_PTR_ADDR 0x0108
|
|
#define SCH_CUR_PTR_OFFSET 0
|
|
#define SCH_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_HWQ_DIS_DONE_INT_STATUS_ADDR 0x010c
|
|
#define RO_HWQ_DIS_DONE_INT_STATUS_OFFSET 0
|
|
#define RO_HWQ_DIS_DONE_INT_STATUS_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_ADDR 0x0110
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_23_OFFSET 23
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_23_MASK 0x00800000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_22_OFFSET 22
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_22_MASK 0x00400000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_21_OFFSET 21
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_21_MASK 0x00200000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_20_OFFSET 20
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_20_MASK 0x00100000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_19_OFFSET 19
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_19_MASK 0x00080000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_18_OFFSET 18
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_18_MASK 0x00040000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_17_OFFSET 17
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_17_MASK 0x00020000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_16_OFFSET 16
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_16_MASK 0x00010000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_15_OFFSET 15
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_15_MASK 0x00008000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_14_OFFSET 14
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_14_MASK 0x00004000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_13_OFFSET 13
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_13_MASK 0x00002000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_12_OFFSET 12
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_12_MASK 0x00001000
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_11_OFFSET 11
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_11_MASK 0x00000800
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_10_OFFSET 10
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_10_MASK 0x00000400
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_9_OFFSET 9
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_9_MASK 0x00000200
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_8_OFFSET 8
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_8_MASK 0x00000100
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_7_OFFSET 7
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_7_MASK 0x00000080
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_6_OFFSET 6
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_6_MASK 0x00000040
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_5_OFFSET 5
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_5_MASK 0x00000020
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_4_OFFSET 4
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_3_OFFSET 3
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_2_OFFSET 2
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_1_OFFSET 1
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_0_OFFSET 0
|
|
#define CFG_HWQ_DIS_DONE_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_HWQ_START_DESC_ERR_INT_ADDR 0x0114
|
|
#define RO_HWQ_START_DESC_ERR_INT_OFFSET 0
|
|
#define RO_HWQ_START_DESC_ERR_INT_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_ADDR 0x0118
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_23_OFFSET 23
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_23_MASK 0x00800000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_22_OFFSET 22
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_22_MASK 0x00400000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_21_OFFSET 21
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_21_MASK 0x00200000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_20_OFFSET 20
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_20_MASK 0x00100000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_19_OFFSET 19
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_19_MASK 0x00080000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_18_OFFSET 18
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_18_MASK 0x00040000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_17_OFFSET 17
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_17_MASK 0x00020000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_16_OFFSET 16
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_16_MASK 0x00010000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_15_OFFSET 15
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_15_MASK 0x00008000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_14_OFFSET 14
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_14_MASK 0x00004000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_13_OFFSET 13
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_13_MASK 0x00002000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_12_OFFSET 12
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_12_MASK 0x00001000
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_11_OFFSET 11
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_11_MASK 0x00000800
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_10_OFFSET 10
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_10_MASK 0x00000400
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_9_OFFSET 9
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_9_MASK 0x00000200
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_8_OFFSET 8
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_8_MASK 0x00000100
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_7_OFFSET 7
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_7_MASK 0x00000080
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_6_OFFSET 6
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_6_MASK 0x00000040
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_5_OFFSET 5
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_5_MASK 0x00000020
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_4_OFFSET 4
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_3_OFFSET 3
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_2_OFFSET 2
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_1_OFFSET 1
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_0_OFFSET 0
|
|
#define CFG_HWQ_START_DESC_ERR_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_HWQ_END_DESC_ERR_INT_ADDR 0x011C
|
|
#define RO_HWQ_END_DESC_ERR_INT_OFFSET 0
|
|
#define RO_HWQ_END_DESC_ERR_INT_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_ADDR 0x0120
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_23_OFFSET 23
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_23_MASK 0x00800000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_22_OFFSET 22
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_22_MASK 0x00400000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_21_OFFSET 21
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_21_MASK 0x00200000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_20_OFFSET 20
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_20_MASK 0x00100000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_19_OFFSET 19
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_19_MASK 0x00080000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_18_OFFSET 18
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_18_MASK 0x00040000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_17_OFFSET 17
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_17_MASK 0x00020000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_16_OFFSET 16
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_16_MASK 0x00010000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_15_OFFSET 15
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_15_MASK 0x00008000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_14_OFFSET 14
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_14_MASK 0x00004000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_13_OFFSET 13
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_13_MASK 0x00002000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_12_OFFSET 12
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_12_MASK 0x00001000
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_11_OFFSET 11
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_11_MASK 0x00000800
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_10_OFFSET 10
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_10_MASK 0x00000400
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_9_OFFSET 9
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_9_MASK 0x00000200
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_8_OFFSET 8
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_8_MASK 0x00000100
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_7_OFFSET 7
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_7_MASK 0x00000080
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_6_OFFSET 6
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_6_MASK 0x00000040
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_5_OFFSET 5
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_5_MASK 0x00000020
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_4_OFFSET 4
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_3_OFFSET 3
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_2_OFFSET 2
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_1_OFFSET 1
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_0_OFFSET 0
|
|
#define CFG_HWQ_END_DESC_ERR_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_HWQ_TX_UNDERRUN_INT_ADDR 0x0124
|
|
#define RO_HWQ_TX_UNDERRUN_INT_OFFSET 0
|
|
#define RO_HWQ_TX_UNDERRUN_INT_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_ADDR 0x0128
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_23_OFFSET 23
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_23_MASK 0x00800000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_22_OFFSET 22
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_22_MASK 0x00400000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_21_OFFSET 21
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_21_MASK 0x00200000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_20_OFFSET 20
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_20_MASK 0x00100000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_19_OFFSET 19
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_19_MASK 0x00080000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_18_OFFSET 18
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_18_MASK 0x00040000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_17_OFFSET 17
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_17_MASK 0x00020000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_16_OFFSET 16
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_16_MASK 0x00010000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_15_OFFSET 15
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_15_MASK 0x00008000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_14_OFFSET 14
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_14_MASK 0x00004000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_13_OFFSET 13
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_13_MASK 0x00002000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_12_OFFSET 12
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_12_MASK 0x00001000
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_11_OFFSET 11
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_11_MASK 0x00000800
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_10_OFFSET 10
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_10_MASK 0x00000400
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_9_OFFSET 9
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_9_MASK 0x00000200
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_8_OFFSET 8
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_8_MASK 0x00000100
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_7_OFFSET 7
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_7_MASK 0x00000080
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_6_OFFSET 6
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_6_MASK 0x00000040
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_5_OFFSET 5
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_5_MASK 0x00000020
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_4_OFFSET 4
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_3_OFFSET 3
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_2_OFFSET 2
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_1_OFFSET 1
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_0_OFFSET 0
|
|
#define CFG_HWQ_TX_UNDERRUN_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_HWQ_TX_DONE_INT_ADDR 0x012C
|
|
#define CFG_TX_DONE_INT_SEL_OFFSET 24
|
|
#define CFG_TX_DONE_INT_SEL_MASK 0x01000000
|
|
#define RO_MPDU_TX_DONE_INT_OFFSET 0
|
|
#define RO_MPDU_TX_DONE_INT_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_HWQ_TX_DONE_INT_CLR_ADDR 0x0130
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_23_OFFSET 23
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_23_MASK 0x00800000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_22_OFFSET 22
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_22_MASK 0x00400000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_21_OFFSET 21
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_21_MASK 0x00200000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_20_OFFSET 20
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_20_MASK 0x00100000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_19_OFFSET 19
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_19_MASK 0x00080000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_18_OFFSET 18
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_18_MASK 0x00040000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_17_OFFSET 17
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_17_MASK 0x00020000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_16_OFFSET 16
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_16_MASK 0x00010000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_15_OFFSET 15
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_15_MASK 0x00008000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_14_OFFSET 14
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_14_MASK 0x00004000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_13_OFFSET 13
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_13_MASK 0x00002000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_12_OFFSET 12
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_12_MASK 0x00001000
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_11_OFFSET 11
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_11_MASK 0x00000800
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_10_OFFSET 10
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_10_MASK 0x00000400
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_9_OFFSET 9
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_9_MASK 0x00000200
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_8_OFFSET 8
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_8_MASK 0x00000100
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_7_OFFSET 7
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_7_MASK 0x00000080
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_6_OFFSET 6
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_6_MASK 0x00000040
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_5_OFFSET 5
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_5_MASK 0x00000020
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_4_OFFSET 4
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_3_OFFSET 3
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_2_OFFSET 2
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_1_OFFSET 1
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_0_OFFSET 0
|
|
#define CFG_HWQ_MPDU_TX_DONE_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CHANNEL_ACCESS_CTRL_ADDR 0x013C
|
|
#define CFG_HWQ_STRICT_PRI_OFFSET 1
|
|
#define CFG_HWQ_STRICT_PRI_MASK 0x00000002
|
|
#define CFG_TDMA_NEED_CCA_OFFSET 0
|
|
#define CFG_TDMA_NEED_CCA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q0_CUR_PTR_ADDR 0x0140
|
|
#define Q0_CUR_PTR_OFFSET 0
|
|
#define Q0_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q1_CUR_PTR_ADDR 0x0144
|
|
#define Q1_CUR_PTR_OFFSET 0
|
|
#define Q1_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q2_CUR_PTR_ADDR 0x0148
|
|
#define Q2_CUR_PTR_OFFSET 0
|
|
#define Q2_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q3_CUR_PTR_ADDR 0x014c
|
|
#define Q3_CUR_PTR_OFFSET 0
|
|
#define Q3_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q4_CUR_PTR_ADDR 0x0150
|
|
#define Q4_CUR_PTR_OFFSET 0
|
|
#define Q4_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q5_CUR_PTR_ADDR 0x0154
|
|
#define Q5_CUR_PTR_OFFSET 0
|
|
#define Q5_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q6_CUR_PTR_ADDR 0x0158
|
|
#define Q6_CUR_PTR_OFFSET 0
|
|
#define Q6_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q7_CUR_PTR_ADDR 0x015c
|
|
#define Q7_CUR_PTR_OFFSET 0
|
|
#define Q7_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q8_CUR_PTR_ADDR 0x0160
|
|
#define Q8_CUR_PTR_OFFSET 0
|
|
#define Q8_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q9_CUR_PTR_ADDR 0x0164
|
|
#define Q9_CUR_PTR_OFFSET 0
|
|
#define Q9_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q10_CUR_PTR_ADDR 0x0168
|
|
#define Q10_CUR_PTR_OFFSET 0
|
|
#define Q10_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q11_CUR_PTR_ADDR 0x016c
|
|
#define Q11_CUR_PTR_OFFSET 0
|
|
#define Q11_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q12_CUR_PTR_ADDR 0x0170
|
|
#define Q12_CUR_PTR_OFFSET 0
|
|
#define Q12_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q13_CUR_PTR_ADDR 0x0174
|
|
#define Q13_CUR_PTR_OFFSET 0
|
|
#define Q13_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q14_CUR_PTR_ADDR 0x0178
|
|
#define Q14_CUR_PTR_OFFSET 0
|
|
#define Q14_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q15_CUR_PTR_ADDR 0x017c
|
|
#define Q15_CUR_PTR_OFFSET 0
|
|
#define Q15_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q16_CUR_PTR_ADDR 0x0180
|
|
#define Q16_CUR_PTR_OFFSET 0
|
|
#define Q16_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q17_CUR_PTR_ADDR 0x0184
|
|
#define Q17_CUR_PTR_OFFSET 0
|
|
#define Q17_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q18_CUR_PTR_ADDR 0x0188
|
|
#define Q18_CUR_PTR_OFFSET 0
|
|
#define Q18_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q19_CUR_PTR_ADDR 0x018c
|
|
#define Q19_CUR_PTR_OFFSET 0
|
|
#define Q19_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q20_CUR_PTR_ADDR 0x0190
|
|
#define Q20_CUR_PTR_OFFSET 0
|
|
#define Q20_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q21_CUR_PTR_ADDR 0x0194
|
|
#define Q21_CUR_PTR_OFFSET 0
|
|
#define Q21_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q22_CUR_PTR_ADDR 0x0198
|
|
#define Q22_CUR_PTR_OFFSET 0
|
|
#define Q22_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_Q23_CUR_PTR_ADDR 0x019c
|
|
#define Q23_CUR_PTR_OFFSET 0
|
|
#define Q23_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_DCU0_CUR_PTR_ADDR 0x01a0
|
|
#define DCU0_CUR_PTR_OFFSET 0
|
|
#define DCU0_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_DCU1_CUR_PTR_ADDR 0x01a4
|
|
#define DCU1_CUR_PTR_OFFSET 0
|
|
#define DCU1_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_DCU2_CUR_PTR_ADDR 0x01a8
|
|
#define DCU2_CUR_PTR_OFFSET 0
|
|
#define DCU2_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_DCU3_CUR_PTR_ADDR 0x01ac
|
|
#define DCU3_CUR_PTR_OFFSET 0
|
|
#define DCU3_CUR_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
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|
#define CFG_RO_DCU4_CUR_PTR_ADDR 0x01b0
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#define DCU4_CUR_PTR_OFFSET 0
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#define DCU4_CUR_PTR_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define RGF_HWQ_READ_REG(addr) SOC_READ_REG(RGF_HWQ_BASEADDR + addr)
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#define RGF_HWQ_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_HWQ_BASEADDR + addr,value)
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