878 lines
30 KiB
C
878 lines
30 KiB
C
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//-----------------------------------
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#define CFG_MAC_RTL_VERSION_ADDR 0x0000
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#define RO_MAC_RTL_VERSION_OFFSET 0
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#define RO_MAC_RTL_VERSION_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_TRX_START_ADDR 0x0004
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#define CFG_MAC_TRX_START_TRIG_OFFSET 1
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#define CFG_MAC_TRX_START_TRIG_MASK 0x00000002
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#define CFG_MAC_TRX_START_NEED_TRIG_OFFSET 0
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#define CFG_MAC_TRX_START_NEED_TRIG_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_DUMMY2_ADDR 0x0008
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//-----------------------------------
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#define CFG_MAC_DUMMY3_ADDR 0x000C
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//-----------------------------------
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#define CFG_MAC_DUMMY4_ADDR 0x0010
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//-----------------------------------
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#define CFG_MAC_DUMMY5_ADDR 0x0014
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//-----------------------------------
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#define CFG_ICG_SW_FORCE_ADDR 0x0018
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#define CFG_ICG_FORCE_ON_OFFSET 0
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#define CFG_ICG_FORCE_ON_MASK 0x00000001
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//-----------------------------------
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#define CFG_RO_NTB_SW_SYNC_VAL_ADDR 0x001C
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#define NTB_SW_SYNC_VAL_OFFSET 0
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#define NTB_SW_SYNC_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RO_NTB_HW_SYNC_VAL_ADDR 0x0020
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#define NTB_HW_SYNC_VAL_OFFSET 0
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#define NTB_HW_SYNC_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_DBG_CTRL0_ADDR 0x0024
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#define CFG_MAC_DBG_USE_TRIG_LATCH_OFFSET 1
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#define CFG_MAC_DBG_USE_TRIG_LATCH_MASK 0x00000002
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#define CFG_MAC_DBG_SEL_OFFSET 0
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#define CFG_MAC_DBG_SEL_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_DBG_CTRL1_ADDR 0x0028
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#define CFG_MAC_DBG_DLY_AFTER_TRIG_OFFSET 18
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#define CFG_MAC_DBG_DLY_AFTER_TRIG_MASK 0xFFFC0000
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#define CFG_MAC_DBG_TRIG_SEL_OFFSET 13
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#define CFG_MAC_DBG_TRIG_SEL_MASK 0x0003E000
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#define RO_REG_TEST_OFFSET 12
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#define RO_REG_TEST_MASK 0x00001000
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#define CFG_MAC_DBG_BUS_SEL_OFFSET 0
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#define CFG_MAC_DBG_BUS_SEL_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_MAC_DBG_BUS_ADDR 0x002C
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#define MAC_DBG_BUS_OFFSET 0
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#define MAC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_TX_DBG_CTRL_ADDR 0x0030
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#define CFG_POSSIBLE_UNDERFLOW_CYCLE_CNT_OFFSET 16
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#define CFG_POSSIBLE_UNDERFLOW_CYCLE_CNT_MASK 0xFFFF0000
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#define CFG_PHY_TX_ABORT_DBG_CNT_CLR_OFFSET 4
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#define CFG_PHY_TX_ABORT_DBG_CNT_CLR_MASK 0x00000010
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#define CFG_TX_BYPASS_CCA_OFFSET 2
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#define CFG_TX_BYPASS_CCA_MASK 0x00000004
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#define CFG_TX_BYPASS_PHY_OFFSET 1
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#define CFG_TX_BYPASS_PHY_MASK 0x00000002
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#define CFG_TX_DBG_CNT_CLR_OFFSET 0
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#define CFG_TX_DBG_CNT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_TX_DBG_CNT_ADDR 0x0034
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#define DBG_TX_CNT_OFFSET 16
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#define DBG_TX_CNT_MASK 0xFFFF0000
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#define PHY_TX_ABORT_DBG_CNT_OFFSET 0
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#define PHY_TX_ABORT_DBG_CNT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_RD_LOCAL_TMR_ADDR 0x0038
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#define LOCAL_TMR_OFFSET 0
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#define LOCAL_TMR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MYNID_ADDR 0x003C
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#define CFG_MYNID_OFFSET 0
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#define CFG_MYNID_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_MYSTAT_ADDR 0x0040
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#define CFG_CCO_MODE_OFFSET 2
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#define CFG_CCO_MODE_MASK 0x00000004
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#define CFG_AUTHENTICATED_OFFSET 1
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#define CFG_AUTHENTICATED_MASK 0x00000002
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#define CFG_ASSOCIATED_OFFSET 0
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#define CFG_ASSOCIATED_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_SEC_ADDR 0x0044
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#define CFG_RX_DECRYPTION_EN_OFFSET 7
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#define CFG_RX_DECRYPTION_EN_MASK 0x00000080
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#define CFG_SEC_AES_MODE_OFFSET 6
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#define CFG_SEC_AES_MODE_MASK 0x00000040
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#define CFG_AES_ENDIAN_OFFSET 0
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#define CFG_AES_ENDIAN_MASK 0x0000003F
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//-----------------------------------
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#define CFG_BEACON_PERIOD_ADDR 0x0048
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#define CFG_BEACON_PERIOD_OFFSET 16
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#define CFG_BEACON_PERIOD_MASK 0xFFFF0000
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//-----------------------------------
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#define CFG_GP_CTRL_ADDR 0x004C
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#define CFG_GP_RTS_EN_OFFSET 1
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#define CFG_GP_RTS_EN_MASK 0x00000002
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#define CFG_GP_PB_SIZE_SEL_OFFSET 0
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#define CFG_GP_PB_SIZE_SEL_MASK 0x00000001
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//-----------------------------------
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#define CFG_TMI_CTRL_ADDR 0x0050
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#define CFG_ENABLE_MAC_LOAD_TMI_OFFSET 2
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#define CFG_ENABLE_MAC_LOAD_TMI_MASK 0x00000004
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#define CFG_TONE_AMP_EN_OFFSET 1
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#define CFG_TONE_AMP_EN_MASK 0x00000002
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#define CFG_TONE_MASK_EN_OFFSET 0
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#define CFG_TONE_MASK_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_TMSK_PTR_ADDR 0x0054
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#define CFG_TONE_MASK_PTR_OFFSET 0
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#define CFG_TONE_MASK_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_TAMP_PTR_ADDR 0x0058
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#define CFG_TONE_AMP_PTR_OFFSET 0
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#define CFG_TONE_AMP_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BAND_PTR_ADDR 0x005C
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#define CFG_BAND_TBL_PTR_OFFSET 0
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#define CFG_BAND_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PRS_CTRL_ADDR 0x0060
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#define CFG_PRS_SENSE_EN_OFFSET 1
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#define CFG_PRS_SENSE_EN_MASK 0x00000002
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#define CFG_PRS_TX_EN_OFFSET 0
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#define CFG_PRS_TX_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_TX_CTRL_ADDR 0x0064
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#define CFG_PB_EXPIRE_TIMER_OFFSET 27
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#define CFG_PB_EXPIRE_TIMER_MASK 0xF8000000
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#define CFG_TX_BEACON_PLD_CRC_BY_SW_OFFSET 26
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#define CFG_TX_BEACON_PLD_CRC_BY_SW_MASK 0x04000000
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#define CFG_NEED_TX_HP10_FC_OFFSET 25
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#define CFG_NEED_TX_HP10_FC_MASK 0x02000000
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#define CFG_TX_FCNUM_OFFSET 24
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#define CFG_TX_FCNUM_MASK 0x01000000
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#define CFG_SG_STA_LOADING_OFFSET 16
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#define CFG_SG_STA_LOADING_MASK 0x00FF0000
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#define CFG_SG_SACK_VER_OFFSET 12
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#define CFG_SG_SACK_VER_MASK 0x0000F000
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#define CFG_SG_FC_VER_OFFSET 8
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#define CFG_SG_FC_VER_MASK 0x00000F00
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#define CFG_RXWSZ_OFFSET 4
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#define CFG_RXWSZ_MASK 0x000000F0
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#define CFG_GP_BDF_OFFSET 3
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#define CFG_GP_BDF_MASK 0x00000008
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#define CFG_GP_SACK_VER_OFFSET 2
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#define CFG_GP_SACK_VER_MASK 0x00000004
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#define CFG_GP_HP10DF_OFFSET 1
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#define CFG_GP_HP10DF_MASK 0x00000002
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#define CFG_GP_HP11DF_OFFSET 0
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#define CFG_GP_HP11DF_MASK 0x00000001
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//-----------------------------------
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#define CFG_MYTEI_ADDR 0x0068
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#define CFG_MYTEI_OFFSET 0
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#define CFG_MYTEI_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_TX_BTS_DLY_ADDR 0x006C
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#define CFG_TX_BTS_DELAY_SIGN_OFFSET 28
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#define CFG_TX_BTS_DELAY_SIGN_MASK 0x10000000
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#define CFG_TX_BTS_DELAY_OFFSET 0
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#define CFG_TX_BTS_DELAY_MASK 0x0FFFFFFF
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//-----------------------------------
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#define CFG_NTB_SYNC_0_ADDR 0x0070
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#define CFG_NTB_SW_SYNC_CLR_OFFSET 20
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#define CFG_NTB_SW_SYNC_CLR_MASK 0x00100000
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#define CFG_NTB_HW_SYNC_CLR_OFFSET 19
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#define CFG_NTB_HW_SYNC_CLR_MASK 0x00080000
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#define CFG_HW_NTB_SYNC_EN_OFFSET 18
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#define CFG_HW_NTB_SYNC_EN_MASK 0x00040000
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#define CFG_MODIFY_NTB_EN_OFFSET 17
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#define CFG_MODIFY_NTB_EN_MASK 0x00020000
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#define CFG_NTB_GOLDEN_GAP_OFFSET 1
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#define CFG_NTB_GOLDEN_GAP_MASK 0x0001FFFE
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#define CFG_NTB_DELTA_VAL_SIGN_OFFSET 0
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#define CFG_NTB_DELTA_VAL_SIGN_MASK 0x00000001
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//-----------------------------------
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#define CFG_NTB_SYNC_1_ADDR 0x0074
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#define CFG_NTB_DELTA_VAL_OFFSET 0
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#define CFG_NTB_DELTA_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RD_NTB_ADDR 0x0078
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#define NTB_TMR_OFFSET 0
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#define NTB_TMR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN0_AES_TBL_ADDR 0x0080
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#define CFG_VLAN0_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN0_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN1_AES_TBL_ADDR 0x0084
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#define CFG_VLAN1_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN1_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN2_AES_TBL_ADDR 0x0088
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#define CFG_VLAN2_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN2_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN3_AES_TBL_ADDR 0x008C
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#define CFG_VLAN3_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN3_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN4_AES_TBL_ADDR 0x0090
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#define CFG_VLAN4_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN4_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN5_AES_TBL_ADDR 0x0094
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#define CFG_VLAN5_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN5_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN6_AES_TBL_ADDR 0x0098
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#define CFG_VLAN6_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN6_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_VLAN7_AES_TBL_ADDR 0x009C
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#define CFG_VLAN7_AES_TBL_PTR_OFFSET 0
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#define CFG_VLAN7_AES_TBL_PTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PHASE_BAND_SEL_ADDR 0x00A0
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#define CFG_SW_IDLE_MODE_EN_OFFSET 10
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#define CFG_SW_IDLE_MODE_EN_MASK 0x00000400
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#define CFG_SW_IDLE_MODE_OFFSET 9
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#define CFG_SW_IDLE_MODE_MASK 0x00000200
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#define CFG_SW_RX_RATE_MODE_EN_OFFSET 8
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#define CFG_SW_RX_RATE_MODE_EN_MASK 0x00000100
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#define CFG_SW_RX_RATE_MODE_OFFSET 5
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#define CFG_SW_RX_RATE_MODE_MASK 0x000000E0
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#define CFG_SW_NARROWBAND_EN_OFFSET 4
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#define CFG_SW_NARROWBAND_EN_MASK 0x00000010
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#define CFG_SW_NARROWBAND_OFFSET 3
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#define CFG_SW_NARROWBAND_MASK 0x00000008
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#define CFG_SW_PHASE_EN_OFFSET 2
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#define CFG_SW_PHASE_EN_MASK 0x00000004
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#define CFG_SW_PHASE_OFFSET 0
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#define CFG_SW_PHASE_MASK 0x00000003
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//-----------------------------------
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#define CFG_BEACON_ADDR 0x00A4
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#define CFG_BCN_ALERT_AHEAD_OFFSET 0
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#define CFG_BCN_ALERT_AHEAD_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BCN_START_NTB_ADDR 0x00A8
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#define CFG_BEACON_START_NTB_OFFSET 0
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#define CFG_BEACON_START_NTB_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_DUMMY17_ADDR 0x00AC
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#define CFG_DUMMY0_OFFSET 0
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#define CFG_DUMMY0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BCN_MISS_MAX_NUM_ADDR 0x00B0
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#define CFG_BCN_MISS_MAX_NUM_OFFSET 0
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#define CFG_BCN_MISS_MAX_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_INT_ENA_MASK_ADDR 0x00B4
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#define CFG_INT_ENABLE_MASK_OFFSET 0
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#define CFG_INT_ENABLE_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI0_MASK_ADDR 0x00B8
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#define CFG_INT_PRI0_MASK_OFFSET 0
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#define CFG_INT_PRI0_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI1_MASK_ADDR 0x00BC
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#define CFG_INT_PRI1_MASK_OFFSET 0
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#define CFG_INT_PRI1_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI2_MASK_ADDR 0x00C0
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#define CFG_INT_PRI2_MASK_OFFSET 0
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#define CFG_INT_PRI2_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI3_MASK_ADDR 0x00C4
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#define CFG_INT_PRI3_MASK_OFFSET 0
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#define CFG_INT_PRI3_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_INT_STS_ADDR 0x00C8
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#define MAC_INT_STATUS_OFFSET 0
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#define MAC_INT_STATUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_MAC_INT_CLR_ADDR 0x00CC
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#define MAC_INT_CLR_31_OFFSET 31
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#define MAC_INT_CLR_31_MASK 0x80000000
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#define MAC_INT_CLR_30_OFFSET 30
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#define MAC_INT_CLR_30_MASK 0x40000000
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#define MAC_INT_CLR_29_OFFSET 29
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#define MAC_INT_CLR_29_MASK 0x20000000
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#define MAC_INT_CLR_28_OFFSET 28
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#define MAC_INT_CLR_28_MASK 0x10000000
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#define MAC_INT_CLR_27_OFFSET 27
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#define MAC_INT_CLR_27_MASK 0x08000000
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#define MAC_INT_CLR_26_OFFSET 26
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#define MAC_INT_CLR_26_MASK 0x04000000
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#define MAC_INT_CLR_25_OFFSET 25
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#define MAC_INT_CLR_25_MASK 0x02000000
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#define MAC_INT_CLR_24_OFFSET 24
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#define MAC_INT_CLR_24_MASK 0x01000000
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#define MAC_INT_CLR_23_OFFSET 23
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#define MAC_INT_CLR_23_MASK 0x00800000
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#define MAC_INT_CLR_22_OFFSET 22
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#define MAC_INT_CLR_22_MASK 0x00400000
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#define MAC_INT_CLR_21_OFFSET 21
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#define MAC_INT_CLR_21_MASK 0x00200000
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#define MAC_INT_CLR_20_OFFSET 20
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#define MAC_INT_CLR_20_MASK 0x00100000
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#define MAC_INT_CLR_19_OFFSET 19
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#define MAC_INT_CLR_19_MASK 0x00080000
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#define MAC_INT_CLR_18_OFFSET 18
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#define MAC_INT_CLR_18_MASK 0x00040000
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#define MAC_INT_CLR_17_OFFSET 17
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#define MAC_INT_CLR_17_MASK 0x00020000
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#define MAC_INT_CLR_16_OFFSET 16
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#define MAC_INT_CLR_16_MASK 0x00010000
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#define MAC_INT_CLR_15_OFFSET 15
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#define MAC_INT_CLR_15_MASK 0x00008000
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#define MAC_INT_CLR_14_OFFSET 14
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#define MAC_INT_CLR_14_MASK 0x00004000
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#define MAC_INT_CLR_13_OFFSET 13
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#define MAC_INT_CLR_13_MASK 0x00002000
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#define MAC_INT_CLR_12_OFFSET 12
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#define MAC_INT_CLR_12_MASK 0x00001000
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#define MAC_INT_CLR_11_OFFSET 11
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#define MAC_INT_CLR_11_MASK 0x00000800
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#define MAC_INT_CLR_10_OFFSET 10
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#define MAC_INT_CLR_10_MASK 0x00000400
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#define MAC_INT_CLR_9_OFFSET 9
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#define MAC_INT_CLR_9_MASK 0x00000200
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#define MAC_INT_CLR_8_OFFSET 8
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#define MAC_INT_CLR_8_MASK 0x00000100
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#define MAC_INT_CLR_7_OFFSET 7
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#define MAC_INT_CLR_7_MASK 0x00000080
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#define MAC_INT_CLR_6_OFFSET 6
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#define MAC_INT_CLR_6_MASK 0x00000040
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#define MAC_INT_CLR_5_OFFSET 5
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#define MAC_INT_CLR_5_MASK 0x00000020
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#define MAC_INT_CLR_4_OFFSET 4
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#define MAC_INT_CLR_4_MASK 0x00000010
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#define MAC_INT_CLR_3_OFFSET 3
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#define MAC_INT_CLR_3_MASK 0x00000008
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#define MAC_INT_CLR_2_OFFSET 2
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#define MAC_INT_CLR_2_MASK 0x00000004
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#define MAC_INT_CLR_1_OFFSET 1
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#define MAC_INT_CLR_1_MASK 0x00000002
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#define MAC_INT_CLR_0_OFFSET 0
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#define MAC_INT_CLR_0_MASK 0x00000001
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//-----------------------------------
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#define CFG_ZC_CAP_ADDR 0x00D0
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#define CFG_ZC_CAP_ENABLE_OFFSET 22
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#define CFG_ZC_CAP_ENABLE_MASK 0x00400000
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#define CFG_ZC_CAP_HALF_PERIOD_OFFSET 21
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#define CFG_ZC_CAP_HALF_PERIOD_MASK 0x00200000
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#define CFG_ZC_CAP_INTERVAL_OFFSET 5
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#define CFG_ZC_CAP_INTERVAL_MASK 0x001FFFE0
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#define CFG_ZC_INT_NUM_OFFSET 2
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#define CFG_ZC_INT_NUM_MASK 0x0000001C
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#define CFG_ZC_TRIG_OFFSET 1
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#define CFG_ZC_TRIG_MASK 0x00000002
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#define CFG_ZC_FALL_OFFSET 0
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#define CFG_ZC_FALL_MASK 0x00000001
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//-----------------------------------
|
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#define CFG_ZC_TS0_ADDR 0x00d4
|
|
#define ZC_TS0_OFFSET 0
|
|
#define ZC_TS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS1_ADDR 0x00d8
|
|
#define ZC_TS1_OFFSET 0
|
|
#define ZC_TS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS2_ADDR 0x00dc
|
|
#define ZC_TS2_OFFSET 0
|
|
#define ZC_TS2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS3_ADDR 0x00e0
|
|
#define ZC_TS3_OFFSET 0
|
|
#define ZC_TS3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS4_ADDR 0x00e4
|
|
#define ZC_TS4_OFFSET 0
|
|
#define ZC_TS4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS5_ADDR 0x00e8
|
|
#define ZC_TS5_OFFSET 0
|
|
#define ZC_TS5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS6_ADDR 0x00ec
|
|
#define ZC_TS6_OFFSET 0
|
|
#define ZC_TS6_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_TS7_ADDR 0x00f0
|
|
#define ZC_TS7_OFFSET 0
|
|
#define ZC_TS7_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SELFGEN_ADDR 0x00f4
|
|
#define CFG_RESP_POWER_OFFSET 8
|
|
#define CFG_RESP_POWER_MASK 0x0000FF00
|
|
#define CFG_RESP_PPDU_TYPE_OFFSET 5
|
|
#define CFG_RESP_PPDU_TYPE_MASK 0x000000E0
|
|
#define CFG_RESP_TAMP_OFFSET 0
|
|
#define CFG_RESP_TAMP_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_GAIN_CTRL_ADDR 0x00f8
|
|
#define CFG_GAIN_LOAD_EN_OFFSET 0
|
|
#define CFG_GAIN_LOAD_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GAIN_PTR_ADDR 0x00fc
|
|
#define CFG_GAIN_PTR_OFFSET 0
|
|
#define CFG_GAIN_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_TX_TIMEOUT_ADDR 0x0100
|
|
#define CFG_PHY_TX_TIMEOUT_EN_OFFSET 25
|
|
#define CFG_PHY_TX_TIMEOUT_EN_MASK 0x02000000
|
|
#define CFG_PHY_TX_TIMEOUT_OFFSET 0
|
|
#define CFG_PHY_TX_TIMEOUT_MASK 0x01FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_INT_CTRL_ADDR 0x0104
|
|
#define RO_RX_DESC_OVERFLOW_INT_STATUS_OFFSET 25
|
|
#define RO_RX_DESC_OVERFLOW_INT_STATUS_MASK 0x3E000000
|
|
#define RO_RX_LOW_WATERMARK_INT_STATUS_OFFSET 20
|
|
#define RO_RX_LOW_WATERMARK_INT_STATUS_MASK 0x01F00000
|
|
#define RO_RX_PLD_OVERFLOW_INT_STATUS_OFFSET 15
|
|
#define RO_RX_PLD_OVERFLOW_INT_STATUS_MASK 0x000F8000
|
|
#define RO_RX_MPDU_INT_STATUS_OFFSET 10
|
|
#define RO_RX_MPDU_INT_STATUS_MASK 0x00007C00
|
|
#define RO_RX_PB_INT_STATUS_OFFSET 5
|
|
#define RO_RX_PB_INT_STATUS_MASK 0x000003E0
|
|
#define RO_RX_FC_INT_STATUS_OFFSET 0
|
|
#define RO_RX_FC_INT_STATUS_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_RX_INT_CLR_ADDR 0x0108
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_4_OFFSET 29
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_4_MASK 0x20000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_3_OFFSET 28
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_3_MASK 0x10000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_2_OFFSET 27
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_2_MASK 0x08000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_1_OFFSET 26
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_1_MASK 0x04000000
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_0_OFFSET 25
|
|
#define CFG_RX_DESC_OVERFLOW_INT_CLR_0_MASK 0x02000000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_4_OFFSET 24
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_4_MASK 0x01000000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_3_OFFSET 23
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_3_MASK 0x00800000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_2_OFFSET 22
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_2_MASK 0x00400000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_1_OFFSET 21
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_1_MASK 0x00200000
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_0_OFFSET 20
|
|
#define CFG_RX_LOW_WATERMARK_INT_CLR_0_MASK 0x00100000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_4_OFFSET 19
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_4_MASK 0x00080000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_3_OFFSET 18
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_3_MASK 0x00040000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_2_OFFSET 17
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_2_MASK 0x00020000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_1_OFFSET 16
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_1_MASK 0x00010000
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_0_OFFSET 15
|
|
#define CFG_RX_PLD_OVERFLOW_INT_CLR_0_MASK 0x00008000
|
|
#define CFG_RX_MPDU_INT_CLR_4_OFFSET 14
|
|
#define CFG_RX_MPDU_INT_CLR_4_MASK 0x00004000
|
|
#define CFG_RX_MPDU_INT_CLR_3_OFFSET 13
|
|
#define CFG_RX_MPDU_INT_CLR_3_MASK 0x00002000
|
|
#define CFG_RX_MPDU_INT_CLR_2_OFFSET 12
|
|
#define CFG_RX_MPDU_INT_CLR_2_MASK 0x00001000
|
|
#define CFG_RX_MPDU_INT_CLR_1_OFFSET 11
|
|
#define CFG_RX_MPDU_INT_CLR_1_MASK 0x00000800
|
|
#define CFG_RX_MPDU_INT_CLR_0_OFFSET 10
|
|
#define CFG_RX_MPDU_INT_CLR_0_MASK 0x00000400
|
|
#define CFG_RX_PB_INT_CLR_4_OFFSET 9
|
|
#define CFG_RX_PB_INT_CLR_4_MASK 0x00000200
|
|
#define CFG_RX_PB_INT_CLR_3_OFFSET 8
|
|
#define CFG_RX_PB_INT_CLR_3_MASK 0x00000100
|
|
#define CFG_RX_PB_INT_CLR_2_OFFSET 7
|
|
#define CFG_RX_PB_INT_CLR_2_MASK 0x00000080
|
|
#define CFG_RX_PB_INT_CLR_1_OFFSET 6
|
|
#define CFG_RX_PB_INT_CLR_1_MASK 0x00000040
|
|
#define CFG_RX_PB_INT_CLR_0_OFFSET 5
|
|
#define CFG_RX_PB_INT_CLR_0_MASK 0x00000020
|
|
#define CFG_RX_FC_INT_CLR_4_OFFSET 4
|
|
#define CFG_RX_FC_INT_CLR_4_MASK 0x00000010
|
|
#define CFG_RX_FC_INT_CLR_3_OFFSET 3
|
|
#define CFG_RX_FC_INT_CLR_3_MASK 0x00000008
|
|
#define CFG_RX_FC_INT_CLR_2_OFFSET 2
|
|
#define CFG_RX_FC_INT_CLR_2_MASK 0x00000004
|
|
#define CFG_RX_FC_INT_CLR_1_OFFSET 1
|
|
#define CFG_RX_FC_INT_CLR_1_MASK 0x00000002
|
|
#define CFG_RX_FC_INT_CLR_0_OFFSET 0
|
|
#define CFG_RX_FC_INT_CLR_0_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_CTRL_ADDR 0x010c
|
|
#define CFG_ZC_GEN_TRIG_OFFSET 21
|
|
#define CFG_ZC_GEN_TRIG_MASK 0x00200000
|
|
#define CFG_ZC_DUR_OFFSET 1
|
|
#define CFG_ZC_DUR_MASK 0x001FFFFE
|
|
#define CFG_ZC_GEN_SEL_OFFSET 0
|
|
#define CFG_ZC_GEN_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_PERIOD_ADDR 0x0110
|
|
#define CFG_ZC_PERIOD_OFFSET 0
|
|
#define CFG_ZC_PERIOD_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_TS_ADDR 0x0114
|
|
#define CFG_ZC_TIMESTAMP_OFFSET 0
|
|
#define CFG_ZC_TIMESTAMP_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_LCT_TRACK_CTRL_ADDR 0x0118
|
|
#define CFG_ZC_VIBRATE_PROTECT_OFFSET 10
|
|
#define CFG_ZC_VIBRATE_PROTECT_MASK 0x1FFFFC00
|
|
#define CFG_HW_AC_TRACK_EN_OFFSET 9
|
|
#define CFG_HW_AC_TRACK_EN_MASK 0x00000200
|
|
#define CFG_HW_AC_TRACK_TRIG_OFFSET 8
|
|
#define CFG_HW_AC_TRACK_TRIG_MASK 0x00000100
|
|
#define CFG_PERIOD_WEIGHT_OFFSET 4
|
|
#define CFG_PERIOD_WEIGHT_MASK 0x000000F0
|
|
#define CFG_LCTE_WEIGHT_OFFSET 0
|
|
#define CFG_LCTE_WEIGHT_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_TIMEOUT_0_ADDR 0x011C
|
|
#define CFG_TX_BUF_TIMEOUT_EN_OFFSET 27
|
|
#define CFG_TX_BUF_TIMEOUT_EN_MASK 0x08000000
|
|
#define CFG_TX_BUF_TIMEOUT_OFFSET 11
|
|
#define CFG_TX_BUF_TIMEOUT_MASK 0x07FFF800
|
|
#define CFG_TX_AES_KEY_TIMEOUT_EN_OFFSET 10
|
|
#define CFG_TX_AES_KEY_TIMEOUT_EN_MASK 0x00000400
|
|
#define CFG_TX_AES_KEY_TIMEOUT_OFFSET 0
|
|
#define CFG_TX_AES_KEY_TIMEOUT_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_TX_TIMEOUT_1_ADDR 0x0120
|
|
#define CFG_TX_PB_DESC_TIMEOUT_OFFSET 1
|
|
#define CFG_TX_PB_DESC_TIMEOUT_MASK 0x0001FFFE
|
|
#define CFG_TX_PB_DESC_TIMEOUT_EN_OFFSET 0
|
|
#define CFG_TX_PB_DESC_TIMEOUT_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_RO_ZC_LCT_DELTA_ADDR 0x0124
|
|
#define DELTA_LCT_VS_LCTE_OFFSET 0
|
|
#define DELTA_LCT_VS_LCTE_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_ZC_GEN_OFFSET_ADDR 0x0128
|
|
#define CFG_ZC_GEN_OFFSET_LEFT_OFFSET 19
|
|
#define CFG_ZC_GEN_OFFSET_LEFT_MASK 0x00080000
|
|
#define CFG_ZC_GEN_OFFSET_OFFSET 0
|
|
#define CFG_ZC_GEN_OFFSET_MASK 0x0007FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_0_LOW_ADDR 0x012c
|
|
#define CFG_PTR0_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR0_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_0_UP_ADDR 0x0130
|
|
#define CFG_PTR0_UP_BOND_OFFSET 0
|
|
#define CFG_PTR0_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_1_LOW_ADDR 0x0134
|
|
#define CFG_PTR1_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR1_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_1_UP_ADDR 0x0138
|
|
#define CFG_PTR1_UP_BOND_OFFSET 0
|
|
#define CFG_PTR1_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_2_LOW_ADDR 0x013c
|
|
#define CFG_PTR2_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR2_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_2_UP_ADDR 0x0140
|
|
#define CFG_PTR2_UP_BOND_OFFSET 0
|
|
#define CFG_PTR2_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_3_LOW_ADDR 0x0144
|
|
#define CFG_PTR3_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR3_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_3_UP_ADDR 0x0148
|
|
#define CFG_PTR3_UP_BOND_OFFSET 0
|
|
#define CFG_PTR3_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_4_LOW_ADDR 0x014c
|
|
#define CFG_PTR4_LOW_BOND_OFFSET 0
|
|
#define CFG_PTR4_LOW_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_4_UP_ADDR 0x0150
|
|
#define CFG_PTR4_UP_BOND_OFFSET 0
|
|
#define CFG_PTR4_UP_BOND_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BUS_MONI_CTRL_ADDR 0x0154
|
|
#define CFG_BUS_ERR_HREADY_FORCE_1_OFFSET 17
|
|
#define CFG_BUS_ERR_HREADY_FORCE_1_MASK 0x00020000
|
|
#define CFG_BUS_ERR_CG_CLR_OFFSET 16
|
|
#define CFG_BUS_ERR_CG_CLR_MASK 0x00010000
|
|
#define CFG_BUS_ERR_CG_EN_OFFSET 15
|
|
#define CFG_BUS_ERR_CG_EN_MASK 0x00008000
|
|
#define CFG_PTR_RANG4_BLACK_OFFSET 14
|
|
#define CFG_PTR_RANG4_BLACK_MASK 0x00004000
|
|
#define CFG_PTR_RANG3_BLACK_OFFSET 13
|
|
#define CFG_PTR_RANG3_BLACK_MASK 0x00002000
|
|
#define CFG_PTR_RANG2_BLACK_OFFSET 12
|
|
#define CFG_PTR_RANG2_BLACK_MASK 0x00001000
|
|
#define CFG_PTR_RANG1_BLACK_OFFSET 11
|
|
#define CFG_PTR_RANG1_BLACK_MASK 0x00000800
|
|
#define CFG_PTR_RANG0_BLACK_OFFSET 10
|
|
#define CFG_PTR_RANG0_BLACK_MASK 0x00000400
|
|
#define CFG_PTR4_CTRL_OFFSET 8
|
|
#define CFG_PTR4_CTRL_MASK 0x00000300
|
|
#define CFG_PTR3_CTRL_OFFSET 6
|
|
#define CFG_PTR3_CTRL_MASK 0x000000C0
|
|
#define CFG_PTR2_CTRL_OFFSET 4
|
|
#define CFG_PTR2_CTRL_MASK 0x00000030
|
|
#define CFG_PTR1_CTRL_OFFSET 2
|
|
#define CFG_PTR1_CTRL_MASK 0x0000000C
|
|
#define CFG_PTR0_CTRL_OFFSET 0
|
|
#define CFG_PTR0_CTRL_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_AHB_DBG_CTRL_ADDR 0x0158
|
|
#define CFG_AHB_TRANS_DONE_SEL_OFFSET 0
|
|
#define CFG_AHB_TRANS_DONE_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_0_ADDR 0x015c
|
|
#define CFG_PHY_RX_ABORT_OFFSET 31
|
|
#define CFG_PHY_RX_ABORT_MASK 0x80000000
|
|
#define CFG_PHY_RX_ABORT_FORCE_EN_OFFSET 30
|
|
#define CFG_PHY_RX_ABORT_FORCE_EN_MASK 0x40000000
|
|
#define CFG_PHY_RX_VERSION_OFFSET 27
|
|
#define CFG_PHY_RX_VERSION_MASK 0x38000000
|
|
#define CFG_PHY_RX_VERSION_FORCE_EN_OFFSET 26
|
|
#define CFG_PHY_RX_VERSION_FORCE_EN_MASK 0x04000000
|
|
#define CFG_PHY_RX_PORT_OFFSET 24
|
|
#define CFG_PHY_RX_PORT_MASK 0x03000000
|
|
#define CFG_PHY_RX_PORT_FORCE_EN_OFFSET 23
|
|
#define CFG_PHY_RX_PORT_FORCE_EN_MASK 0x00800000
|
|
#define CFG_PHY_PB_CRC_DONE_OFFSET 22
|
|
#define CFG_PHY_PB_CRC_DONE_MASK 0x00400000
|
|
#define CFG_PHY_PB_CRC_DONE_FORCE_EN_OFFSET 21
|
|
#define CFG_PHY_PB_CRC_DONE_FORCE_EN_MASK 0x00200000
|
|
#define CFG_PHY_FC_CRC_DONE_OFFSET 20
|
|
#define CFG_PHY_FC_CRC_DONE_MASK 0x00100000
|
|
#define CFG_PHY_FC_CRC_DONE_FORCE_EN_OFFSET 19
|
|
#define CFG_PHY_FC_CRC_DONE_FORCE_EN_MASK 0x00080000
|
|
#define CFG_PHY_RX_PRS_OFFSET 18
|
|
#define CFG_PHY_RX_PRS_MASK 0x00040000
|
|
#define CFG_PHY_RX_PRS_FORCE_EN_OFFSET 17
|
|
#define CFG_PHY_RX_PRS_FORCE_EN_MASK 0x00020000
|
|
#define CFG_PHY_PCS_BUSY_OFFSET 16
|
|
#define CFG_PHY_PCS_BUSY_MASK 0x00010000
|
|
#define CFG_PHY_PCS_BUSY_FORCE_EN_OFFSET 15
|
|
#define CFG_PHY_PCS_BUSY_FORCE_EN_MASK 0x00008000
|
|
#define CFG_PHY_RX_VLD_OFFSET 14
|
|
#define CFG_PHY_RX_VLD_MASK 0x00004000
|
|
#define CFG_PHY_RX_VLD_FORCE_EN_OFFSET 13
|
|
#define CFG_PHY_RX_VLD_FORCE_EN_MASK 0x00002000
|
|
#define CFG_PHY_RX_FRAME_OFFSET 12
|
|
#define CFG_PHY_RX_FRAME_MASK 0x00001000
|
|
#define CFG_PHY_RX_FRAME_FORCE_EN_OFFSET 11
|
|
#define CFG_PHY_RX_FRAME_FORCE_EN_MASK 0x00000800
|
|
#define CFG_PHY_RX_RATE_MODE_OFFSET 8
|
|
#define CFG_PHY_RX_RATE_MODE_MASK 0x00000700
|
|
#define CFG_PHY_RX_RATE_MODE_FORCE_EN_OFFSET 7
|
|
#define CFG_PHY_RX_RATE_MODE_FORCE_EN_MASK 0x00000080
|
|
#define CFG_PHY_RX_READY_OFFSET 6
|
|
#define CFG_PHY_RX_READY_MASK 0x00000040
|
|
#define CFG_PHY_RX_READY_FORCE_EN_OFFSET 5
|
|
#define CFG_PHY_RX_READY_FORCE_EN_MASK 0x00000020
|
|
#define CFG_PHY_RX_ENABLE_OFFSET 4
|
|
#define CFG_PHY_RX_ENABLE_MASK 0x00000010
|
|
#define CFG_PHY_RX_ENABLE_FORCE_EN_OFFSET 3
|
|
#define CFG_PHY_RX_ENABLE_FORCE_EN_MASK 0x00000008
|
|
#define CFG_PHY_RX_PHASE_SEL_OFFSET 1
|
|
#define CFG_PHY_RX_PHASE_SEL_MASK 0x00000006
|
|
#define CFG_PHY_RX_PHASE_SEL_FORCE_EN_OFFSET 0
|
|
#define CFG_PHY_RX_PHASE_SEL_FORCE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PHY_FORCE_1_ADDR 0x0160
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_OFFSET 28
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_MASK 0x70000000
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_FORCE_EN_OFFSET 27
|
|
#define CFG_PHY_TX_PLD_MODU_MODE_FORCE_EN_MASK 0x08000000
|
|
#define CFG_PHY_TX_RATE_MODE_OFFSET 25
|
|
#define CFG_PHY_TX_RATE_MODE_MASK 0x06000000
|
|
#define CFG_PHY_TX_RATE_MODE_FORCE_EN_OFFSET 24
|
|
#define CFG_PHY_TX_RATE_MODE_FORCE_EN_MASK 0x01000000
|
|
#define CFG_PHY_TX_ENABLE_OFFSET 23
|
|
#define CFG_PHY_TX_ENABLE_MASK 0x00800000
|
|
#define CFG_PHY_TX_ENABLE_FORCE_EN_OFFSET 22
|
|
#define CFG_PHY_TX_ENABLE_FORCE_EN_MASK 0x00400000
|
|
#define CFG_PHY_TX_ABORT_OFFSET 21
|
|
#define CFG_PHY_TX_ABORT_MASK 0x00200000
|
|
#define CFG_PHY_TX_ABORT_FORCE_EN_OFFSET 20
|
|
#define CFG_PHY_TX_ABORT_FORCE_EN_MASK 0x00100000
|
|
#define CFG_PHY_TX_START_OFFSET 19
|
|
#define CFG_PHY_TX_START_MASK 0x00080000
|
|
#define CFG_PHY_TX_START_FORCE_EN_OFFSET 18
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#define CFG_PHY_TX_START_FORCE_EN_MASK 0x00040000
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#define CFG_PHY_TX_BANDSEL_OFFSET 16
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#define CFG_PHY_TX_BANDSEL_MASK 0x00030000
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#define CFG_PHY_TX_BANDSEL_FORCE_EN_OFFSET 15
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#define CFG_PHY_TX_BANDSEL_FORCE_EN_MASK 0x00008000
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#define CFG_PHY_TX_VERSION_OFFSET 12
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#define CFG_PHY_TX_VERSION_MASK 0x00007000
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#define CFG_PHY_TX_VERSION_FORCE_EN_OFFSET 11
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#define CFG_PHY_TX_VERSION_FORCE_EN_MASK 0x00000800
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#define CFG_PHY_TX_PRS_OFFSET 10
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#define CFG_PHY_TX_PRS_MASK 0x00000400
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#define CFG_PHY_TX_PRS_FORCE_EN_OFFSET 9
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#define CFG_PHY_TX_PRS_FORCE_EN_MASK 0x00000200
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#define CFG_PHY_TX_VLD_OFFSET 8
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#define CFG_PHY_TX_VLD_MASK 0x00000100
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#define CFG_PHY_TX_VLD_FORCE_EN_OFFSET 7
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#define CFG_PHY_TX_VLD_FORCE_EN_MASK 0x00000080
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#define CFG_PHY_PB_RCV_DONE_OFFSET 6
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#define CFG_PHY_PB_RCV_DONE_MASK 0x00000040
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#define CFG_PHY_PB_RCV_DONE_FORCE_EN_OFFSET 5
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#define CFG_PHY_PB_RCV_DONE_FORCE_EN_MASK 0x00000020
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#define CFG_PHY_FC_RCV_DONE_OFFSET 4
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#define CFG_PHY_FC_RCV_DONE_MASK 0x00000010
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#define CFG_PHY_FC_RCV_DONE_FORCE_EN_OFFSET 3
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#define CFG_PHY_FC_RCV_DONE_FORCE_EN_MASK 0x00000008
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#define CFG_PHY_RX_BANDSEL_OFFSET 1
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#define CFG_PHY_RX_BANDSEL_MASK 0x00000006
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#define CFG_PHY_RX_BANDSEL_FORCE_EN_OFFSET 0
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#define CFG_PHY_RX_BANDSEL_FORCE_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_PHY_FORCE_2_ADDR 0x0164
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#define CFG_PHY_TX_UNDERFLOW_OFFSET 6
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#define CFG_PHY_TX_UNDERFLOW_MASK 0x00000040
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#define CFG_PHY_TX_UNDERFLOW_FORCE_EN_OFFSET 5
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#define CFG_PHY_TX_UNDERFLOW_FORCE_EN_MASK 0x00000020
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#define CFG_NARROW_BANDSEL_OFFSET 4
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#define CFG_NARROW_BANDSEL_MASK 0x00000010
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#define CFG_NARROW_BANDSEL_FORCE_EN_OFFSET 3
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#define CFG_NARROW_BANDSEL_FORCE_EN_MASK 0x00000008
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#define CFG_PHY_TX_PHASE_SEL_OFFSET 1
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#define CFG_PHY_TX_PHASE_SEL_MASK 0x00000006
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#define CFG_PHY_TX_PHASE_SEL_FORCE_EN_OFFSET 0
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#define CFG_PHY_TX_PHASE_SEL_FORCE_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_RD_MACPHY_INTF_0_ADDR 0x0168
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#define PHY_RX_BANDSEL_OFFSET 30
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#define PHY_RX_BANDSEL_MASK 0xC0000000
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#define PHY_RX_PORT_OFFSET 28
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#define PHY_RX_PORT_MASK 0x30000000
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#define PHY_RX_PRS_OFFSET 27
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#define PHY_RX_PRS_MASK 0x08000000
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#define PHY_RX_VLD_OFFSET 26
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#define PHY_RX_VLD_MASK 0x04000000
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#define PHY_RX_FRAME_OFFSET 25
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#define PHY_RX_FRAME_MASK 0x02000000
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#define PHY_RX_PHASE_SEL_OFFSET 23
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#define PHY_RX_PHASE_SEL_MASK 0x01800000
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#define PHY_RX_RATE_MODE_OFFSET 20
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#define PHY_RX_RATE_MODE_MASK 0x00700000
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#define PHY_RX_ENABLE_OFFSET 19
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#define PHY_RX_ENABLE_MASK 0x00080000
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#define PHY_RX_READY_OFFSET 18
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#define PHY_RX_READY_MASK 0x00040000
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#define TX_SW_FC_VLD_OFFSET 17
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#define TX_SW_FC_VLD_MASK 0x00020000
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#define PHY_TX_READY_OFFSET 16
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#define PHY_TX_READY_MASK 0x00010000
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#define PHY_TX_PROCESSING_OFFSET 15
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#define PHY_TX_PROCESSING_MASK 0x00008000
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#define PHY_TX_PHASE_SEL_OFFSET 13
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#define PHY_TX_PHASE_SEL_MASK 0x00006000
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#define PHY_TX_PLD_MODU_MODE_OFFSET 10
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#define PHY_TX_PLD_MODU_MODE_MASK 0x00001C00
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#define PHY_TX_RATE_MODE_OFFSET 8
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#define PHY_TX_RATE_MODE_MASK 0x00000300
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#define PHY_TX_ENABLE_OFFSET 7
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#define PHY_TX_ENABLE_MASK 0x00000080
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#define PHY_TX_BANDSEL_OFFSET 5
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#define PHY_TX_BANDSEL_MASK 0x00000060
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#define PHY_TX_VERSION_OFFSET 2
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#define PHY_TX_VERSION_MASK 0x0000001C
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#define PHY_TX_PRS_OFFSET 1
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#define PHY_TX_PRS_MASK 0x00000002
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#define PHY_TX_VLD_OFFSET 0
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#define PHY_TX_VLD_MASK 0x00000001
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//-----------------------------------
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#define CFG_RD_MACPHY_INTF_1_ADDR 0x016c
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#define RX_SW_FC_VLD_OFFSET 5
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#define RX_SW_FC_VLD_MASK 0x00000020
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#define PHY_PB_RCV_DONE_OFFSET 4
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#define PHY_PB_RCV_DONE_MASK 0x00000010
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#define PHY_FC_RCV_DONE_OFFSET 3
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#define PHY_FC_RCV_DONE_MASK 0x00000008
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#define PHY_RX_VERSION_OFFSET 0
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#define PHY_RX_VERSION_MASK 0x00000007
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//HW module read/write macro
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#define RGF_MAC_READ_REG(addr) SOC_READ_REG(RGF_MAC_BASEADDR + addr)
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#define RGF_MAC_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_BASEADDR + addr,value)
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