237 lines
7.4 KiB
C
237 lines
7.4 KiB
C
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//-----------------------------------
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#define CFG_INTC_RVER_ADDR 0x0000
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#define INTC_RF_VER_OFFSET 0
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#define INTC_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_INT_ENA0_ADDR 0x0004
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#define INT_ENA0_OFFSET 0
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#define INT_ENA0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_ENA1_ADDR 0x0008
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#define INT_ENA1_OFFSET 0
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#define INT_ENA1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_SRC0_ADDR 0x000c
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#define INT_SRC0_OFFSET 0
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#define INT_SRC0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_SRC1_ADDR 0x0010
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#define INT_SRC1_OFFSET 0
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#define INT_SRC1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_STS0_ADDR 0x0014
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#define INT_STS0_OFFSET 0
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#define INT_STS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_STS1_ADDR 0x0018
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#define INT_STS1_OFFSET 0
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#define INT_STS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INT_PRI_STS_ADDR 0x001c
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#define INT_ID_OFFSET 8
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#define INT_ID_MASK 0x00003F00
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#define INT_PRI_STS_OFFSET 0
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#define INT_PRI_STS_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_SEL_ADDR 0x0020
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#define INT_PRI_SEL_OFFSET 0
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#define INT_PRI_SEL_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG0_ADDR 0x0030
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#define INT7_PRI_CFG_OFFSET 28
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#define INT7_PRI_CFG_MASK 0x70000000
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#define INT6_PRI_CFG_OFFSET 24
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#define INT6_PRI_CFG_MASK 0x07000000
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#define INT5_PRI_CFG_OFFSET 20
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#define INT5_PRI_CFG_MASK 0x00700000
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#define INT4_PRI_CFG_OFFSET 16
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#define INT4_PRI_CFG_MASK 0x00070000
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#define INT3_PRI_CFG_OFFSET 12
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#define INT3_PRI_CFG_MASK 0x00007000
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#define INT2_PRI_CFG_OFFSET 8
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#define INT2_PRI_CFG_MASK 0x00000700
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#define INT1_PRI_CFG_OFFSET 4
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#define INT1_PRI_CFG_MASK 0x00000070
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#define INT0_PRI_CFG_OFFSET 0
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#define INT0_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG1_ADDR 0x0034
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#define INT15_PRI_CFG_OFFSET 28
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#define INT15_PRI_CFG_MASK 0x70000000
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#define INT14_PRI_CFG_OFFSET 24
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#define INT14_PRI_CFG_MASK 0x07000000
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#define INT13_PRI_CFG_OFFSET 20
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#define INT13_PRI_CFG_MASK 0x00700000
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#define INT12_PRI_CFG_OFFSET 16
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#define INT12_PRI_CFG_MASK 0x00070000
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#define INT11_PRI_CFG_OFFSET 12
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#define INT11_PRI_CFG_MASK 0x00007000
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#define INT10_PRI_CFG_OFFSET 8
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#define INT10_PRI_CFG_MASK 0x00000700
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#define INT9_PRI_CFG_OFFSET 4
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#define INT9_PRI_CFG_MASK 0x00000070
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#define INT8_PRI_CFG_OFFSET 0
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#define INT8_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG2_ADDR 0x0038
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#define INT23_PRI_CFG_OFFSET 28
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#define INT23_PRI_CFG_MASK 0x70000000
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#define INT22_PRI_CFG_OFFSET 24
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#define INT22_PRI_CFG_MASK 0x07000000
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#define INT21_PRI_CFG_OFFSET 20
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#define INT21_PRI_CFG_MASK 0x00700000
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#define INT20_PRI_CFG_OFFSET 16
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#define INT20_PRI_CFG_MASK 0x00070000
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#define INT19_PRI_CFG_OFFSET 12
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#define INT19_PRI_CFG_MASK 0x00007000
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#define INT18_PRI_CFG_OFFSET 8
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#define INT18_PRI_CFG_MASK 0x00000700
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#define INT17_PRI_CFG_OFFSET 4
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#define INT17_PRI_CFG_MASK 0x00000070
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#define INT16_PRI_CFG_OFFSET 0
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#define INT16_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG3_ADDR 0x003c
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#define INT31_PRI_CFG_OFFSET 28
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#define INT31_PRI_CFG_MASK 0x70000000
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#define INT30_PRI_CFG_OFFSET 24
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#define INT30_PRI_CFG_MASK 0x07000000
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#define INT29_PRI_CFG_OFFSET 20
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#define INT29_PRI_CFG_MASK 0x00700000
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#define INT28_PRI_CFG_OFFSET 16
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#define INT28_PRI_CFG_MASK 0x00070000
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#define INT27_PRI_CFG_OFFSET 12
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#define INT27_PRI_CFG_MASK 0x00007000
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#define INT26_PRI_CFG_OFFSET 8
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#define INT26_PRI_CFG_MASK 0x00000700
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#define INT25_PRI_CFG_OFFSET 4
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#define INT25_PRI_CFG_MASK 0x00000070
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#define INT24_PRI_CFG_OFFSET 0
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#define INT24_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG4_ADDR 0x0040
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#define INT39_PRI_CFG_OFFSET 28
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#define INT39_PRI_CFG_MASK 0x70000000
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#define INT38_PRI_CFG_OFFSET 24
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#define INT38_PRI_CFG_MASK 0x07000000
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#define INT37_PRI_CFG_OFFSET 20
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#define INT37_PRI_CFG_MASK 0x00700000
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#define INT36_PRI_CFG_OFFSET 16
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#define INT36_PRI_CFG_MASK 0x00070000
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#define INT35_PRI_CFG_OFFSET 12
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#define INT35_PRI_CFG_MASK 0x00007000
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#define INT34_PRI_CFG_OFFSET 8
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#define INT34_PRI_CFG_MASK 0x00000700
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#define INT33_PRI_CFG_OFFSET 4
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#define INT33_PRI_CFG_MASK 0x00000070
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#define INT32_PRI_CFG_OFFSET 0
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#define INT32_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG5_ADDR 0x0044
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#define INT47_PRI_CFG_OFFSET 28
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#define INT47_PRI_CFG_MASK 0x70000000
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#define INT46_PRI_CFG_OFFSET 24
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#define INT46_PRI_CFG_MASK 0x07000000
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#define INT45_PRI_CFG_OFFSET 20
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#define INT45_PRI_CFG_MASK 0x00700000
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#define INT44_PRI_CFG_OFFSET 16
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#define INT44_PRI_CFG_MASK 0x00070000
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#define INT43_PRI_CFG_OFFSET 12
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#define INT43_PRI_CFG_MASK 0x00007000
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#define INT42_PRI_CFG_OFFSET 8
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#define INT42_PRI_CFG_MASK 0x00000700
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#define INT41_PRI_CFG_OFFSET 4
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#define INT41_PRI_CFG_MASK 0x00000070
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#define INT40_PRI_CFG_OFFSET 0
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#define INT40_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG6_ADDR 0x0048
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#define INT55_PRI_CFG_OFFSET 28
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#define INT55_PRI_CFG_MASK 0x70000000
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#define INT54_PRI_CFG_OFFSET 24
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#define INT54_PRI_CFG_MASK 0x07000000
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#define INT53_PRI_CFG_OFFSET 20
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#define INT53_PRI_CFG_MASK 0x00700000
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#define INT52_PRI_CFG_OFFSET 16
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#define INT52_PRI_CFG_MASK 0x00070000
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#define INT51_PRI_CFG_OFFSET 12
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#define INT51_PRI_CFG_MASK 0x00007000
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#define INT50_PRI_CFG_OFFSET 8
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#define INT50_PRI_CFG_MASK 0x00000700
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#define INT49_PRI_CFG_OFFSET 4
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#define INT49_PRI_CFG_MASK 0x00000070
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#define INT48_PRI_CFG_OFFSET 0
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#define INT48_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INT_PRI_CFG7_ADDR 0x004c
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#define INT63_PRI_CFG_OFFSET 28
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#define INT63_PRI_CFG_MASK 0x70000000
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#define INT62_PRI_CFG_OFFSET 24
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#define INT62_PRI_CFG_MASK 0x07000000
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#define INT61_PRI_CFG_OFFSET 20
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#define INT61_PRI_CFG_MASK 0x00700000
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#define INT60_PRI_CFG_OFFSET 16
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#define INT60_PRI_CFG_MASK 0x00070000
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#define INT59_PRI_CFG_OFFSET 12
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#define INT59_PRI_CFG_MASK 0x00007000
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#define INT58_PRI_CFG_OFFSET 8
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#define INT58_PRI_CFG_MASK 0x00000700
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#define INT57_PRI_CFG_OFFSET 4
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#define INT57_PRI_CFG_MASK 0x00000070
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#define INT56_PRI_CFG_OFFSET 0
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#define INT56_PRI_CFG_MASK 0x00000007
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//-----------------------------------
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#define CFG_INTER_MSIP_ADDR 0x0050
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#define MSIP_REG_OFFSET 0
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#define MSIP_REG_MASK 0x00000001
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//-----------------------------------
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#define CFG_INTER_MTIP_CTL1_ADDR 0x0054
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#define MTIP_INT_FORCE_OFFSET 24
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#define MTIP_INT_FORCE_MASK 0x01000000
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#define MTIP_INT_EN_OFFSET 16
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#define MTIP_INT_EN_MASK 0x00010000
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#define MTIP_CNT_DONE_OFFSET 8
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#define MTIP_CNT_DONE_MASK 0x00000100
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#define MTIP_CNT_EN_OFFSET 0
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#define MTIP_CNT_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_INTER_MTIP_CTL2_ADDR 0x0058
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#define MTIP_CNT_INT_CLR_OFFSET 0
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#define MTIP_CNT_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_INTER_MTIP_CNT_ADDR 0x005C
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#define MTIP_CNT_OFFSET 0
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#define MTIP_CNT_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_INTER_MTIP_CMP_ADDR 0x0060
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#define MTIP_CMP_OFFSET 0
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#define MTIP_CMP_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define INTC_READ_REG(addr) SOC_READ_REG(INTC_BASEADDR + addr)
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#define INTC_WRITE_REG(addr,value) SOC_WRITE_REG(INTC_BASEADDR + addr,value)
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#define INTC1_READ_REG(addr) SOC_READ_REG(INTC1_BASEADDR + addr)
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#define INTC1_WRITE_REG(addr,value) SOC_WRITE_REG(INTC1_BASEADDR + addr,value)
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