303 lines
9.6 KiB
C
303 lines
9.6 KiB
C
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//-----------------------------------
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#define CFG_APB_RVER_ADDR 0x0000
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#define APB_RF_VER_OFFSET 0
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#define APB_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_APB_GLB_GEN0_ADDR 0x0004
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#define PWM0_EB_OFFSET 30
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#define PWM0_EB_MASK 0x40000000
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#define SADC_EB_OFFSET 29
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#define SADC_EB_MASK 0x20000000
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#define IIS_EB_OFFSET 28
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#define IIS_EB_MASK 0x10000000
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#define DMA10_EB_OFFSET 27
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#define DMA10_EB_MASK 0x08000000
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#define DMA9_EB_OFFSET 26
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#define DMA9_EB_MASK 0x04000000
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#define DMA8_EB_OFFSET 25
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#define DMA8_EB_MASK 0x02000000
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#define DMA7_EB_OFFSET 24
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#define DMA7_EB_MASK 0x01000000
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#define DMA6_EB_OFFSET 23
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#define DMA6_EB_MASK 0x00800000
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#define DMA5_EB_OFFSET 22
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#define DMA5_EB_MASK 0x00400000
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#define DMA4_EB_OFFSET 21
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#define DMA4_EB_MASK 0x00200000
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#define DMA3_EB_OFFSET 20
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#define DMA3_EB_MASK 0x00100000
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#define DMA2_EB_OFFSET 19
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#define DMA2_EB_MASK 0x00080000
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#define DMA1_EB_OFFSET 18
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#define DMA1_EB_MASK 0x00040000
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#define DMA0_EB_OFFSET 17
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#define DMA0_EB_MASK 0x00020000
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#define UART_MEM_EB_OFFSET 16
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#define UART_MEM_EB_MASK 0x00010000
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#define UART_3_EB_OFFSET 15
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#define UART_3_EB_MASK 0x00008000
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#define CAN_EB_OFFSET 14
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#define CAN_EB_MASK 0x00004000
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#define WDG0_EB_OFFSET 13
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#define WDG0_EB_MASK 0x00002000
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#define STMR_EB_OFFSET 12
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#define STMR_EB_MASK 0x00001000
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#define SPI_S0_EB_OFFSET 11
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#define SPI_S0_EB_MASK 0x00000800
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#define SPI_M1_EB_OFFSET 10
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#define SPI_M1_EB_MASK 0x00000400
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#define SPI_M0_EB_OFFSET 9
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#define SPI_M0_EB_MASK 0x00000200
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#define CLKREG_EB_OFFSET 8
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#define CLKREG_EB_MASK 0x00000100
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#define PINREG_EB_OFFSET 6
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#define PINREG_EB_MASK 0x00000040
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#define UART_2_EB_OFFSET 5
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#define UART_2_EB_MASK 0x00000020
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#define UART_1_EB_OFFSET 4
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#define UART_1_EB_MASK 0x00000010
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#define INTC0_EB_OFFSET 3
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#define INTC0_EB_MASK 0x00000008
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#define GTMR0_EB_OFFSET 2
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#define GTMR0_EB_MASK 0x00000004
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#define GPIO_EB_OFFSET 1
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#define GPIO_EB_MASK 0x00000002
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#define UART_0_EB_OFFSET 0
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#define UART_0_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_GLB_GRST0_ADDR 0x0008
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#define PWM0_SOFT_RST_OFFSET 30
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#define PWM0_SOFT_RST_MASK 0x40000000
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#define SADC_SOFT_RST_OFFSET 29
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#define SADC_SOFT_RST_MASK 0x20000000
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#define IIS_SOFT_RST_OFFSET 28
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#define IIS_SOFT_RST_MASK 0x10000000
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#define DMA10_SOFT_RST_OFFSET 27
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#define DMA10_SOFT_RST_MASK 0x08000000
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#define DMA9_SOFT_RST_OFFSET 26
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#define DMA9_SOFT_RST_MASK 0x04000000
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#define DMA8_SOFT_RST_OFFSET 25
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#define DMA8_SOFT_RST_MASK 0x02000000
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#define DMA7_SOFT_RST_OFFSET 24
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#define DMA7_SOFT_RST_MASK 0x01000000
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#define DMA6_SOFT_RST_OFFSET 23
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#define DMA6_SOFT_RST_MASK 0x00800000
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#define DMA5_SOFT_RST_OFFSET 22
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#define DMA5_SOFT_RST_MASK 0x00400000
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#define DMA4_SOFT_RST_OFFSET 21
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#define DMA4_SOFT_RST_MASK 0x00200000
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#define DMA3_SOFT_RST_OFFSET 20
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#define DMA3_SOFT_RST_MASK 0x00100000
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#define DMA2_SOFT_RST_OFFSET 19
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#define DMA2_SOFT_RST_MASK 0x00080000
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#define DMA1_SOFT_RST_OFFSET 18
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#define DMA1_SOFT_RST_MASK 0x00040000
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#define DMA0_SOFT_RST_OFFSET 17
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#define DMA0_SOFT_RST_MASK 0x00020000
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#define UART_MEM_SOFT_RST_OFFSET 16
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#define UART_MEM_SOFT_RST_MASK 0x00010000
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#define UART_3_SOFT_RST_OFFSET 15
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#define UART_3_SOFT_RST_MASK 0x00008000
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#define CAN_SOFT_RST_OFFSET 14
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#define CAN_SOFT_RST_MASK 0x00004000
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#define WDG0_SOFT_RST_OFFSET 13
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#define WDG0_SOFT_RST_MASK 0x00002000
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#define STMR_SOFT_RST_OFFSET 12
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#define STMR_SOFT_RST_MASK 0x00001000
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#define SPI_S0_SOFT_RST_OFFSET 11
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#define SPI_S0_SOFT_RST_MASK 0x00000800
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#define SPI_M1_SOFT_RST_OFFSET 10
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#define SPI_M1_SOFT_RST_MASK 0x00000400
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#define SPI_M0_SOFT_RST_OFFSET 9
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#define SPI_M0_SOFT_RST_MASK 0x00000200
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#define CLKREG_SOFT_RST_OFFSET 8
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#define CLKREG_SOFT_RST_MASK 0x00000100
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#define PINREG_SOFT_RST_OFFSET 6
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#define PINREG_SOFT_RST_MASK 0x00000040
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#define UART_2_SOFT_RST_OFFSET 5
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#define UART_2_SOFT_RST_MASK 0x00000020
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#define UART_1_SOFT_RST_OFFSET 4
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#define UART_1_SOFT_RST_MASK 0x00000010
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#define INTC0_SOFT_RST_OFFSET 3
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#define INTC0_SOFT_RST_MASK 0x00000008
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#define GTMR0_SOFT_RST_OFFSET 2
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#define GTMR0_SOFT_RST_MASK 0x00000004
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#define GPIO_SOFT_RST_OFFSET 1
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#define GPIO_SOFT_RST_MASK 0x00000002
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#define UART_0_SOFT_RST_OFFSET 0
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#define UART_0_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_GPIO_CFG_ADDR 0x000c
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#define GPIO_ENA_CFG_OFFSET 0
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#define GPIO_ENA_CFG_MASK 0x000001FF
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//-----------------------------------
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#define CFG_APB_GLB_CTRL_ADDR 0x0010
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#define GLB_CTRL0_OFFSET 0
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#define GLB_CTRL0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_APB_UART_LR_ADDR 0x0014
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#define PUART3_FIFO_LR_OFFSET 3
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#define PUART3_FIFO_LR_MASK 0x00000008
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#define PUART2_FIFO_LR_OFFSET 2
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#define PUART2_FIFO_LR_MASK 0x00000004
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#define PUART1_FIFO_LR_OFFSET 1
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#define PUART1_FIFO_LR_MASK 0x00000002
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#define PUART0_FIFO_LR_OFFSET 0
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#define PUART0_FIFO_LR_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_SADC_CFG0_ADDR 0x0018
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#define SADC_DATA_SUM_OFFSET 16
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#define SADC_DATA_SUM_MASK 0xFFFF0000
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#define SADC_SUM_VLD_OFFSET 15
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#define SADC_SUM_VLD_MASK 0x00008000
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#define SADC_SUM_CLR_OFFSET 14
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#define SADC_SUM_CLR_MASK 0x00004000
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#define SADC_DATA_CNT_OFFSET 8
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#define SADC_DATA_CNT_MASK 0x00003F00
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#define SADC_DATA_NUM_OFFSET 0
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#define SADC_DATA_NUM_MASK 0x0000003F
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//-----------------------------------
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#define CFG_APB_GLB_GEN1_ADDR 0x001c
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#define I2C1_EB_OFFSET 8
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#define I2C1_EB_MASK 0x00000100
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#define I2C0_EB_OFFSET 7
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#define I2C0_EB_MASK 0x00000080
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#define SIG_PWM3_EB_OFFSET 6
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#define SIG_PWM3_EB_MASK 0x00000040
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#define SIG_PWM2_EB_OFFSET 5
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#define SIG_PWM2_EB_MASK 0x00000020
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#define SIG_PWM1_EB_OFFSET 4
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#define SIG_PWM1_EB_MASK 0x00000010
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#define SIG_PWM0_EB_OFFSET 3
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#define SIG_PWM0_EB_MASK 0x00000008
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#define GMTX_EB_OFFSET 2
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#define GMTX_EB_MASK 0x00000004
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#define PWM2_EB_OFFSET 1
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#define PWM2_EB_MASK 0x00000002
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#define PWM1_EB_OFFSET 0
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#define PWM1_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_GLB_GRST1_ADDR 0x0020
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#define I2C1_SOFT_RST_OFFSET 8
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#define I2C1_SOFT_RST_MASK 0x00000100
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#define I2C0_SOFT_RST_OFFSET 7
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#define I2C0_SOFT_RST_MASK 0x00000080
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#define SIG_PWM3_SOFT_RST_OFFSET 6
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#define SIG_PWM3_SOFT_RST_MASK 0x00000040
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#define SIG_PWM2_SOFT_RST_OFFSET 5
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#define SIG_PWM2_SOFT_RST_MASK 0x00000020
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#define SIG_PWM1_SOFT_RST_OFFSET 4
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#define SIG_PWM1_SOFT_RST_MASK 0x00000010
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#define SIG_PWM0_SOFT_RST_OFFSET 3
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#define SIG_PWM0_SOFT_RST_MASK 0x00000008
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#define GMTX_SOFT_RST_OFFSET 2
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#define GMTX_SOFT_RST_MASK 0x00000004
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#define PWM2_SOFT_RST_OFFSET 1
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#define PWM2_SOFT_RST_MASK 0x00000002
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#define PWM1_SOFT_RST_OFFSET 0
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#define PWM1_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_UART_CFG_ADDR 0x0024
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#define UART3_RXD_FROM_ANA_OFFSET 11
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#define UART3_RXD_FROM_ANA_MASK 0x00000800
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#define UART2_RXD_FROM_ANA_OFFSET 10
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#define UART2_RXD_FROM_ANA_MASK 0x00000400
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#define UART1_RXD_FROM_ANA_OFFSET 9
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#define UART1_RXD_FROM_ANA_MASK 0x00000200
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#define UART0_RXD_FROM_ANA_OFFSET 8
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#define UART0_RXD_FROM_ANA_MASK 0x00000100
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#define CLK_38KHZ_ENA_OFFSET 4
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#define CLK_38KHZ_ENA_MASK 0x00000010
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#define UART3_IRDA_MODE_OFFSET 3
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#define UART3_IRDA_MODE_MASK 0x00000008
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#define UART2_IRDA_MODE_OFFSET 2
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#define UART2_IRDA_MODE_MASK 0x00000004
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#define UART1_IRDA_MODE_OFFSET 1
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#define UART1_IRDA_MODE_MASK 0x00000002
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#define UART0_IRDA_MODE_OFFSET 0
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#define UART0_IRDA_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_ANA_CFG0_ADDR 0x0028
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#define RX_GLAN_SEL_OFFSET 13
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#define RX_GLAN_SEL_MASK 0x00002000
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#define DAC_DATA_SEL_OFFSET 12
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#define DAC_DATA_SEL_MASK 0x00001000
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#define ANA_I2C_SOFT_RST_OFFSET 11
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#define ANA_I2C_SOFT_RST_MASK 0x00000800
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#define DCDC_DIS_LMTCUR_OFFSET 10
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#define DCDC_DIS_LMTCUR_MASK 0x00000400
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#define DCDC_EN_PFM_OFFSET 9
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#define DCDC_EN_PFM_MASK 0x00000200
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#define DCDC_LMTCUR_250M_OFFSET 8
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#define DCDC_LMTCUR_250M_MASK 0x00000100
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#define SELB_1P8_OFFSET 5
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#define SELB_1P8_MASK 0x00000020
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#define BURN_IN_OFFSET 4
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#define BURN_IN_MASK 0x00000010
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#define ANA_DEBUG_SEL_OFFSET 0
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#define ANA_DEBUG_SEL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_APB_SADC_CFG1_ADDR 0x002c
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#define SADC_RX_EOF_NUM_OFFSET 0
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#define SADC_RX_EOF_NUM_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SIG_PWM0_CFG_ADDR 0x0030
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#define SIG_PWM0_PRESCALAR_OFFSET 8
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#define SIG_PWM0_PRESCALAR_MASK 0x0000FF00
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#define SIG_PWM0_TARGET_OFFSET 0
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#define SIG_PWM0_TARGET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG_PWM1_CFG_ADDR 0x0034
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#define SIG_PWM1_PRESCALAR_OFFSET 8
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#define SIG_PWM1_PRESCALAR_MASK 0x0000FF00
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#define SIG_PWM1_TARGET_OFFSET 0
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#define SIG_PWM1_TARGET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG_PWM2_CFG_ADDR 0x0038
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#define SIG_PWM2_PRESCALAR_OFFSET 8
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#define SIG_PWM2_PRESCALAR_MASK 0x0000FF00
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#define SIG_PWM2_TARGET_OFFSET 0
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#define SIG_PWM2_TARGET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG_PWM3_CFG_ADDR 0x003c
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#define SIG_PWM3_PRESCALAR_OFFSET 8
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#define SIG_PWM3_PRESCALAR_MASK 0x0000FF00
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#define SIG_PWM3_TARGET_OFFSET 0
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#define SIG_PWM3_TARGET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_APB_SADC_CFG2_ADDR 0x0040
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#define SADC_SEL_FAST_OFFSET 8
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#define SADC_SEL_FAST_MASK 0x00000100
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#define SADC_PHASE_SW_MAX_OFFSET 4
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#define SADC_PHASE_SW_MAX_MASK 0x00000030
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#define SADC_PHASE_SEL_OFFSET 2
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#define SADC_PHASE_SEL_MASK 0x0000000C
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#define SADC_MODE_OFFSET 0
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#define SADC_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_FTST_CFG_ADDR 0x0044
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#define FUNCTST_FORCE_EB_OFFSET 0
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#define FUNCTST_FORCE_EB_MASK 0x00000001
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//HW module read/write macro
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#define APB_GLB_READ_REG(addr) SOC_READ_REG(APB_GLB_BASEADDR + addr)
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#define APB_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(APB_GLB_BASEADDR + addr,value)
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