56 lines
1.9 KiB
C
56 lines
1.9 KiB
C
#define SPI_MST_BASEADDR 0x4400A000
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#define ADA_BASEADDR 0x53200000
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#define EFUSE_DIG_BASEADDR 0x62040000
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#define GTMR_BASEADDR 0x44003000
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#define GTMR1_BASEADDR 0x62020000
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#define INTC_BASEADDR 0x44004000
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#define INTC1_BASEADDR 0x62030000
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#define RGF_HWQ_BASEADDR 0x51000800
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#define RGF_MAC_INT_BASEADDR 0x00000000
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#define RGF_RAW_BASEADDR 0x51001000
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#define RGF_MAC_RX_DESC_BASEADDR 0x00000000
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#define RGF_RX_BASEADDR 0x51000C00
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#define RGF_MAC_BASEADDR 0x51000000
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#define RGF_TMR_BASEADDR 0x51000400
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#define RGF_MAC_TX_DESC_BASEADDR 0x00000000
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#define PHY_TX_BASEADDR 0x51900000
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#define SEC_SYS_RF_BASEADDR 0x60000000
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#define SPI_BASEADDR 0x4400A000
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#define SPI1_BASEADDR 0x4400B000
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#define SPI2_BASEADDR 0x4400C000
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#define APB_UART_BASEADDR 0x44001000
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#define APB_UART1_BASEADDR 0x44005000
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#define APB_UART2_BASEADDR 0x44006000
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#define APB_UART3_BASEADDR 0x44010000
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#define WDG_BASEADDR 0x4400e000
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#define WDG1_BASEADDR 0x62010000
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#define GPIO_BASEADDR 0x4400_2000
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#define MAIL_BOX_RF_BASEADDR 0x55000000
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#define MAIL_BOX_RF1_BASEADDR 0x65000000
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#define SEC_GLB_RF_BASEADDR 0x62000000
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#define I2S_BASEADDR 0x4401F000
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#define PHY_DFE_BASEADDR 0x51C00000
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#define APB_GLB_BASEADDR 0x44000000
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#define SFC_RF_BASEADDR 0x61000100
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#define SMC_RF_BASEADDR 0x61000200
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#define DMA_BASEADDR 0x44012000
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#define DMA1_BASEADDR 0x44013000
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#define DMA2_BASEADDR 0x44014000
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#define DMA3_BASEADDR 0x44015000
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#define DMA4_BASEADDR 0x44016000
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#define DMA5_BASEADDR 0x44017000
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#define DMA6_BASEADDR 0x44018000
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#define DMA7_BASEADDR 0x44019000
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#define DMA8_BASEADDR 0x4401A000
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#define DMA9_BASEADDR 0x4401B000
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#define DMA10_BASEADDR 0x4401C000
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#define AHB_RF_BASEADDR 0x50000000
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#define PHY_RXTD_BASEADDR 0x51A00000
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#define SNAPSHOT_RF_BASEADDR 0x52000000
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#define PHY_BASEADDR 0x51800000
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#define PIN_RF_BASEADDR 0x44007000
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#define GPIO_MTX_BASEADDR 0x44020000
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#define PHY_RX_FD_BASEADDR 0x51B00000
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#define SW_DMA_REG0_BASEADDR 0x70000000
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#define SW_DMA_REG1_BASEADDR 0x71000000
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