1818 lines
59 KiB
C
1818 lines
59 KiB
C
|
|
//-----------------------------------
|
|
#define CFG_RSTL_PIN_CFG_ADDR 0x4
|
|
#define RSTL_SEC_OFFSET 17
|
|
#define RSTL_SEC_MASK 0x00020000
|
|
#define RSTL_ODRV_OFFSET 16
|
|
#define RSTL_ODRV_MASK 0x00010000
|
|
#define RSTL_IINV_OFFSET 15
|
|
#define RSTL_IINV_MASK 0x00008000
|
|
#define RSTL_OINV_OFFSET 14
|
|
#define RSTL_OINV_MASK 0x00004000
|
|
#define RSTL_OPOS_OFFSET 13
|
|
#define RSTL_OPOS_MASK 0x00002000
|
|
#define RSTL_ONEG_OFFSET 12
|
|
#define RSTL_ONEG_MASK 0x00001000
|
|
#define RSTL_IPOS_OFFSET 11
|
|
#define RSTL_IPOS_MASK 0x00000800
|
|
#define RSTL_INEG_OFFSET 10
|
|
#define RSTL_INEG_MASK 0x00000400
|
|
#define RSTL_ORE_OFFSET 9
|
|
#define RSTL_ORE_MASK 0x00000200
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|
#define RSTL_IRE_OFFSET 8
|
|
#define RSTL_IRE_MASK 0x00000100
|
|
#define RSTL_FUNC_WPU_OFFSET 7
|
|
#define RSTL_FUNC_WPU_MASK 0x00000080
|
|
#define RSTL_FUNC_WPD_OFFSET 6
|
|
#define RSTL_FUNC_WPD_MASK 0x00000040
|
|
#define RSTL_FUNC_SEL_OFFSET 4
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|
#define RSTL_FUNC_SEL_MASK 0x00000030
|
|
#define RSTL_MCU_WPU_OFFSET 3
|
|
#define RSTL_MCU_WPU_MASK 0x00000008
|
|
#define RSTL_MCU_WPD_OFFSET 2
|
|
#define RSTL_MCU_WPD_MASK 0x00000004
|
|
#define RSTL_MCU_IE_OFFSET 1
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|
#define RSTL_MCU_IE_MASK 0x00000002
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|
#define RSTL_MCU_OE_OFFSET 0
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|
#define RSTL_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
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|
#define CFG_UART0_TXD_PIN_CFG_ADDR 0x8
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|
#define UART0_TXD_SEC_OFFSET 17
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|
#define UART0_TXD_SEC_MASK 0x00020000
|
|
#define UART0_TXD_ODRV_OFFSET 16
|
|
#define UART0_TXD_ODRV_MASK 0x00010000
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|
#define UART0_TXD_IINV_OFFSET 15
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|
#define UART0_TXD_IINV_MASK 0x00008000
|
|
#define UART0_TXD_OINV_OFFSET 14
|
|
#define UART0_TXD_OINV_MASK 0x00004000
|
|
#define UART0_TXD_OPOS_OFFSET 13
|
|
#define UART0_TXD_OPOS_MASK 0x00002000
|
|
#define UART0_TXD_ONEG_OFFSET 12
|
|
#define UART0_TXD_ONEG_MASK 0x00001000
|
|
#define UART0_TXD_IPOS_OFFSET 11
|
|
#define UART0_TXD_IPOS_MASK 0x00000800
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|
#define UART0_TXD_INEG_OFFSET 10
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|
#define UART0_TXD_INEG_MASK 0x00000400
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|
#define UART0_TXD_ORE_OFFSET 9
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|
#define UART0_TXD_ORE_MASK 0x00000200
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|
#define UART0_TXD_IRE_OFFSET 8
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|
#define UART0_TXD_IRE_MASK 0x00000100
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|
#define UART0_TXD_FUNC_WPU_OFFSET 7
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|
#define UART0_TXD_FUNC_WPU_MASK 0x00000080
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|
#define UART0_TXD_FUNC_WPD_OFFSET 6
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|
#define UART0_TXD_FUNC_WPD_MASK 0x00000040
|
|
#define UART0_TXD_FUNC_SEL_OFFSET 4
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|
#define UART0_TXD_FUNC_SEL_MASK 0x00000030
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|
#define UART0_TXD_MCU_WPU_OFFSET 3
|
|
#define UART0_TXD_MCU_WPU_MASK 0x00000008
|
|
#define UART0_TXD_MCU_WPD_OFFSET 2
|
|
#define UART0_TXD_MCU_WPD_MASK 0x00000004
|
|
#define UART0_TXD_MCU_IE_OFFSET 1
|
|
#define UART0_TXD_MCU_IE_MASK 0x00000002
|
|
#define UART0_TXD_MCU_OE_OFFSET 0
|
|
#define UART0_TXD_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_UART0_RXD_PIN_CFG_ADDR 0xc
|
|
#define UART0_RXD_SEC_OFFSET 17
|
|
#define UART0_RXD_SEC_MASK 0x00020000
|
|
#define UART0_RXD_ODRV_OFFSET 16
|
|
#define UART0_RXD_ODRV_MASK 0x00010000
|
|
#define UART0_RXD_IINV_OFFSET 15
|
|
#define UART0_RXD_IINV_MASK 0x00008000
|
|
#define UART0_RXD_OINV_OFFSET 14
|
|
#define UART0_RXD_OINV_MASK 0x00004000
|
|
#define UART0_RXD_OPOS_OFFSET 13
|
|
#define UART0_RXD_OPOS_MASK 0x00002000
|
|
#define UART0_RXD_ONEG_OFFSET 12
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|
#define UART0_RXD_ONEG_MASK 0x00001000
|
|
#define UART0_RXD_IPOS_OFFSET 11
|
|
#define UART0_RXD_IPOS_MASK 0x00000800
|
|
#define UART0_RXD_INEG_OFFSET 10
|
|
#define UART0_RXD_INEG_MASK 0x00000400
|
|
#define UART0_RXD_ORE_OFFSET 9
|
|
#define UART0_RXD_ORE_MASK 0x00000200
|
|
#define UART0_RXD_IRE_OFFSET 8
|
|
#define UART0_RXD_IRE_MASK 0x00000100
|
|
#define UART0_RXD_FUNC_WPU_OFFSET 7
|
|
#define UART0_RXD_FUNC_WPU_MASK 0x00000080
|
|
#define UART0_RXD_FUNC_WPD_OFFSET 6
|
|
#define UART0_RXD_FUNC_WPD_MASK 0x00000040
|
|
#define UART0_RXD_FUNC_SEL_OFFSET 4
|
|
#define UART0_RXD_FUNC_SEL_MASK 0x00000030
|
|
#define UART0_RXD_MCU_WPU_OFFSET 3
|
|
#define UART0_RXD_MCU_WPU_MASK 0x00000008
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|
#define UART0_RXD_MCU_WPD_OFFSET 2
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|
#define UART0_RXD_MCU_WPD_MASK 0x00000004
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|
#define UART0_RXD_MCU_IE_OFFSET 1
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|
#define UART0_RXD_MCU_IE_MASK 0x00000002
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|
#define UART0_RXD_MCU_OE_OFFSET 0
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|
#define UART0_RXD_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TMS_PIN_CFG_ADDR 0x10
|
|
#define TMS_SEC_OFFSET 17
|
|
#define TMS_SEC_MASK 0x00020000
|
|
#define TMS_ODRV_OFFSET 16
|
|
#define TMS_ODRV_MASK 0x00010000
|
|
#define TMS_IINV_OFFSET 15
|
|
#define TMS_IINV_MASK 0x00008000
|
|
#define TMS_OINV_OFFSET 14
|
|
#define TMS_OINV_MASK 0x00004000
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|
#define TMS_OPOS_OFFSET 13
|
|
#define TMS_OPOS_MASK 0x00002000
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|
#define TMS_ONEG_OFFSET 12
|
|
#define TMS_ONEG_MASK 0x00001000
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|
#define TMS_IPOS_OFFSET 11
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|
#define TMS_IPOS_MASK 0x00000800
|
|
#define TMS_INEG_OFFSET 10
|
|
#define TMS_INEG_MASK 0x00000400
|
|
#define TMS_ORE_OFFSET 9
|
|
#define TMS_ORE_MASK 0x00000200
|
|
#define TMS_IRE_OFFSET 8
|
|
#define TMS_IRE_MASK 0x00000100
|
|
#define TMS_FUNC_WPU_OFFSET 7
|
|
#define TMS_FUNC_WPU_MASK 0x00000080
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|
#define TMS_FUNC_WPD_OFFSET 6
|
|
#define TMS_FUNC_WPD_MASK 0x00000040
|
|
#define TMS_FUNC_SEL_OFFSET 4
|
|
#define TMS_FUNC_SEL_MASK 0x00000030
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|
#define TMS_MCU_WPU_OFFSET 3
|
|
#define TMS_MCU_WPU_MASK 0x00000008
|
|
#define TMS_MCU_WPD_OFFSET 2
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|
#define TMS_MCU_WPD_MASK 0x00000004
|
|
#define TMS_MCU_IE_OFFSET 1
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|
#define TMS_MCU_IE_MASK 0x00000002
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|
#define TMS_MCU_OE_OFFSET 0
|
|
#define TMS_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TCK_PIN_CFG_ADDR 0x14
|
|
#define TCK_SEC_OFFSET 17
|
|
#define TCK_SEC_MASK 0x00020000
|
|
#define TCK_ODRV_OFFSET 16
|
|
#define TCK_ODRV_MASK 0x00010000
|
|
#define TCK_IINV_OFFSET 15
|
|
#define TCK_IINV_MASK 0x00008000
|
|
#define TCK_OINV_OFFSET 14
|
|
#define TCK_OINV_MASK 0x00004000
|
|
#define TCK_OPOS_OFFSET 13
|
|
#define TCK_OPOS_MASK 0x00002000
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|
#define TCK_ONEG_OFFSET 12
|
|
#define TCK_ONEG_MASK 0x00001000
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|
#define TCK_IPOS_OFFSET 11
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|
#define TCK_IPOS_MASK 0x00000800
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|
#define TCK_INEG_OFFSET 10
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|
#define TCK_INEG_MASK 0x00000400
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|
#define TCK_ORE_OFFSET 9
|
|
#define TCK_ORE_MASK 0x00000200
|
|
#define TCK_IRE_OFFSET 8
|
|
#define TCK_IRE_MASK 0x00000100
|
|
#define TCK_FUNC_WPU_OFFSET 7
|
|
#define TCK_FUNC_WPU_MASK 0x00000080
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|
#define TCK_FUNC_WPD_OFFSET 6
|
|
#define TCK_FUNC_WPD_MASK 0x00000040
|
|
#define TCK_FUNC_SEL_OFFSET 4
|
|
#define TCK_FUNC_SEL_MASK 0x00000030
|
|
#define TCK_MCU_WPU_OFFSET 3
|
|
#define TCK_MCU_WPU_MASK 0x00000008
|
|
#define TCK_MCU_WPD_OFFSET 2
|
|
#define TCK_MCU_WPD_MASK 0x00000004
|
|
#define TCK_MCU_IE_OFFSET 1
|
|
#define TCK_MCU_IE_MASK 0x00000002
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|
#define TCK_MCU_OE_OFFSET 0
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|
#define TCK_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TDO_PIN_CFG_ADDR 0x18
|
|
#define TDO_SEC_OFFSET 17
|
|
#define TDO_SEC_MASK 0x00020000
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|
#define TDO_ODRV_OFFSET 16
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|
#define TDO_ODRV_MASK 0x00010000
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|
#define TDO_IINV_OFFSET 15
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|
#define TDO_IINV_MASK 0x00008000
|
|
#define TDO_OINV_OFFSET 14
|
|
#define TDO_OINV_MASK 0x00004000
|
|
#define TDO_OPOS_OFFSET 13
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|
#define TDO_OPOS_MASK 0x00002000
|
|
#define TDO_ONEG_OFFSET 12
|
|
#define TDO_ONEG_MASK 0x00001000
|
|
#define TDO_IPOS_OFFSET 11
|
|
#define TDO_IPOS_MASK 0x00000800
|
|
#define TDO_INEG_OFFSET 10
|
|
#define TDO_INEG_MASK 0x00000400
|
|
#define TDO_ORE_OFFSET 9
|
|
#define TDO_ORE_MASK 0x00000200
|
|
#define TDO_IRE_OFFSET 8
|
|
#define TDO_IRE_MASK 0x00000100
|
|
#define TDO_FUNC_WPU_OFFSET 7
|
|
#define TDO_FUNC_WPU_MASK 0x00000080
|
|
#define TDO_FUNC_WPD_OFFSET 6
|
|
#define TDO_FUNC_WPD_MASK 0x00000040
|
|
#define TDO_FUNC_SEL_OFFSET 4
|
|
#define TDO_FUNC_SEL_MASK 0x00000030
|
|
#define TDO_MCU_WPU_OFFSET 3
|
|
#define TDO_MCU_WPU_MASK 0x00000008
|
|
#define TDO_MCU_WPD_OFFSET 2
|
|
#define TDO_MCU_WPD_MASK 0x00000004
|
|
#define TDO_MCU_IE_OFFSET 1
|
|
#define TDO_MCU_IE_MASK 0x00000002
|
|
#define TDO_MCU_OE_OFFSET 0
|
|
#define TDO_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TDI_PIN_CFG_ADDR 0x1c
|
|
#define TDI_SEC_OFFSET 17
|
|
#define TDI_SEC_MASK 0x00020000
|
|
#define TDI_ODRV_OFFSET 16
|
|
#define TDI_ODRV_MASK 0x00010000
|
|
#define TDI_IINV_OFFSET 15
|
|
#define TDI_IINV_MASK 0x00008000
|
|
#define TDI_OINV_OFFSET 14
|
|
#define TDI_OINV_MASK 0x00004000
|
|
#define TDI_OPOS_OFFSET 13
|
|
#define TDI_OPOS_MASK 0x00002000
|
|
#define TDI_ONEG_OFFSET 12
|
|
#define TDI_ONEG_MASK 0x00001000
|
|
#define TDI_IPOS_OFFSET 11
|
|
#define TDI_IPOS_MASK 0x00000800
|
|
#define TDI_INEG_OFFSET 10
|
|
#define TDI_INEG_MASK 0x00000400
|
|
#define TDI_ORE_OFFSET 9
|
|
#define TDI_ORE_MASK 0x00000200
|
|
#define TDI_IRE_OFFSET 8
|
|
#define TDI_IRE_MASK 0x00000100
|
|
#define TDI_FUNC_WPU_OFFSET 7
|
|
#define TDI_FUNC_WPU_MASK 0x00000080
|
|
#define TDI_FUNC_WPD_OFFSET 6
|
|
#define TDI_FUNC_WPD_MASK 0x00000040
|
|
#define TDI_FUNC_SEL_OFFSET 4
|
|
#define TDI_FUNC_SEL_MASK 0x00000030
|
|
#define TDI_MCU_WPU_OFFSET 3
|
|
#define TDI_MCU_WPU_MASK 0x00000008
|
|
#define TDI_MCU_WPD_OFFSET 2
|
|
#define TDI_MCU_WPD_MASK 0x00000004
|
|
#define TDI_MCU_IE_OFFSET 1
|
|
#define TDI_MCU_IE_MASK 0x00000002
|
|
#define TDI_MCU_OE_OFFSET 0
|
|
#define TDI_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_TRST_PIN_CFG_ADDR 0x20
|
|
#define TRST_SEC_OFFSET 17
|
|
#define TRST_SEC_MASK 0x00020000
|
|
#define TRST_ODRV_OFFSET 16
|
|
#define TRST_ODRV_MASK 0x00010000
|
|
#define TRST_IINV_OFFSET 15
|
|
#define TRST_IINV_MASK 0x00008000
|
|
#define TRST_OINV_OFFSET 14
|
|
#define TRST_OINV_MASK 0x00004000
|
|
#define TRST_OPOS_OFFSET 13
|
|
#define TRST_OPOS_MASK 0x00002000
|
|
#define TRST_ONEG_OFFSET 12
|
|
#define TRST_ONEG_MASK 0x00001000
|
|
#define TRST_IPOS_OFFSET 11
|
|
#define TRST_IPOS_MASK 0x00000800
|
|
#define TRST_INEG_OFFSET 10
|
|
#define TRST_INEG_MASK 0x00000400
|
|
#define TRST_ORE_OFFSET 9
|
|
#define TRST_ORE_MASK 0x00000200
|
|
#define TRST_IRE_OFFSET 8
|
|
#define TRST_IRE_MASK 0x00000100
|
|
#define TRST_FUNC_WPU_OFFSET 7
|
|
#define TRST_FUNC_WPU_MASK 0x00000080
|
|
#define TRST_FUNC_WPD_OFFSET 6
|
|
#define TRST_FUNC_WPD_MASK 0x00000040
|
|
#define TRST_FUNC_SEL_OFFSET 4
|
|
#define TRST_FUNC_SEL_MASK 0x00000030
|
|
#define TRST_MCU_WPU_OFFSET 3
|
|
#define TRST_MCU_WPU_MASK 0x00000008
|
|
#define TRST_MCU_WPD_OFFSET 2
|
|
#define TRST_MCU_WPD_MASK 0x00000004
|
|
#define TRST_MCU_IE_OFFSET 1
|
|
#define TRST_MCU_IE_MASK 0x00000002
|
|
#define TRST_MCU_OE_OFFSET 0
|
|
#define TRST_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO00_PIN_CFG_ADDR 0x24
|
|
#define GPIO00_SEC_OFFSET 17
|
|
#define GPIO00_SEC_MASK 0x00020000
|
|
#define GPIO00_ODRV_OFFSET 16
|
|
#define GPIO00_ODRV_MASK 0x00010000
|
|
#define GPIO00_OINV_OFFSET 15
|
|
#define GPIO00_OINV_MASK 0x00008000
|
|
#define GPIO00_IINV_OFFSET 14
|
|
#define GPIO00_IINV_MASK 0x00004000
|
|
#define GPIO00_OPOS_OFFSET 13
|
|
#define GPIO00_OPOS_MASK 0x00002000
|
|
#define GPIO00_ONEG_OFFSET 12
|
|
#define GPIO00_ONEG_MASK 0x00001000
|
|
#define GPIO00_IPOS_OFFSET 11
|
|
#define GPIO00_IPOS_MASK 0x00000800
|
|
#define GPIO00_INEG_OFFSET 10
|
|
#define GPIO00_INEG_MASK 0x00000400
|
|
#define GPIO00_ORE_OFFSET 9
|
|
#define GPIO00_ORE_MASK 0x00000200
|
|
#define GPIO00_IRE_OFFSET 8
|
|
#define GPIO00_IRE_MASK 0x00000100
|
|
#define GPIO00_FUNC_WPU_OFFSET 7
|
|
#define GPIO00_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO00_FUNC_WPD_OFFSET 6
|
|
#define GPIO00_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO00_FUNC_SEL_OFFSET 4
|
|
#define GPIO00_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO00_MCU_WPU_OFFSET 3
|
|
#define GPIO00_MCU_WPU_MASK 0x00000008
|
|
#define GPIO00_MCU_WPD_OFFSET 2
|
|
#define GPIO00_MCU_WPD_MASK 0x00000004
|
|
#define GPIO00_MCU_IE_OFFSET 1
|
|
#define GPIO00_MCU_IE_MASK 0x00000002
|
|
#define GPIO00_MCU_OE_OFFSET 0
|
|
#define GPIO00_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO01_PIN_CFG_ADDR 0x28
|
|
#define GPIO01_SEC_OFFSET 17
|
|
#define GPIO01_SEC_MASK 0x00020000
|
|
#define GPIO01_ODRV_OFFSET 16
|
|
#define GPIO01_ODRV_MASK 0x00010000
|
|
#define GPIO01_IINV_OFFSET 15
|
|
#define GPIO01_IINV_MASK 0x00008000
|
|
#define GPIO01_OINV_OFFSET 14
|
|
#define GPIO01_OINV_MASK 0x00004000
|
|
#define GPIO01_OPOS_OFFSET 13
|
|
#define GPIO01_OPOS_MASK 0x00002000
|
|
#define GPIO01_ONEG_OFFSET 12
|
|
#define GPIO01_ONEG_MASK 0x00001000
|
|
#define GPIO01_IPOS_OFFSET 11
|
|
#define GPIO01_IPOS_MASK 0x00000800
|
|
#define GPIO01_INEG_OFFSET 10
|
|
#define GPIO01_INEG_MASK 0x00000400
|
|
#define GPIO01_ORE_OFFSET 9
|
|
#define GPIO01_ORE_MASK 0x00000200
|
|
#define GPIO01_IRE_OFFSET 8
|
|
#define GPIO01_IRE_MASK 0x00000100
|
|
#define GPIO01_FUNC_WPU_OFFSET 7
|
|
#define GPIO01_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO01_FUNC_WPD_OFFSET 6
|
|
#define GPIO01_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO01_FUNC_SEL_OFFSET 4
|
|
#define GPIO01_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO01_MCU_WPU_OFFSET 3
|
|
#define GPIO01_MCU_WPU_MASK 0x00000008
|
|
#define GPIO01_MCU_WPD_OFFSET 2
|
|
#define GPIO01_MCU_WPD_MASK 0x00000004
|
|
#define GPIO01_MCU_IE_OFFSET 1
|
|
#define GPIO01_MCU_IE_MASK 0x00000002
|
|
#define GPIO01_MCU_OE_OFFSET 0
|
|
#define GPIO01_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO02_PIN_CFG_ADDR 0x2c
|
|
#define GPIO02_SEC_OFFSET 17
|
|
#define GPIO02_SEC_MASK 0x00020000
|
|
#define GPIO02_ODRV_OFFSET 16
|
|
#define GPIO02_ODRV_MASK 0x00010000
|
|
#define GPIO02_IINV_OFFSET 15
|
|
#define GPIO02_IINV_MASK 0x00008000
|
|
#define GPIO02_OINV_OFFSET 14
|
|
#define GPIO02_OINV_MASK 0x00004000
|
|
#define GPIO02_OPOS_OFFSET 13
|
|
#define GPIO02_OPOS_MASK 0x00002000
|
|
#define GPIO02_ONEG_OFFSET 12
|
|
#define GPIO02_ONEG_MASK 0x00001000
|
|
#define GPIO02_IPOS_OFFSET 11
|
|
#define GPIO02_IPOS_MASK 0x00000800
|
|
#define GPIO02_INEG_OFFSET 10
|
|
#define GPIO02_INEG_MASK 0x00000400
|
|
#define GPIO02_ORE_OFFSET 9
|
|
#define GPIO02_ORE_MASK 0x00000200
|
|
#define GPIO02_IRE_OFFSET 8
|
|
#define GPIO02_IRE_MASK 0x00000100
|
|
#define GPIO02_FUNC_WPU_OFFSET 7
|
|
#define GPIO02_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO02_FUNC_WPD_OFFSET 6
|
|
#define GPIO02_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO02_FUNC_SEL_OFFSET 4
|
|
#define GPIO02_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO02_MCU_WPU_OFFSET 3
|
|
#define GPIO02_MCU_WPU_MASK 0x00000008
|
|
#define GPIO02_MCU_WPD_OFFSET 2
|
|
#define GPIO02_MCU_WPD_MASK 0x00000004
|
|
#define GPIO02_MCU_IE_OFFSET 1
|
|
#define GPIO02_MCU_IE_MASK 0x00000002
|
|
#define GPIO02_MCU_OE_OFFSET 0
|
|
#define GPIO02_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO03_PIN_CFG_ADDR 0x30
|
|
#define GPIO03_SEC_OFFSET 17
|
|
#define GPIO03_SEC_MASK 0x00020000
|
|
#define GPIO03_ODRV_OFFSET 16
|
|
#define GPIO03_ODRV_MASK 0x00010000
|
|
#define GPIO03_IINV_OFFSET 15
|
|
#define GPIO03_IINV_MASK 0x00008000
|
|
#define GPIO03_OINV_OFFSET 14
|
|
#define GPIO03_OINV_MASK 0x00004000
|
|
#define GPIO03_OPOS_OFFSET 13
|
|
#define GPIO03_OPOS_MASK 0x00002000
|
|
#define GPIO03_ONEG_OFFSET 12
|
|
#define GPIO03_ONEG_MASK 0x00001000
|
|
#define GPIO03_IPOS_OFFSET 11
|
|
#define GPIO03_IPOS_MASK 0x00000800
|
|
#define GPIO03_INEG_OFFSET 10
|
|
#define GPIO03_INEG_MASK 0x00000400
|
|
#define GPIO03_ORE_OFFSET 9
|
|
#define GPIO03_ORE_MASK 0x00000200
|
|
#define GPIO03_IRE_OFFSET 8
|
|
#define GPIO03_IRE_MASK 0x00000100
|
|
#define GPIO03_FUNC_WPU_OFFSET 7
|
|
#define GPIO03_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO03_FUNC_WPD_OFFSET 6
|
|
#define GPIO03_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO03_FUNC_SEL_OFFSET 4
|
|
#define GPIO03_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO03_MCU_WPU_OFFSET 3
|
|
#define GPIO03_MCU_WPU_MASK 0x00000008
|
|
#define GPIO03_MCU_WPD_OFFSET 2
|
|
#define GPIO03_MCU_WPD_MASK 0x00000004
|
|
#define GPIO03_MCU_IE_OFFSET 1
|
|
#define GPIO03_MCU_IE_MASK 0x00000002
|
|
#define GPIO03_MCU_OE_OFFSET 0
|
|
#define GPIO03_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO04_PIN_CFG_ADDR 0x34
|
|
#define GPIO04_SEC_OFFSET 17
|
|
#define GPIO04_SEC_MASK 0x00020000
|
|
#define GPIO04_ODRV_OFFSET 16
|
|
#define GPIO04_ODRV_MASK 0x00010000
|
|
#define GPIO04_IINV_OFFSET 15
|
|
#define GPIO04_IINV_MASK 0x00008000
|
|
#define GPIO04_OINV_OFFSET 14
|
|
#define GPIO04_OINV_MASK 0x00004000
|
|
#define GPIO04_OPOS_OFFSET 13
|
|
#define GPIO04_OPOS_MASK 0x00002000
|
|
#define GPIO04_ONEG_OFFSET 12
|
|
#define GPIO04_ONEG_MASK 0x00001000
|
|
#define GPIO04_IPOS_OFFSET 11
|
|
#define GPIO04_IPOS_MASK 0x00000800
|
|
#define GPIO04_INEG_OFFSET 10
|
|
#define GPIO04_INEG_MASK 0x00000400
|
|
#define GPIO04_ORE_OFFSET 9
|
|
#define GPIO04_ORE_MASK 0x00000200
|
|
#define GPIO04_IRE_OFFSET 8
|
|
#define GPIO04_IRE_MASK 0x00000100
|
|
#define GPIO04_FUNC_WPU_OFFSET 7
|
|
#define GPIO04_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO04_FUNC_WPD_OFFSET 6
|
|
#define GPIO04_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO04_FUNC_SEL_OFFSET 4
|
|
#define GPIO04_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO04_MCU_WPU_OFFSET 3
|
|
#define GPIO04_MCU_WPU_MASK 0x00000008
|
|
#define GPIO04_MCU_WPD_OFFSET 2
|
|
#define GPIO04_MCU_WPD_MASK 0x00000004
|
|
#define GPIO04_MCU_IE_OFFSET 1
|
|
#define GPIO04_MCU_IE_MASK 0x00000002
|
|
#define GPIO04_MCU_OE_OFFSET 0
|
|
#define GPIO04_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO05_PIN_CFG_ADDR 0x38
|
|
#define GPIO05_SEC_OFFSET 17
|
|
#define GPIO05_SEC_MASK 0x00020000
|
|
#define GPIO05_ODRV_OFFSET 16
|
|
#define GPIO05_ODRV_MASK 0x00010000
|
|
#define GPIO05_IINV_OFFSET 15
|
|
#define GPIO05_IINV_MASK 0x00008000
|
|
#define GPIO05_OINV_OFFSET 14
|
|
#define GPIO05_OINV_MASK 0x00004000
|
|
#define GPIO05_OPOS_OFFSET 13
|
|
#define GPIO05_OPOS_MASK 0x00002000
|
|
#define GPIO05_ONEG_OFFSET 12
|
|
#define GPIO05_ONEG_MASK 0x00001000
|
|
#define GPIO05_IPOS_OFFSET 11
|
|
#define GPIO05_IPOS_MASK 0x00000800
|
|
#define GPIO05_INEG_OFFSET 10
|
|
#define GPIO05_INEG_MASK 0x00000400
|
|
#define GPIO05_ORE_OFFSET 9
|
|
#define GPIO05_ORE_MASK 0x00000200
|
|
#define GPIO05_IRE_OFFSET 8
|
|
#define GPIO05_IRE_MASK 0x00000100
|
|
#define GPIO05_FUNC_WPU_OFFSET 7
|
|
#define GPIO05_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO05_FUNC_WPD_OFFSET 6
|
|
#define GPIO05_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO05_FUNC_SEL_OFFSET 4
|
|
#define GPIO05_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO05_MCU_WPU_OFFSET 3
|
|
#define GPIO05_MCU_WPU_MASK 0x00000008
|
|
#define GPIO05_MCU_WPD_OFFSET 2
|
|
#define GPIO05_MCU_WPD_MASK 0x00000004
|
|
#define GPIO05_MCU_IE_OFFSET 1
|
|
#define GPIO05_MCU_IE_MASK 0x00000002
|
|
#define GPIO05_MCU_OE_OFFSET 0
|
|
#define GPIO05_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO06_PIN_CFG_ADDR 0x3c
|
|
#define GPIO06_SEC_OFFSET 17
|
|
#define GPIO06_SEC_MASK 0x00020000
|
|
#define GPIO06_ODRV_OFFSET 16
|
|
#define GPIO06_ODRV_MASK 0x00010000
|
|
#define GPIO06_IINV_OFFSET 15
|
|
#define GPIO06_IINV_MASK 0x00008000
|
|
#define GPIO06_OINV_OFFSET 14
|
|
#define GPIO06_OINV_MASK 0x00004000
|
|
#define GPIO06_OPOS_OFFSET 13
|
|
#define GPIO06_OPOS_MASK 0x00002000
|
|
#define GPIO06_ONEG_OFFSET 12
|
|
#define GPIO06_ONEG_MASK 0x00001000
|
|
#define GPIO06_IPOS_OFFSET 11
|
|
#define GPIO06_IPOS_MASK 0x00000800
|
|
#define GPIO06_INEG_OFFSET 10
|
|
#define GPIO06_INEG_MASK 0x00000400
|
|
#define GPIO06_ORE_OFFSET 9
|
|
#define GPIO06_ORE_MASK 0x00000200
|
|
#define GPIO06_IRE_OFFSET 8
|
|
#define GPIO06_IRE_MASK 0x00000100
|
|
#define GPIO06_FUNC_WPU_OFFSET 7
|
|
#define GPIO06_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO06_FUNC_WPD_OFFSET 6
|
|
#define GPIO06_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO06_FUNC_SEL_OFFSET 4
|
|
#define GPIO06_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO06_MCU_WPU_OFFSET 3
|
|
#define GPIO06_MCU_WPU_MASK 0x00000008
|
|
#define GPIO06_MCU_WPD_OFFSET 2
|
|
#define GPIO06_MCU_WPD_MASK 0x00000004
|
|
#define GPIO06_MCU_IE_OFFSET 1
|
|
#define GPIO06_MCU_IE_MASK 0x00000002
|
|
#define GPIO06_MCU_OE_OFFSET 0
|
|
#define GPIO06_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO07_PIN_CFG_ADDR 0x40
|
|
#define GPIO07_SEC_OFFSET 17
|
|
#define GPIO07_SEC_MASK 0x00020000
|
|
#define GPIO07_ODRV_OFFSET 16
|
|
#define GPIO07_ODRV_MASK 0x00010000
|
|
#define GPIO07_IINV_OFFSET 15
|
|
#define GPIO07_IINV_MASK 0x00008000
|
|
#define GPIO07_OINV_OFFSET 14
|
|
#define GPIO07_OINV_MASK 0x00004000
|
|
#define GPIO07_OPOS_OFFSET 13
|
|
#define GPIO07_OPOS_MASK 0x00002000
|
|
#define GPIO07_ONEG_OFFSET 12
|
|
#define GPIO07_ONEG_MASK 0x00001000
|
|
#define GPIO07_IPOS_OFFSET 11
|
|
#define GPIO07_IPOS_MASK 0x00000800
|
|
#define GPIO07_INEG_OFFSET 10
|
|
#define GPIO07_INEG_MASK 0x00000400
|
|
#define GPIO07_ORE_OFFSET 9
|
|
#define GPIO07_ORE_MASK 0x00000200
|
|
#define GPIO07_IRE_OFFSET 8
|
|
#define GPIO07_IRE_MASK 0x00000100
|
|
#define GPIO07_FUNC_WPU_OFFSET 7
|
|
#define GPIO07_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO07_FUNC_WPD_OFFSET 6
|
|
#define GPIO07_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO07_FUNC_SEL_OFFSET 4
|
|
#define GPIO07_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO07_MCU_WPU_OFFSET 3
|
|
#define GPIO07_MCU_WPU_MASK 0x00000008
|
|
#define GPIO07_MCU_WPD_OFFSET 2
|
|
#define GPIO07_MCU_WPD_MASK 0x00000004
|
|
#define GPIO07_MCU_IE_OFFSET 1
|
|
#define GPIO07_MCU_IE_MASK 0x00000002
|
|
#define GPIO07_MCU_OE_OFFSET 0
|
|
#define GPIO07_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO08_PIN_CFG_ADDR 0x44
|
|
#define GPIO08_SEC_OFFSET 17
|
|
#define GPIO08_SEC_MASK 0x00020000
|
|
#define GPIO08_ODRV_OFFSET 16
|
|
#define GPIO08_ODRV_MASK 0x00010000
|
|
#define GPIO08_IINV_OFFSET 15
|
|
#define GPIO08_IINV_MASK 0x00008000
|
|
#define GPIO08_OINV_OFFSET 14
|
|
#define GPIO08_OINV_MASK 0x00004000
|
|
#define GPIO08_OPOS_OFFSET 13
|
|
#define GPIO08_OPOS_MASK 0x00002000
|
|
#define GPIO08_ONEG_OFFSET 12
|
|
#define GPIO08_ONEG_MASK 0x00001000
|
|
#define GPIO08_IPOS_OFFSET 11
|
|
#define GPIO08_IPOS_MASK 0x00000800
|
|
#define GPIO08_INEG_OFFSET 10
|
|
#define GPIO08_INEG_MASK 0x00000400
|
|
#define GPIO08_ORE_OFFSET 9
|
|
#define GPIO08_ORE_MASK 0x00000200
|
|
#define GPIO08_IRE_OFFSET 8
|
|
#define GPIO08_IRE_MASK 0x00000100
|
|
#define GPIO08_FUNC_WPU_OFFSET 7
|
|
#define GPIO08_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO08_FUNC_WPD_OFFSET 6
|
|
#define GPIO08_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO08_FUNC_SEL_OFFSET 4
|
|
#define GPIO08_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO08_MCU_WPU_OFFSET 3
|
|
#define GPIO08_MCU_WPU_MASK 0x00000008
|
|
#define GPIO08_MCU_WPD_OFFSET 2
|
|
#define GPIO08_MCU_WPD_MASK 0x00000004
|
|
#define GPIO08_MCU_IE_OFFSET 1
|
|
#define GPIO08_MCU_IE_MASK 0x00000002
|
|
#define GPIO08_MCU_OE_OFFSET 0
|
|
#define GPIO08_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO09_PIN_CFG_ADDR 0x48
|
|
#define GPIO09_SEC_OFFSET 17
|
|
#define GPIO09_SEC_MASK 0x00020000
|
|
#define GPIO09_ODRV_OFFSET 16
|
|
#define GPIO09_ODRV_MASK 0x00010000
|
|
#define GPIO09_IINV_OFFSET 15
|
|
#define GPIO09_IINV_MASK 0x00008000
|
|
#define GPIO09_OINV_OFFSET 14
|
|
#define GPIO09_OINV_MASK 0x00004000
|
|
#define GPIO09_OPOS_OFFSET 13
|
|
#define GPIO09_OPOS_MASK 0x00002000
|
|
#define GPIO09_ONEG_OFFSET 12
|
|
#define GPIO09_ONEG_MASK 0x00001000
|
|
#define GPIO09_IPOS_OFFSET 11
|
|
#define GPIO09_IPOS_MASK 0x00000800
|
|
#define GPIO09_INEG_OFFSET 10
|
|
#define GPIO09_INEG_MASK 0x00000400
|
|
#define GPIO09_ORE_OFFSET 9
|
|
#define GPIO09_ORE_MASK 0x00000200
|
|
#define GPIO09_IRE_OFFSET 8
|
|
#define GPIO09_IRE_MASK 0x00000100
|
|
#define GPIO09_FUNC_WPU_OFFSET 7
|
|
#define GPIO09_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO09_FUNC_WPD_OFFSET 6
|
|
#define GPIO09_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO09_FUNC_SEL_OFFSET 4
|
|
#define GPIO09_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO09_MCU_WPU_OFFSET 3
|
|
#define GPIO09_MCU_WPU_MASK 0x00000008
|
|
#define GPIO09_MCU_WPD_OFFSET 2
|
|
#define GPIO09_MCU_WPD_MASK 0x00000004
|
|
#define GPIO09_MCU_IE_OFFSET 1
|
|
#define GPIO09_MCU_IE_MASK 0x00000002
|
|
#define GPIO09_MCU_OE_OFFSET 0
|
|
#define GPIO09_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO10_PIN_CFG_ADDR 0x4c
|
|
#define GPIO10_SEC_OFFSET 17
|
|
#define GPIO10_SEC_MASK 0x00020000
|
|
#define GPIO10_ODRV_OFFSET 16
|
|
#define GPIO10_ODRV_MASK 0x00010000
|
|
#define GPIO10_IINV_OFFSET 15
|
|
#define GPIO10_IINV_MASK 0x00008000
|
|
#define GPIO10_OINV_OFFSET 14
|
|
#define GPIO10_OINV_MASK 0x00004000
|
|
#define GPIO10_OPOS_OFFSET 13
|
|
#define GPIO10_OPOS_MASK 0x00002000
|
|
#define GPIO10_ONEG_OFFSET 12
|
|
#define GPIO10_ONEG_MASK 0x00001000
|
|
#define GPIO10_IPOS_OFFSET 11
|
|
#define GPIO10_IPOS_MASK 0x00000800
|
|
#define GPIO10_INEG_OFFSET 10
|
|
#define GPIO10_INEG_MASK 0x00000400
|
|
#define GPIO10_ORE_OFFSET 9
|
|
#define GPIO10_ORE_MASK 0x00000200
|
|
#define GPIO10_IRE_OFFSET 8
|
|
#define GPIO10_IRE_MASK 0x00000100
|
|
#define GPIO10_FUNC_WPU_OFFSET 7
|
|
#define GPIO10_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO10_FUNC_WPD_OFFSET 6
|
|
#define GPIO10_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO10_FUNC_SEL_OFFSET 4
|
|
#define GPIO10_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO10_MCU_WPU_OFFSET 3
|
|
#define GPIO10_MCU_WPU_MASK 0x00000008
|
|
#define GPIO10_MCU_WPD_OFFSET 2
|
|
#define GPIO10_MCU_WPD_MASK 0x00000004
|
|
#define GPIO10_MCU_IE_OFFSET 1
|
|
#define GPIO10_MCU_IE_MASK 0x00000002
|
|
#define GPIO10_MCU_OE_OFFSET 0
|
|
#define GPIO10_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO11_PIN_CFG_ADDR 0x50
|
|
#define GPIO11_SEC_OFFSET 17
|
|
#define GPIO11_SEC_MASK 0x00020000
|
|
#define GPIO11_ODRV_OFFSET 16
|
|
#define GPIO11_ODRV_MASK 0x00010000
|
|
#define GPIO11_IINV_OFFSET 15
|
|
#define GPIO11_IINV_MASK 0x00008000
|
|
#define GPIO11_OINV_OFFSET 14
|
|
#define GPIO11_OINV_MASK 0x00004000
|
|
#define GPIO11_OPOS_OFFSET 13
|
|
#define GPIO11_OPOS_MASK 0x00002000
|
|
#define GPIO11_ONEG_OFFSET 12
|
|
#define GPIO11_ONEG_MASK 0x00001000
|
|
#define GPIO11_IPOS_OFFSET 11
|
|
#define GPIO11_IPOS_MASK 0x00000800
|
|
#define GPIO11_INEG_OFFSET 10
|
|
#define GPIO11_INEG_MASK 0x00000400
|
|
#define GPIO11_ORE_OFFSET 9
|
|
#define GPIO11_ORE_MASK 0x00000200
|
|
#define GPIO11_IRE_OFFSET 8
|
|
#define GPIO11_IRE_MASK 0x00000100
|
|
#define GPIO11_FUNC_WPU_OFFSET 7
|
|
#define GPIO11_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO11_FUNC_WPD_OFFSET 6
|
|
#define GPIO11_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO11_FUNC_SEL_OFFSET 4
|
|
#define GPIO11_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO11_MCU_WPU_OFFSET 3
|
|
#define GPIO11_MCU_WPU_MASK 0x00000008
|
|
#define GPIO11_MCU_WPD_OFFSET 2
|
|
#define GPIO11_MCU_WPD_MASK 0x00000004
|
|
#define GPIO11_MCU_IE_OFFSET 1
|
|
#define GPIO11_MCU_IE_MASK 0x00000002
|
|
#define GPIO11_MCU_OE_OFFSET 0
|
|
#define GPIO11_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO12_PIN_CFG_ADDR 0x54
|
|
#define GPIO12_SEC_OFFSET 17
|
|
#define GPIO12_SEC_MASK 0x00020000
|
|
#define GPIO12_ODRV_OFFSET 16
|
|
#define GPIO12_ODRV_MASK 0x00010000
|
|
#define GPIO12_IINV_OFFSET 15
|
|
#define GPIO12_IINV_MASK 0x00008000
|
|
#define GPIO12_OINV_OFFSET 14
|
|
#define GPIO12_OINV_MASK 0x00004000
|
|
#define GPIO12_OPOS_OFFSET 13
|
|
#define GPIO12_OPOS_MASK 0x00002000
|
|
#define GPIO12_ONEG_OFFSET 12
|
|
#define GPIO12_ONEG_MASK 0x00001000
|
|
#define GPIO12_IPOS_OFFSET 11
|
|
#define GPIO12_IPOS_MASK 0x00000800
|
|
#define GPIO12_INEG_OFFSET 10
|
|
#define GPIO12_INEG_MASK 0x00000400
|
|
#define GPIO12_ORE_OFFSET 9
|
|
#define GPIO12_ORE_MASK 0x00000200
|
|
#define GPIO12_IRE_OFFSET 8
|
|
#define GPIO12_IRE_MASK 0x00000100
|
|
#define GPIO12_FUNC_WPU_OFFSET 7
|
|
#define GPIO12_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO12_FUNC_WPD_OFFSET 6
|
|
#define GPIO12_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO12_FUNC_SEL_OFFSET 4
|
|
#define GPIO12_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO12_MCU_WPU_OFFSET 3
|
|
#define GPIO12_MCU_WPU_MASK 0x00000008
|
|
#define GPIO12_MCU_WPD_OFFSET 2
|
|
#define GPIO12_MCU_WPD_MASK 0x00000004
|
|
#define GPIO12_MCU_IE_OFFSET 1
|
|
#define GPIO12_MCU_IE_MASK 0x00000002
|
|
#define GPIO12_MCU_OE_OFFSET 0
|
|
#define GPIO12_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO13_PIN_CFG_ADDR 0x58
|
|
#define GPIO13_SEC_OFFSET 17
|
|
#define GPIO13_SEC_MASK 0x00020000
|
|
#define GPIO13_ODRV_OFFSET 16
|
|
#define GPIO13_ODRV_MASK 0x00010000
|
|
#define GPIO13_IINV_OFFSET 15
|
|
#define GPIO13_IINV_MASK 0x00008000
|
|
#define GPIO13_OINV_OFFSET 14
|
|
#define GPIO13_OINV_MASK 0x00004000
|
|
#define GPIO13_OPOS_OFFSET 13
|
|
#define GPIO13_OPOS_MASK 0x00002000
|
|
#define GPIO13_ONEG_OFFSET 12
|
|
#define GPIO13_ONEG_MASK 0x00001000
|
|
#define GPIO13_IPOS_OFFSET 11
|
|
#define GPIO13_IPOS_MASK 0x00000800
|
|
#define GPIO13_INEG_OFFSET 10
|
|
#define GPIO13_INEG_MASK 0x00000400
|
|
#define GPIO13_ORE_OFFSET 9
|
|
#define GPIO13_ORE_MASK 0x00000200
|
|
#define GPIO13_IRE_OFFSET 8
|
|
#define GPIO13_IRE_MASK 0x00000100
|
|
#define GPIO13_FUNC_WPU_OFFSET 7
|
|
#define GPIO13_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO13_FUNC_WPD_OFFSET 6
|
|
#define GPIO13_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO13_FUNC_SEL_OFFSET 4
|
|
#define GPIO13_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO13_MCU_WPU_OFFSET 3
|
|
#define GPIO13_MCU_WPU_MASK 0x00000008
|
|
#define GPIO13_MCU_WPD_OFFSET 2
|
|
#define GPIO13_MCU_WPD_MASK 0x00000004
|
|
#define GPIO13_MCU_IE_OFFSET 1
|
|
#define GPIO13_MCU_IE_MASK 0x00000002
|
|
#define GPIO13_MCU_OE_OFFSET 0
|
|
#define GPIO13_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO14_PIN_CFG_ADDR 0x5c
|
|
#define GPIO14_SEC_OFFSET 17
|
|
#define GPIO14_SEC_MASK 0x00020000
|
|
#define GPIO14_ODRV_OFFSET 16
|
|
#define GPIO14_ODRV_MASK 0x00010000
|
|
#define GPIO14_IINV_OFFSET 15
|
|
#define GPIO14_IINV_MASK 0x00008000
|
|
#define GPIO14_OINV_OFFSET 14
|
|
#define GPIO14_OINV_MASK 0x00004000
|
|
#define GPIO14_OPOS_OFFSET 13
|
|
#define GPIO14_OPOS_MASK 0x00002000
|
|
#define GPIO14_ONEG_OFFSET 12
|
|
#define GPIO14_ONEG_MASK 0x00001000
|
|
#define GPIO14_IPOS_OFFSET 11
|
|
#define GPIO14_IPOS_MASK 0x00000800
|
|
#define GPIO14_INEG_OFFSET 10
|
|
#define GPIO14_INEG_MASK 0x00000400
|
|
#define GPIO14_ORE_OFFSET 9
|
|
#define GPIO14_ORE_MASK 0x00000200
|
|
#define GPIO14_IRE_OFFSET 8
|
|
#define GPIO14_IRE_MASK 0x00000100
|
|
#define GPIO14_FUNC_WPU_OFFSET 7
|
|
#define GPIO14_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO14_FUNC_WPD_OFFSET 6
|
|
#define GPIO14_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO14_FUNC_SEL_OFFSET 4
|
|
#define GPIO14_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO14_MCU_WPU_OFFSET 3
|
|
#define GPIO14_MCU_WPU_MASK 0x00000008
|
|
#define GPIO14_MCU_WPD_OFFSET 2
|
|
#define GPIO14_MCU_WPD_MASK 0x00000004
|
|
#define GPIO14_MCU_IE_OFFSET 1
|
|
#define GPIO14_MCU_IE_MASK 0x00000002
|
|
#define GPIO14_MCU_OE_OFFSET 0
|
|
#define GPIO14_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO15_PIN_CFG_ADDR 0x60
|
|
#define GPIO15_SEC_OFFSET 17
|
|
#define GPIO15_SEC_MASK 0x00020000
|
|
#define GPIO15_ODRV_OFFSET 16
|
|
#define GPIO15_ODRV_MASK 0x00010000
|
|
#define GPIO15_IINV_OFFSET 15
|
|
#define GPIO15_IINV_MASK 0x00008000
|
|
#define GPIO15_OINV_OFFSET 14
|
|
#define GPIO15_OINV_MASK 0x00004000
|
|
#define GPIO15_OPOS_OFFSET 13
|
|
#define GPIO15_OPOS_MASK 0x00002000
|
|
#define GPIO15_ONEG_OFFSET 12
|
|
#define GPIO15_ONEG_MASK 0x00001000
|
|
#define GPIO15_IPOS_OFFSET 11
|
|
#define GPIO15_IPOS_MASK 0x00000800
|
|
#define GPIO15_INEG_OFFSET 10
|
|
#define GPIO15_INEG_MASK 0x00000400
|
|
#define GPIO15_ORE_OFFSET 9
|
|
#define GPIO15_ORE_MASK 0x00000200
|
|
#define GPIO15_IRE_OFFSET 8
|
|
#define GPIO15_IRE_MASK 0x00000100
|
|
#define GPIO15_FUNC_WPU_OFFSET 7
|
|
#define GPIO15_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO15_FUNC_WPD_OFFSET 6
|
|
#define GPIO15_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO15_FUNC_SEL_OFFSET 4
|
|
#define GPIO15_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO15_MCU_WPU_OFFSET 3
|
|
#define GPIO15_MCU_WPU_MASK 0x00000008
|
|
#define GPIO15_MCU_WPD_OFFSET 2
|
|
#define GPIO15_MCU_WPD_MASK 0x00000004
|
|
#define GPIO15_MCU_IE_OFFSET 1
|
|
#define GPIO15_MCU_IE_MASK 0x00000002
|
|
#define GPIO15_MCU_OE_OFFSET 0
|
|
#define GPIO15_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO16_PIN_CFG_ADDR 0x64
|
|
#define GPIO16_SEC_OFFSET 17
|
|
#define GPIO16_SEC_MASK 0x00020000
|
|
#define GPIO16_ODRV_OFFSET 16
|
|
#define GPIO16_ODRV_MASK 0x00010000
|
|
#define GPIO16_IINV_OFFSET 15
|
|
#define GPIO16_IINV_MASK 0x00008000
|
|
#define GPIO16_OINV_OFFSET 14
|
|
#define GPIO16_OINV_MASK 0x00004000
|
|
#define GPIO16_OPOS_OFFSET 13
|
|
#define GPIO16_OPOS_MASK 0x00002000
|
|
#define GPIO16_ONEG_OFFSET 12
|
|
#define GPIO16_ONEG_MASK 0x00001000
|
|
#define GPIO16_IPOS_OFFSET 11
|
|
#define GPIO16_IPOS_MASK 0x00000800
|
|
#define GPIO16_INEG_OFFSET 10
|
|
#define GPIO16_INEG_MASK 0x00000400
|
|
#define GPIO16_ORE_OFFSET 9
|
|
#define GPIO16_ORE_MASK 0x00000200
|
|
#define GPIO16_IRE_OFFSET 8
|
|
#define GPIO16_IRE_MASK 0x00000100
|
|
#define GPIO16_FUNC_WPU_OFFSET 7
|
|
#define GPIO16_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO16_FUNC_WPD_OFFSET 6
|
|
#define GPIO16_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO16_FUNC_SEL_OFFSET 4
|
|
#define GPIO16_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO16_MCU_WPU_OFFSET 3
|
|
#define GPIO16_MCU_WPU_MASK 0x00000008
|
|
#define GPIO16_MCU_WPD_OFFSET 2
|
|
#define GPIO16_MCU_WPD_MASK 0x00000004
|
|
#define GPIO16_MCU_IE_OFFSET 1
|
|
#define GPIO16_MCU_IE_MASK 0x00000002
|
|
#define GPIO16_MCU_OE_OFFSET 0
|
|
#define GPIO16_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO17_PIN_CFG_ADDR 0x68
|
|
#define GPIO17_SEC_OFFSET 17
|
|
#define GPIO17_SEC_MASK 0x00020000
|
|
#define GPIO17_ODRV_OFFSET 16
|
|
#define GPIO17_ODRV_MASK 0x00010000
|
|
#define GPIO17_IINV_OFFSET 15
|
|
#define GPIO17_IINV_MASK 0x00008000
|
|
#define GPIO17_OINV_OFFSET 14
|
|
#define GPIO17_OINV_MASK 0x00004000
|
|
#define GPIO17_OPOS_OFFSET 13
|
|
#define GPIO17_OPOS_MASK 0x00002000
|
|
#define GPIO17_ONEG_OFFSET 12
|
|
#define GPIO17_ONEG_MASK 0x00001000
|
|
#define GPIO17_IPOS_OFFSET 11
|
|
#define GPIO17_IPOS_MASK 0x00000800
|
|
#define GPIO17_INEG_OFFSET 10
|
|
#define GPIO17_INEG_MASK 0x00000400
|
|
#define GPIO17_ORE_OFFSET 9
|
|
#define GPIO17_ORE_MASK 0x00000200
|
|
#define GPIO17_IRE_OFFSET 8
|
|
#define GPIO17_IRE_MASK 0x00000100
|
|
#define GPIO17_FUNC_WPU_OFFSET 7
|
|
#define GPIO17_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO17_FUNC_WPD_OFFSET 6
|
|
#define GPIO17_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO17_FUNC_SEL_OFFSET 4
|
|
#define GPIO17_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO17_MCU_WPU_OFFSET 3
|
|
#define GPIO17_MCU_WPU_MASK 0x00000008
|
|
#define GPIO17_MCU_WPD_OFFSET 2
|
|
#define GPIO17_MCU_WPD_MASK 0x00000004
|
|
#define GPIO17_MCU_IE_OFFSET 1
|
|
#define GPIO17_MCU_IE_MASK 0x00000002
|
|
#define GPIO17_MCU_OE_OFFSET 0
|
|
#define GPIO17_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO18_PIN_CFG_ADDR 0x6c
|
|
#define GPIO18_SEC_OFFSET 17
|
|
#define GPIO18_SEC_MASK 0x00020000
|
|
#define GPIO18_ODRV_OFFSET 16
|
|
#define GPIO18_ODRV_MASK 0x00010000
|
|
#define GPIO18_IINV_OFFSET 15
|
|
#define GPIO18_IINV_MASK 0x00008000
|
|
#define GPIO18_OINV_OFFSET 14
|
|
#define GPIO18_OINV_MASK 0x00004000
|
|
#define GPIO18_OPOS_OFFSET 13
|
|
#define GPIO18_OPOS_MASK 0x00002000
|
|
#define GPIO18_ONEG_OFFSET 12
|
|
#define GPIO18_ONEG_MASK 0x00001000
|
|
#define GPIO18_IPOS_OFFSET 11
|
|
#define GPIO18_IPOS_MASK 0x00000800
|
|
#define GPIO18_INEG_OFFSET 10
|
|
#define GPIO18_INEG_MASK 0x00000400
|
|
#define GPIO18_ORE_OFFSET 9
|
|
#define GPIO18_ORE_MASK 0x00000200
|
|
#define GPIO18_IRE_OFFSET 8
|
|
#define GPIO18_IRE_MASK 0x00000100
|
|
#define GPIO18_FUNC_WPU_OFFSET 7
|
|
#define GPIO18_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO18_FUNC_WPD_OFFSET 6
|
|
#define GPIO18_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO18_FUNC_SEL_OFFSET 4
|
|
#define GPIO18_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO18_MCU_WPU_OFFSET 3
|
|
#define GPIO18_MCU_WPU_MASK 0x00000008
|
|
#define GPIO18_MCU_WPD_OFFSET 2
|
|
#define GPIO18_MCU_WPD_MASK 0x00000004
|
|
#define GPIO18_MCU_IE_OFFSET 1
|
|
#define GPIO18_MCU_IE_MASK 0x00000002
|
|
#define GPIO18_MCU_OE_OFFSET 0
|
|
#define GPIO18_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO19_PIN_CFG_ADDR 0x70
|
|
#define GPIO19_SEC_OFFSET 17
|
|
#define GPIO19_SEC_MASK 0x00020000
|
|
#define GPIO19_ODRV_OFFSET 16
|
|
#define GPIO19_ODRV_MASK 0x00010000
|
|
#define GPIO19_IINV_OFFSET 15
|
|
#define GPIO19_IINV_MASK 0x00008000
|
|
#define GPIO19_OINV_OFFSET 14
|
|
#define GPIO19_OINV_MASK 0x00004000
|
|
#define GPIO19_OPOS_OFFSET 13
|
|
#define GPIO19_OPOS_MASK 0x00002000
|
|
#define GPIO19_ONEG_OFFSET 12
|
|
#define GPIO19_ONEG_MASK 0x00001000
|
|
#define GPIO19_IPOS_OFFSET 11
|
|
#define GPIO19_IPOS_MASK 0x00000800
|
|
#define GPIO19_INEG_OFFSET 10
|
|
#define GPIO19_INEG_MASK 0x00000400
|
|
#define GPIO19_ORE_OFFSET 9
|
|
#define GPIO19_ORE_MASK 0x00000200
|
|
#define GPIO19_IRE_OFFSET 8
|
|
#define GPIO19_IRE_MASK 0x00000100
|
|
#define GPIO19_FUNC_WPU_OFFSET 7
|
|
#define GPIO19_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO19_FUNC_WPD_OFFSET 6
|
|
#define GPIO19_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO19_FUNC_SEL_OFFSET 4
|
|
#define GPIO19_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO19_MCU_WPU_OFFSET 3
|
|
#define GPIO19_MCU_WPU_MASK 0x00000008
|
|
#define GPIO19_MCU_WPD_OFFSET 2
|
|
#define GPIO19_MCU_WPD_MASK 0x00000004
|
|
#define GPIO19_MCU_IE_OFFSET 1
|
|
#define GPIO19_MCU_IE_MASK 0x00000002
|
|
#define GPIO19_MCU_OE_OFFSET 0
|
|
#define GPIO19_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO20_PIN_CFG_ADDR 0x74
|
|
#define GPIO20_SEC_OFFSET 17
|
|
#define GPIO20_SEC_MASK 0x00020000
|
|
#define GPIO20_ODRV_OFFSET 16
|
|
#define GPIO20_ODRV_MASK 0x00010000
|
|
#define GPIO20_IINV_OFFSET 15
|
|
#define GPIO20_IINV_MASK 0x00008000
|
|
#define GPIO20_OINV_OFFSET 14
|
|
#define GPIO20_OINV_MASK 0x00004000
|
|
#define GPIO20_OPOS_OFFSET 13
|
|
#define GPIO20_OPOS_MASK 0x00002000
|
|
#define GPIO20_ONEG_OFFSET 12
|
|
#define GPIO20_ONEG_MASK 0x00001000
|
|
#define GPIO20_IPOS_OFFSET 11
|
|
#define GPIO20_IPOS_MASK 0x00000800
|
|
#define GPIO20_INEG_OFFSET 10
|
|
#define GPIO20_INEG_MASK 0x00000400
|
|
#define GPIO20_ORE_OFFSET 9
|
|
#define GPIO20_ORE_MASK 0x00000200
|
|
#define GPIO20_IRE_OFFSET 8
|
|
#define GPIO20_IRE_MASK 0x00000100
|
|
#define GPIO20_FUNC_WPU_OFFSET 7
|
|
#define GPIO20_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO20_FUNC_WPD_OFFSET 6
|
|
#define GPIO20_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO20_FUNC_SEL_OFFSET 4
|
|
#define GPIO20_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO20_MCU_WPU_OFFSET 3
|
|
#define GPIO20_MCU_WPU_MASK 0x00000008
|
|
#define GPIO20_MCU_WPD_OFFSET 2
|
|
#define GPIO20_MCU_WPD_MASK 0x00000004
|
|
#define GPIO20_MCU_IE_OFFSET 1
|
|
#define GPIO20_MCU_IE_MASK 0x00000002
|
|
#define GPIO20_MCU_OE_OFFSET 0
|
|
#define GPIO20_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO21_PIN_CFG_ADDR 0x78
|
|
#define GPIO21_SEC_OFFSET 17
|
|
#define GPIO21_SEC_MASK 0x00020000
|
|
#define GPIO21_ODRV_OFFSET 16
|
|
#define GPIO21_ODRV_MASK 0x00010000
|
|
#define GPIO21_IINV_OFFSET 15
|
|
#define GPIO21_IINV_MASK 0x00008000
|
|
#define GPIO21_OINV_OFFSET 14
|
|
#define GPIO21_OINV_MASK 0x00004000
|
|
#define GPIO21_OPOS_OFFSET 13
|
|
#define GPIO21_OPOS_MASK 0x00002000
|
|
#define GPIO21_ONEG_OFFSET 12
|
|
#define GPIO21_ONEG_MASK 0x00001000
|
|
#define GPIO21_IPOS_OFFSET 11
|
|
#define GPIO21_IPOS_MASK 0x00000800
|
|
#define GPIO21_INEG_OFFSET 10
|
|
#define GPIO21_INEG_MASK 0x00000400
|
|
#define GPIO21_ORE_OFFSET 9
|
|
#define GPIO21_ORE_MASK 0x00000200
|
|
#define GPIO21_IRE_OFFSET 8
|
|
#define GPIO21_IRE_MASK 0x00000100
|
|
#define GPIO21_FUNC_WPU_OFFSET 7
|
|
#define GPIO21_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO21_FUNC_WPD_OFFSET 6
|
|
#define GPIO21_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO21_FUNC_SEL_OFFSET 4
|
|
#define GPIO21_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO21_MCU_WPU_OFFSET 3
|
|
#define GPIO21_MCU_WPU_MASK 0x00000008
|
|
#define GPIO21_MCU_WPD_OFFSET 2
|
|
#define GPIO21_MCU_WPD_MASK 0x00000004
|
|
#define GPIO21_MCU_IE_OFFSET 1
|
|
#define GPIO21_MCU_IE_MASK 0x00000002
|
|
#define GPIO21_MCU_OE_OFFSET 0
|
|
#define GPIO21_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO22_PIN_CFG_ADDR 0x7c
|
|
#define GPIO22_SEC_OFFSET 17
|
|
#define GPIO22_SEC_MASK 0x00020000
|
|
#define GPIO22_ODRV_OFFSET 16
|
|
#define GPIO22_ODRV_MASK 0x00010000
|
|
#define GPIO22_IINV_OFFSET 15
|
|
#define GPIO22_IINV_MASK 0x00008000
|
|
#define GPIO22_OINV_OFFSET 14
|
|
#define GPIO22_OINV_MASK 0x00004000
|
|
#define GPIO22_OPOS_OFFSET 13
|
|
#define GPIO22_OPOS_MASK 0x00002000
|
|
#define GPIO22_ONEG_OFFSET 12
|
|
#define GPIO22_ONEG_MASK 0x00001000
|
|
#define GPIO22_IPOS_OFFSET 11
|
|
#define GPIO22_IPOS_MASK 0x00000800
|
|
#define GPIO22_INEG_OFFSET 10
|
|
#define GPIO22_INEG_MASK 0x00000400
|
|
#define GPIO22_ORE_OFFSET 9
|
|
#define GPIO22_ORE_MASK 0x00000200
|
|
#define GPIO22_IRE_OFFSET 8
|
|
#define GPIO22_IRE_MASK 0x00000100
|
|
#define GPIO22_FUNC_WPU_OFFSET 7
|
|
#define GPIO22_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO22_FUNC_WPD_OFFSET 6
|
|
#define GPIO22_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO22_FUNC_SEL_OFFSET 4
|
|
#define GPIO22_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO22_MCU_WPU_OFFSET 3
|
|
#define GPIO22_MCU_WPU_MASK 0x00000008
|
|
#define GPIO22_MCU_WPD_OFFSET 2
|
|
#define GPIO22_MCU_WPD_MASK 0x00000004
|
|
#define GPIO22_MCU_IE_OFFSET 1
|
|
#define GPIO22_MCU_IE_MASK 0x00000002
|
|
#define GPIO22_MCU_OE_OFFSET 0
|
|
#define GPIO22_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO23_PIN_CFG_ADDR 0x80
|
|
#define GPIO23_SEC_OFFSET 17
|
|
#define GPIO23_SEC_MASK 0x00020000
|
|
#define GPIO23_ODRV_OFFSET 16
|
|
#define GPIO23_ODRV_MASK 0x00010000
|
|
#define GPIO23_IINV_OFFSET 15
|
|
#define GPIO23_IINV_MASK 0x00008000
|
|
#define GPIO23_OINV_OFFSET 14
|
|
#define GPIO23_OINV_MASK 0x00004000
|
|
#define GPIO23_OPOS_OFFSET 13
|
|
#define GPIO23_OPOS_MASK 0x00002000
|
|
#define GPIO23_ONEG_OFFSET 12
|
|
#define GPIO23_ONEG_MASK 0x00001000
|
|
#define GPIO23_IPOS_OFFSET 11
|
|
#define GPIO23_IPOS_MASK 0x00000800
|
|
#define GPIO23_INEG_OFFSET 10
|
|
#define GPIO23_INEG_MASK 0x00000400
|
|
#define GPIO23_ORE_OFFSET 9
|
|
#define GPIO23_ORE_MASK 0x00000200
|
|
#define GPIO23_IRE_OFFSET 8
|
|
#define GPIO23_IRE_MASK 0x00000100
|
|
#define GPIO23_FUNC_WPU_OFFSET 7
|
|
#define GPIO23_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO23_FUNC_WPD_OFFSET 6
|
|
#define GPIO23_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO23_FUNC_SEL_OFFSET 4
|
|
#define GPIO23_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO23_MCU_WPU_OFFSET 3
|
|
#define GPIO23_MCU_WPU_MASK 0x00000008
|
|
#define GPIO23_MCU_WPD_OFFSET 2
|
|
#define GPIO23_MCU_WPD_MASK 0x00000004
|
|
#define GPIO23_MCU_IE_OFFSET 1
|
|
#define GPIO23_MCU_IE_MASK 0x00000002
|
|
#define GPIO23_MCU_OE_OFFSET 0
|
|
#define GPIO23_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO24_PIN_CFG_ADDR 0x84
|
|
#define GPIO24_SEC_OFFSET 17
|
|
#define GPIO24_SEC_MASK 0x00020000
|
|
#define GPIO24_ODRV_OFFSET 16
|
|
#define GPIO24_ODRV_MASK 0x00010000
|
|
#define GPIO24_IINV_OFFSET 15
|
|
#define GPIO24_IINV_MASK 0x00008000
|
|
#define GPIO24_OINV_OFFSET 14
|
|
#define GPIO24_OINV_MASK 0x00004000
|
|
#define GPIO24_OPOS_OFFSET 13
|
|
#define GPIO24_OPOS_MASK 0x00002000
|
|
#define GPIO24_ONEG_OFFSET 12
|
|
#define GPIO24_ONEG_MASK 0x00001000
|
|
#define GPIO24_IPOS_OFFSET 11
|
|
#define GPIO24_IPOS_MASK 0x00000800
|
|
#define GPIO24_INEG_OFFSET 10
|
|
#define GPIO24_INEG_MASK 0x00000400
|
|
#define GPIO24_ORE_OFFSET 9
|
|
#define GPIO24_ORE_MASK 0x00000200
|
|
#define GPIO24_IRE_OFFSET 8
|
|
#define GPIO24_IRE_MASK 0x00000100
|
|
#define GPIO24_FUNC_WPU_OFFSET 7
|
|
#define GPIO24_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO24_FUNC_WPD_OFFSET 6
|
|
#define GPIO24_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO24_FUNC_SEL_OFFSET 4
|
|
#define GPIO24_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO24_MCU_WPU_OFFSET 3
|
|
#define GPIO24_MCU_WPU_MASK 0x00000008
|
|
#define GPIO24_MCU_WPD_OFFSET 2
|
|
#define GPIO24_MCU_WPD_MASK 0x00000004
|
|
#define GPIO24_MCU_IE_OFFSET 1
|
|
#define GPIO24_MCU_IE_MASK 0x00000002
|
|
#define GPIO24_MCU_OE_OFFSET 0
|
|
#define GPIO24_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO25_PIN_CFG_ADDR 0x88
|
|
#define GPIO25_SEC_OFFSET 17
|
|
#define GPIO25_SEC_MASK 0x00020000
|
|
#define GPIO25_ODRV_OFFSET 16
|
|
#define GPIO25_ODRV_MASK 0x00010000
|
|
#define GPIO25_IINV_OFFSET 15
|
|
#define GPIO25_IINV_MASK 0x00008000
|
|
#define GPIO25_OINV_OFFSET 14
|
|
#define GPIO25_OINV_MASK 0x00004000
|
|
#define GPIO25_OPOS_OFFSET 13
|
|
#define GPIO25_OPOS_MASK 0x00002000
|
|
#define GPIO25_ONEG_OFFSET 12
|
|
#define GPIO25_ONEG_MASK 0x00001000
|
|
#define GPIO25_IPOS_OFFSET 11
|
|
#define GPIO25_IPOS_MASK 0x00000800
|
|
#define GPIO25_INEG_OFFSET 10
|
|
#define GPIO25_INEG_MASK 0x00000400
|
|
#define GPIO25_ORE_OFFSET 9
|
|
#define GPIO25_ORE_MASK 0x00000200
|
|
#define GPIO25_IRE_OFFSET 8
|
|
#define GPIO25_IRE_MASK 0x00000100
|
|
#define GPIO25_FUNC_WPU_OFFSET 7
|
|
#define GPIO25_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO25_FUNC_WPD_OFFSET 6
|
|
#define GPIO25_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO25_FUNC_SEL_OFFSET 4
|
|
#define GPIO25_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO25_MCU_WPU_OFFSET 3
|
|
#define GPIO25_MCU_WPU_MASK 0x00000008
|
|
#define GPIO25_MCU_WPD_OFFSET 2
|
|
#define GPIO25_MCU_WPD_MASK 0x00000004
|
|
#define GPIO25_MCU_IE_OFFSET 1
|
|
#define GPIO25_MCU_IE_MASK 0x00000002
|
|
#define GPIO25_MCU_OE_OFFSET 0
|
|
#define GPIO25_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO26_PIN_CFG_ADDR 0x8c
|
|
#define GPIO26_SEC_OFFSET 17
|
|
#define GPIO26_SEC_MASK 0x00020000
|
|
#define GPIO26_ODRV_OFFSET 16
|
|
#define GPIO26_ODRV_MASK 0x00010000
|
|
#define GPIO26_IINV_OFFSET 15
|
|
#define GPIO26_IINV_MASK 0x00008000
|
|
#define GPIO26_OINV_OFFSET 14
|
|
#define GPIO26_OINV_MASK 0x00004000
|
|
#define GPIO26_OPOS_OFFSET 13
|
|
#define GPIO26_OPOS_MASK 0x00002000
|
|
#define GPIO26_ONEG_OFFSET 12
|
|
#define GPIO26_ONEG_MASK 0x00001000
|
|
#define GPIO26_IPOS_OFFSET 11
|
|
#define GPIO26_IPOS_MASK 0x00000800
|
|
#define GPIO26_INEG_OFFSET 10
|
|
#define GPIO26_INEG_MASK 0x00000400
|
|
#define GPIO26_ORE_OFFSET 9
|
|
#define GPIO26_ORE_MASK 0x00000200
|
|
#define GPIO26_IRE_OFFSET 8
|
|
#define GPIO26_IRE_MASK 0x00000100
|
|
#define GPIO26_FUNC_WPU_OFFSET 7
|
|
#define GPIO26_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO26_FUNC_WPD_OFFSET 6
|
|
#define GPIO26_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO26_FUNC_SEL_OFFSET 4
|
|
#define GPIO26_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO26_MCU_WPU_OFFSET 3
|
|
#define GPIO26_MCU_WPU_MASK 0x00000008
|
|
#define GPIO26_MCU_WPD_OFFSET 2
|
|
#define GPIO26_MCU_WPD_MASK 0x00000004
|
|
#define GPIO26_MCU_IE_OFFSET 1
|
|
#define GPIO26_MCU_IE_MASK 0x00000002
|
|
#define GPIO26_MCU_OE_OFFSET 0
|
|
#define GPIO26_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO27_PIN_CFG_ADDR 0x90
|
|
#define GPIO27_SEC_OFFSET 17
|
|
#define GPIO27_SEC_MASK 0x00020000
|
|
#define GPIO27_ODRV_OFFSET 16
|
|
#define GPIO27_ODRV_MASK 0x00010000
|
|
#define GPIO27_IINV_OFFSET 15
|
|
#define GPIO27_IINV_MASK 0x00008000
|
|
#define GPIO27_OINV_OFFSET 14
|
|
#define GPIO27_OINV_MASK 0x00004000
|
|
#define GPIO27_OPOS_OFFSET 13
|
|
#define GPIO27_OPOS_MASK 0x00002000
|
|
#define GPIO27_ONEG_OFFSET 12
|
|
#define GPIO27_ONEG_MASK 0x00001000
|
|
#define GPIO27_IPOS_OFFSET 11
|
|
#define GPIO27_IPOS_MASK 0x00000800
|
|
#define GPIO27_INEG_OFFSET 10
|
|
#define GPIO27_INEG_MASK 0x00000400
|
|
#define GPIO27_ORE_OFFSET 9
|
|
#define GPIO27_ORE_MASK 0x00000200
|
|
#define GPIO27_IRE_OFFSET 8
|
|
#define GPIO27_IRE_MASK 0x00000100
|
|
#define GPIO27_FUNC_WPU_OFFSET 7
|
|
#define GPIO27_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO27_FUNC_WPD_OFFSET 6
|
|
#define GPIO27_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO27_FUNC_SEL_OFFSET 4
|
|
#define GPIO27_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO27_MCU_WPU_OFFSET 3
|
|
#define GPIO27_MCU_WPU_MASK 0x00000008
|
|
#define GPIO27_MCU_WPD_OFFSET 2
|
|
#define GPIO27_MCU_WPD_MASK 0x00000004
|
|
#define GPIO27_MCU_IE_OFFSET 1
|
|
#define GPIO27_MCU_IE_MASK 0x00000002
|
|
#define GPIO27_MCU_OE_OFFSET 0
|
|
#define GPIO27_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO28_PIN_CFG_ADDR 0x94
|
|
#define GPIO28_SEC_OFFSET 17
|
|
#define GPIO28_SEC_MASK 0x00020000
|
|
#define GPIO28_ODRV_OFFSET 16
|
|
#define GPIO28_ODRV_MASK 0x00010000
|
|
#define GPIO28_IINV_OFFSET 15
|
|
#define GPIO28_IINV_MASK 0x00008000
|
|
#define GPIO28_OINV_OFFSET 14
|
|
#define GPIO28_OINV_MASK 0x00004000
|
|
#define GPIO28_OPOS_OFFSET 13
|
|
#define GPIO28_OPOS_MASK 0x00002000
|
|
#define GPIO28_ONEG_OFFSET 12
|
|
#define GPIO28_ONEG_MASK 0x00001000
|
|
#define GPIO28_IPOS_OFFSET 11
|
|
#define GPIO28_IPOS_MASK 0x00000800
|
|
#define GPIO28_INEG_OFFSET 10
|
|
#define GPIO28_INEG_MASK 0x00000400
|
|
#define GPIO28_ORE_OFFSET 9
|
|
#define GPIO28_ORE_MASK 0x00000200
|
|
#define GPIO28_IRE_OFFSET 8
|
|
#define GPIO28_IRE_MASK 0x00000100
|
|
#define GPIO28_FUNC_WPU_OFFSET 7
|
|
#define GPIO28_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO28_FUNC_WPD_OFFSET 6
|
|
#define GPIO28_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO28_FUNC_SEL_OFFSET 4
|
|
#define GPIO28_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO28_MCU_WPU_OFFSET 3
|
|
#define GPIO28_MCU_WPU_MASK 0x00000008
|
|
#define GPIO28_MCU_WPD_OFFSET 2
|
|
#define GPIO28_MCU_WPD_MASK 0x00000004
|
|
#define GPIO28_MCU_IE_OFFSET 1
|
|
#define GPIO28_MCU_IE_MASK 0x00000002
|
|
#define GPIO28_MCU_OE_OFFSET 0
|
|
#define GPIO28_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO43_PIN_CFG_ADDR 0x98
|
|
#define GPIO43_SEC_OFFSET 17
|
|
#define GPIO43_SEC_MASK 0x00020000
|
|
#define GPIO43_ODRV_OFFSET 16
|
|
#define GPIO43_ODRV_MASK 0x00010000
|
|
#define GPIO43_IINV_OFFSET 15
|
|
#define GPIO43_IINV_MASK 0x00008000
|
|
#define GPIO43_OINV_OFFSET 14
|
|
#define GPIO43_OINV_MASK 0x00004000
|
|
#define GPIO43_OPOS_OFFSET 13
|
|
#define GPIO43_OPOS_MASK 0x00002000
|
|
#define GPIO43_ONEG_OFFSET 12
|
|
#define GPIO43_ONEG_MASK 0x00001000
|
|
#define GPIO43_IPOS_OFFSET 11
|
|
#define GPIO43_IPOS_MASK 0x00000800
|
|
#define GPIO43_INEG_OFFSET 10
|
|
#define GPIO43_INEG_MASK 0x00000400
|
|
#define GPIO43_ORE_OFFSET 9
|
|
#define GPIO43_ORE_MASK 0x00000200
|
|
#define GPIO43_IRE_OFFSET 8
|
|
#define GPIO43_IRE_MASK 0x00000100
|
|
#define GPIO43_FUNC_WPU_OFFSET 7
|
|
#define GPIO43_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO43_FUNC_WPD_OFFSET 6
|
|
#define GPIO43_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO43_FUNC_SEL_OFFSET 4
|
|
#define GPIO43_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO43_MCU_WPU_OFFSET 3
|
|
#define GPIO43_MCU_WPU_MASK 0x00000008
|
|
#define GPIO43_MCU_WPD_OFFSET 2
|
|
#define GPIO43_MCU_WPD_MASK 0x00000004
|
|
#define GPIO43_MCU_IE_OFFSET 1
|
|
#define GPIO43_MCU_IE_MASK 0x00000002
|
|
#define GPIO43_MCU_OE_OFFSET 0
|
|
#define GPIO43_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO44_PIN_CFG_ADDR 0x9c
|
|
#define GPIO44_SEC_OFFSET 17
|
|
#define GPIO44_SEC_MASK 0x00020000
|
|
#define GPIO44_ODRV_OFFSET 16
|
|
#define GPIO44_ODRV_MASK 0x00010000
|
|
#define GPIO44_IINV_OFFSET 15
|
|
#define GPIO44_IINV_MASK 0x00008000
|
|
#define GPIO44_OINV_OFFSET 14
|
|
#define GPIO44_OINV_MASK 0x00004000
|
|
#define GPIO44_OPOS_OFFSET 13
|
|
#define GPIO44_OPOS_MASK 0x00002000
|
|
#define GPIO44_ONEG_OFFSET 12
|
|
#define GPIO44_ONEG_MASK 0x00001000
|
|
#define GPIO44_IPOS_OFFSET 11
|
|
#define GPIO44_IPOS_MASK 0x00000800
|
|
#define GPIO44_INEG_OFFSET 10
|
|
#define GPIO44_INEG_MASK 0x00000400
|
|
#define GPIO44_ORE_OFFSET 9
|
|
#define GPIO44_ORE_MASK 0x00000200
|
|
#define GPIO44_IRE_OFFSET 8
|
|
#define GPIO44_IRE_MASK 0x00000100
|
|
#define GPIO44_FUNC_WPU_OFFSET 7
|
|
#define GPIO44_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO44_FUNC_WPD_OFFSET 6
|
|
#define GPIO44_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO44_FUNC_SEL_OFFSET 4
|
|
#define GPIO44_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO44_MCU_WPU_OFFSET 3
|
|
#define GPIO44_MCU_WPU_MASK 0x00000008
|
|
#define GPIO44_MCU_WPD_OFFSET 2
|
|
#define GPIO44_MCU_WPD_MASK 0x00000004
|
|
#define GPIO44_MCU_IE_OFFSET 1
|
|
#define GPIO44_MCU_IE_MASK 0x00000002
|
|
#define GPIO44_MCU_OE_OFFSET 0
|
|
#define GPIO44_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO45_PIN_CFG_ADDR 0xa0
|
|
#define GPIO45_SEC_OFFSET 17
|
|
#define GPIO45_SEC_MASK 0x00020000
|
|
#define GPIO45_ODRV_OFFSET 16
|
|
#define GPIO45_ODRV_MASK 0x00010000
|
|
#define GPIO45_IINV_OFFSET 15
|
|
#define GPIO45_IINV_MASK 0x00008000
|
|
#define GPIO45_OINV_OFFSET 14
|
|
#define GPIO45_OINV_MASK 0x00004000
|
|
#define GPIO45_OPOS_OFFSET 13
|
|
#define GPIO45_OPOS_MASK 0x00002000
|
|
#define GPIO45_ONEG_OFFSET 12
|
|
#define GPIO45_ONEG_MASK 0x00001000
|
|
#define GPIO45_IPOS_OFFSET 11
|
|
#define GPIO45_IPOS_MASK 0x00000800
|
|
#define GPIO45_INEG_OFFSET 10
|
|
#define GPIO45_INEG_MASK 0x00000400
|
|
#define GPIO45_ORE_OFFSET 9
|
|
#define GPIO45_ORE_MASK 0x00000200
|
|
#define GPIO45_IRE_OFFSET 8
|
|
#define GPIO45_IRE_MASK 0x00000100
|
|
#define GPIO45_FUNC_WPU_OFFSET 7
|
|
#define GPIO45_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO45_FUNC_WPD_OFFSET 6
|
|
#define GPIO45_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO45_FUNC_SEL_OFFSET 4
|
|
#define GPIO45_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO45_MCU_WPU_OFFSET 3
|
|
#define GPIO45_MCU_WPU_MASK 0x00000008
|
|
#define GPIO45_MCU_WPD_OFFSET 2
|
|
#define GPIO45_MCU_WPD_MASK 0x00000004
|
|
#define GPIO45_MCU_IE_OFFSET 1
|
|
#define GPIO45_MCU_IE_MASK 0x00000002
|
|
#define GPIO45_MCU_OE_OFFSET 0
|
|
#define GPIO45_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO46_PIN_CFG_ADDR 0xa4
|
|
#define GPIO46_SEC_OFFSET 17
|
|
#define GPIO46_SEC_MASK 0x00020000
|
|
#define GPIO46_ODRV_OFFSET 16
|
|
#define GPIO46_ODRV_MASK 0x00010000
|
|
#define GPIO46_IINV_OFFSET 15
|
|
#define GPIO46_IINV_MASK 0x00008000
|
|
#define GPIO46_OINV_OFFSET 14
|
|
#define GPIO46_OINV_MASK 0x00004000
|
|
#define GPIO46_OPOS_OFFSET 13
|
|
#define GPIO46_OPOS_MASK 0x00002000
|
|
#define GPIO46_ONEG_OFFSET 12
|
|
#define GPIO46_ONEG_MASK 0x00001000
|
|
#define GPIO46_IPOS_OFFSET 11
|
|
#define GPIO46_IPOS_MASK 0x00000800
|
|
#define GPIO46_INEG_OFFSET 10
|
|
#define GPIO46_INEG_MASK 0x00000400
|
|
#define GPIO46_ORE_OFFSET 9
|
|
#define GPIO46_ORE_MASK 0x00000200
|
|
#define GPIO46_IRE_OFFSET 8
|
|
#define GPIO46_IRE_MASK 0x00000100
|
|
#define GPIO46_FUNC_WPU_OFFSET 7
|
|
#define GPIO46_FUNC_WPU_MASK 0x00000080
|
|
#define GPIO46_FUNC_WPD_OFFSET 6
|
|
#define GPIO46_FUNC_WPD_MASK 0x00000040
|
|
#define GPIO46_FUNC_SEL_OFFSET 4
|
|
#define GPIO46_FUNC_SEL_MASK 0x00000030
|
|
#define GPIO46_MCU_WPU_OFFSET 3
|
|
#define GPIO46_MCU_WPU_MASK 0x00000008
|
|
#define GPIO46_MCU_WPD_OFFSET 2
|
|
#define GPIO46_MCU_WPD_MASK 0x00000004
|
|
#define GPIO46_MCU_IE_OFFSET 1
|
|
#define GPIO46_MCU_IE_MASK 0x00000002
|
|
#define GPIO46_MCU_OE_OFFSET 0
|
|
#define GPIO46_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SMC_CLK_PIN_CFG_ADDR 0xa8
|
|
#define SMC_CLK_SEC_OFFSET 17
|
|
#define SMC_CLK_SEC_MASK 0x00020000
|
|
#define SMC_CLK_ODRV_OFFSET 16
|
|
#define SMC_CLK_ODRV_MASK 0x00010000
|
|
#define SMC_CLK_IINV_OFFSET 15
|
|
#define SMC_CLK_IINV_MASK 0x00008000
|
|
#define SMC_CLK_OINV_OFFSET 14
|
|
#define SMC_CLK_OINV_MASK 0x00004000
|
|
#define SMC_CLK_OPOS_OFFSET 13
|
|
#define SMC_CLK_OPOS_MASK 0x00002000
|
|
#define SMC_CLK_ONEG_OFFSET 12
|
|
#define SMC_CLK_ONEG_MASK 0x00001000
|
|
#define SMC_CLK_IPOS_OFFSET 11
|
|
#define SMC_CLK_IPOS_MASK 0x00000800
|
|
#define SMC_CLK_INEG_OFFSET 10
|
|
#define SMC_CLK_INEG_MASK 0x00000400
|
|
#define SMC_CLK_ORE_OFFSET 9
|
|
#define SMC_CLK_ORE_MASK 0x00000200
|
|
#define SMC_CLK_IRE_OFFSET 8
|
|
#define SMC_CLK_IRE_MASK 0x00000100
|
|
#define SMC_CLK_FUNC_WPU_OFFSET 7
|
|
#define SMC_CLK_FUNC_WPU_MASK 0x00000080
|
|
#define SMC_CLK_FUNC_WPD_OFFSET 6
|
|
#define SMC_CLK_FUNC_WPD_MASK 0x00000040
|
|
#define SMC_CLK_FUNC_SEL_OFFSET 4
|
|
#define SMC_CLK_FUNC_SEL_MASK 0x00000030
|
|
#define SMC_CLK_MCU_WPU_OFFSET 3
|
|
#define SMC_CLK_MCU_WPU_MASK 0x00000008
|
|
#define SMC_CLK_MCU_WPD_OFFSET 2
|
|
#define SMC_CLK_MCU_WPD_MASK 0x00000004
|
|
#define SMC_CLK_MCU_IE_OFFSET 1
|
|
#define SMC_CLK_MCU_IE_MASK 0x00000002
|
|
#define SMC_CLK_MCU_OE_OFFSET 0
|
|
#define SMC_CLK_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SMC_CS_PIN_CFG_ADDR 0xac
|
|
#define SMC_CS_SEC_OFFSET 17
|
|
#define SMC_CS_SEC_MASK 0x00020000
|
|
#define SMC_CS_ODRV_OFFSET 16
|
|
#define SMC_CS_ODRV_MASK 0x00010000
|
|
#define SMC_CS_IINV_OFFSET 15
|
|
#define SMC_CS_IINV_MASK 0x00008000
|
|
#define SMC_CS_OINV_OFFSET 14
|
|
#define SMC_CS_OINV_MASK 0x00004000
|
|
#define SMC_CS_OPOS_OFFSET 13
|
|
#define SMC_CS_OPOS_MASK 0x00002000
|
|
#define SMC_CS_ONEG_OFFSET 12
|
|
#define SMC_CS_ONEG_MASK 0x00001000
|
|
#define SMC_CS_IPOS_OFFSET 11
|
|
#define SMC_CS_IPOS_MASK 0x00000800
|
|
#define SMC_CS_INEG_OFFSET 10
|
|
#define SMC_CS_INEG_MASK 0x00000400
|
|
#define SMC_CS_ORE_OFFSET 9
|
|
#define SMC_CS_ORE_MASK 0x00000200
|
|
#define SMC_CS_IRE_OFFSET 8
|
|
#define SMC_CS_IRE_MASK 0x00000100
|
|
#define SMC_CS_FUNC_WPU_OFFSET 7
|
|
#define SMC_CS_FUNC_WPU_MASK 0x00000080
|
|
#define SMC_CS_FUNC_WPD_OFFSET 6
|
|
#define SMC_CS_FUNC_WPD_MASK 0x00000040
|
|
#define SMC_CS_FUNC_SEL_OFFSET 4
|
|
#define SMC_CS_FUNC_SEL_MASK 0x00000030
|
|
#define SMC_CS_MCU_WPU_OFFSET 3
|
|
#define SMC_CS_MCU_WPU_MASK 0x00000008
|
|
#define SMC_CS_MCU_WPD_OFFSET 2
|
|
#define SMC_CS_MCU_WPD_MASK 0x00000004
|
|
#define SMC_CS_MCU_IE_OFFSET 1
|
|
#define SMC_CS_MCU_IE_MASK 0x00000002
|
|
#define SMC_CS_MCU_OE_OFFSET 0
|
|
#define SMC_CS_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SMC_D0_PIN_CFG_ADDR 0xb0
|
|
#define SMC_D0_SEC_OFFSET 17
|
|
#define SMC_D0_SEC_MASK 0x00020000
|
|
#define SMC_D0_ODRV_OFFSET 16
|
|
#define SMC_D0_ODRV_MASK 0x00010000
|
|
#define SMC_D0_IINV_OFFSET 15
|
|
#define SMC_D0_IINV_MASK 0x00008000
|
|
#define SMC_D0_OINV_OFFSET 14
|
|
#define SMC_D0_OINV_MASK 0x00004000
|
|
#define SMC_D0_OPOS_OFFSET 13
|
|
#define SMC_D0_OPOS_MASK 0x00002000
|
|
#define SMC_D0_ONEG_OFFSET 12
|
|
#define SMC_D0_ONEG_MASK 0x00001000
|
|
#define SMC_D0_IPOS_OFFSET 11
|
|
#define SMC_D0_IPOS_MASK 0x00000800
|
|
#define SMC_D0_INEG_OFFSET 10
|
|
#define SMC_D0_INEG_MASK 0x00000400
|
|
#define SMC_D0_ORE_OFFSET 9
|
|
#define SMC_D0_ORE_MASK 0x00000200
|
|
#define SMC_D0_IRE_OFFSET 8
|
|
#define SMC_D0_IRE_MASK 0x00000100
|
|
#define SMC_D0_FUNC_WPU_OFFSET 7
|
|
#define SMC_D0_FUNC_WPU_MASK 0x00000080
|
|
#define SMC_D0_FUNC_WPD_OFFSET 6
|
|
#define SMC_D0_FUNC_WPD_MASK 0x00000040
|
|
#define SMC_D0_FUNC_SEL_OFFSET 4
|
|
#define SMC_D0_FUNC_SEL_MASK 0x00000030
|
|
#define SMC_D0_MCU_WPU_OFFSET 3
|
|
#define SMC_D0_MCU_WPU_MASK 0x00000008
|
|
#define SMC_D0_MCU_WPD_OFFSET 2
|
|
#define SMC_D0_MCU_WPD_MASK 0x00000004
|
|
#define SMC_D0_MCU_IE_OFFSET 1
|
|
#define SMC_D0_MCU_IE_MASK 0x00000002
|
|
#define SMC_D0_MCU_OE_OFFSET 0
|
|
#define SMC_D0_MCU_OE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SMC_D1_PIN_CFG_ADDR 0xb4
|
|
#define SMC_D1_SEC_OFFSET 17
|
|
#define SMC_D1_SEC_MASK 0x00020000
|
|
#define SMC_D1_ODRV_OFFSET 16
|
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#define SMC_D1_ODRV_MASK 0x00010000
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#define SMC_D1_IINV_OFFSET 15
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#define SMC_D1_IINV_MASK 0x00008000
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#define SMC_D1_OINV_OFFSET 14
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#define SMC_D1_OINV_MASK 0x00004000
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#define SMC_D1_OPOS_OFFSET 13
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#define SMC_D1_OPOS_MASK 0x00002000
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#define SMC_D1_ONEG_OFFSET 12
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#define SMC_D1_ONEG_MASK 0x00001000
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#define SMC_D1_IPOS_OFFSET 11
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#define SMC_D1_IPOS_MASK 0x00000800
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#define SMC_D1_INEG_OFFSET 10
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#define SMC_D1_INEG_MASK 0x00000400
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#define SMC_D1_ORE_OFFSET 9
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#define SMC_D1_ORE_MASK 0x00000200
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#define SMC_D1_IRE_OFFSET 8
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#define SMC_D1_IRE_MASK 0x00000100
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#define SMC_D1_FUNC_WPU_OFFSET 7
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#define SMC_D1_FUNC_WPU_MASK 0x00000080
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#define SMC_D1_FUNC_WPD_OFFSET 6
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#define SMC_D1_FUNC_WPD_MASK 0x00000040
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#define SMC_D1_FUNC_SEL_OFFSET 4
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#define SMC_D1_FUNC_SEL_MASK 0x00000030
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#define SMC_D1_MCU_WPU_OFFSET 3
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#define SMC_D1_MCU_WPU_MASK 0x00000008
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#define SMC_D1_MCU_WPD_OFFSET 2
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#define SMC_D1_MCU_WPD_MASK 0x00000004
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#define SMC_D1_MCU_IE_OFFSET 1
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#define SMC_D1_MCU_IE_MASK 0x00000002
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#define SMC_D1_MCU_OE_OFFSET 0
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#define SMC_D1_MCU_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SMC_D2_PIN_CFG_ADDR 0xb8
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#define SMC_D2_SEC_OFFSET 17
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#define SMC_D2_SEC_MASK 0x00020000
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#define SMC_D2_ODRV_OFFSET 16
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#define SMC_D2_ODRV_MASK 0x00010000
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#define SMC_D2_IINV_OFFSET 15
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#define SMC_D2_IINV_MASK 0x00008000
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#define SMC_D2_OINV_OFFSET 14
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#define SMC_D2_OINV_MASK 0x00004000
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#define SMC_D2_OPOS_OFFSET 13
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#define SMC_D2_OPOS_MASK 0x00002000
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#define SMC_D2_ONEG_OFFSET 12
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#define SMC_D2_ONEG_MASK 0x00001000
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#define SMC_D2_IPOS_OFFSET 11
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#define SMC_D2_IPOS_MASK 0x00000800
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#define SMC_D2_INEG_OFFSET 10
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#define SMC_D2_INEG_MASK 0x00000400
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#define SMC_D2_ORE_OFFSET 9
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#define SMC_D2_ORE_MASK 0x00000200
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#define SMC_D2_IRE_OFFSET 8
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#define SMC_D2_IRE_MASK 0x00000100
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#define SMC_D2_FUNC_WPU_OFFSET 7
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#define SMC_D2_FUNC_WPU_MASK 0x00000080
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#define SMC_D2_FUNC_WPD_OFFSET 6
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#define SMC_D2_FUNC_WPD_MASK 0x00000040
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#define SMC_D2_FUNC_SEL_OFFSET 4
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#define SMC_D2_FUNC_SEL_MASK 0x00000030
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#define SMC_D2_MCU_WPU_OFFSET 3
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#define SMC_D2_MCU_WPU_MASK 0x00000008
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#define SMC_D2_MCU_WPD_OFFSET 2
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#define SMC_D2_MCU_WPD_MASK 0x00000004
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#define SMC_D2_MCU_IE_OFFSET 1
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#define SMC_D2_MCU_IE_MASK 0x00000002
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#define SMC_D2_MCU_OE_OFFSET 0
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#define SMC_D2_MCU_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SMC_D3_PIN_CFG_ADDR 0xbc
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#define SMC_D3_SEC_OFFSET 17
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#define SMC_D3_SEC_MASK 0x00020000
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#define SMC_D3_ODRV_OFFSET 16
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#define SMC_D3_ODRV_MASK 0x00010000
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#define SMC_D3_IINV_OFFSET 15
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#define SMC_D3_IINV_MASK 0x00008000
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#define SMC_D3_OINV_OFFSET 14
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#define SMC_D3_OINV_MASK 0x00004000
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#define SMC_D3_OPOS_OFFSET 13
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#define SMC_D3_OPOS_MASK 0x00002000
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#define SMC_D3_ONEG_OFFSET 12
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#define SMC_D3_ONEG_MASK 0x00001000
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#define SMC_D3_IPOS_OFFSET 11
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#define SMC_D3_IPOS_MASK 0x00000800
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#define SMC_D3_INEG_OFFSET 10
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#define SMC_D3_INEG_MASK 0x00000400
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#define SMC_D3_ORE_OFFSET 9
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#define SMC_D3_ORE_MASK 0x00000200
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#define SMC_D3_IRE_OFFSET 8
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#define SMC_D3_IRE_MASK 0x00000100
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#define SMC_D3_FUNC_WPU_OFFSET 7
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#define SMC_D3_FUNC_WPU_MASK 0x00000080
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#define SMC_D3_FUNC_WPD_OFFSET 6
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#define SMC_D3_FUNC_WPD_MASK 0x00000040
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#define SMC_D3_FUNC_SEL_OFFSET 4
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#define SMC_D3_FUNC_SEL_MASK 0x00000030
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#define SMC_D3_MCU_WPU_OFFSET 3
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#define SMC_D3_MCU_WPU_MASK 0x00000008
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#define SMC_D3_MCU_WPD_OFFSET 2
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#define SMC_D3_MCU_WPD_MASK 0x00000004
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#define SMC_D3_MCU_IE_OFFSET 1
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#define SMC_D3_MCU_IE_MASK 0x00000002
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#define SMC_D3_MCU_OE_OFFSET 0
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#define SMC_D3_MCU_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO47_PIN_CFG_ADDR 0xc0
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#define GPIO47_SEC_OFFSET 17
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#define GPIO47_SEC_MASK 0x00020000
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#define GPIO47_ODRV_OFFSET 16
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#define GPIO47_ODRV_MASK 0x00010000
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#define GPIO47_IINV_OFFSET 15
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#define GPIO47_IINV_MASK 0x00008000
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#define GPIO47_OINV_OFFSET 14
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#define GPIO47_OINV_MASK 0x00004000
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#define GPIO47_OPOS_OFFSET 13
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#define GPIO47_OPOS_MASK 0x00002000
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#define GPIO47_ONEG_OFFSET 12
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#define GPIO47_ONEG_MASK 0x00001000
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#define GPIO47_IPOS_OFFSET 11
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#define GPIO47_IPOS_MASK 0x00000800
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#define GPIO47_INEG_OFFSET 10
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#define GPIO47_INEG_MASK 0x00000400
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#define GPIO47_ORE_OFFSET 9
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#define GPIO47_ORE_MASK 0x00000200
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#define GPIO47_IRE_OFFSET 8
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#define GPIO47_IRE_MASK 0x00000100
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#define GPIO47_FUNC_WPU_OFFSET 7
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#define GPIO47_FUNC_WPU_MASK 0x00000080
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#define GPIO47_FUNC_WPD_OFFSET 6
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#define GPIO47_FUNC_WPD_MASK 0x00000040
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#define GPIO47_FUNC_SEL_OFFSET 4
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#define GPIO47_FUNC_SEL_MASK 0x00000030
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#define GPIO47_MCU_WPU_OFFSET 3
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#define GPIO47_MCU_WPU_MASK 0x00000008
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#define GPIO47_MCU_WPD_OFFSET 2
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#define GPIO47_MCU_WPD_MASK 0x00000004
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#define GPIO47_MCU_IE_OFFSET 1
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#define GPIO47_MCU_IE_MASK 0x00000002
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#define GPIO47_MCU_OE_OFFSET 0
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#define GPIO47_MCU_OE_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO48_PIN_CFG_ADDR 0xc4
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#define GPIO48_SEC_OFFSET 17
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#define GPIO48_SEC_MASK 0x00020000
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#define GPIO48_ODRV_OFFSET 16
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#define GPIO48_ODRV_MASK 0x00010000
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#define GPIO48_IINV_OFFSET 15
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#define GPIO48_IINV_MASK 0x00008000
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#define GPIO48_OINV_OFFSET 14
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#define GPIO48_OINV_MASK 0x00004000
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#define GPIO48_OPOS_OFFSET 13
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#define GPIO48_OPOS_MASK 0x00002000
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#define GPIO48_ONEG_OFFSET 12
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#define GPIO48_ONEG_MASK 0x00001000
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#define GPIO48_IPOS_OFFSET 11
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#define GPIO48_IPOS_MASK 0x00000800
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#define GPIO48_INEG_OFFSET 10
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#define GPIO48_INEG_MASK 0x00000400
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#define GPIO48_ORE_OFFSET 9
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#define GPIO48_ORE_MASK 0x00000200
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#define GPIO48_IRE_OFFSET 8
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#define GPIO48_IRE_MASK 0x00000100
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#define GPIO48_FUNC_WPU_OFFSET 7
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#define GPIO48_FUNC_WPU_MASK 0x00000080
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#define GPIO48_FUNC_WPD_OFFSET 6
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#define GPIO48_FUNC_WPD_MASK 0x00000040
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#define GPIO48_FUNC_SEL_OFFSET 4
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#define GPIO48_FUNC_SEL_MASK 0x00000030
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#define GPIO48_MCU_WPU_OFFSET 3
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#define GPIO48_MCU_WPU_MASK 0x00000008
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#define GPIO48_MCU_WPD_OFFSET 2
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#define GPIO48_MCU_WPD_MASK 0x00000004
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#define GPIO48_MCU_IE_OFFSET 1
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#define GPIO48_MCU_IE_MASK 0x00000002
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#define GPIO48_MCU_OE_OFFSET 0
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#define GPIO48_MCU_OE_MASK 0x00000001
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//HW module read/write macro
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#define PIN_RF_READ_REG(addr) SOC_READ_REG(PIN_RF_BASEADDR + addr)
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#define PIN_RF_WRITE_REG(addr,value) SOC_WRITE_REG(PIN_RF_BASEADDR + addr,value)
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