421 lines
14 KiB
C
Executable File
421 lines
14 KiB
C
Executable File
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//-----------------------------------
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#define CFG_UART_FIFO_ADDR 0x0
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#define RXFIFO_RD_BYTE_OFFSET 0
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#define RXFIFO_RD_BYTE_MASK 0x000000FF
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//-----------------------------------
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#define CFG_UART_INT_ENA_ADDR 0x4
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#define BRK_DET_INT_ENA_OFFSET 18
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#define BRK_DET_INT_ENA_MASK 0x00040000
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#define CTS_CHG_INT_ENA_OFFSET 17
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#define CTS_CHG_INT_ENA_MASK 0x00020000
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#define DSR_CHG_INT_ENA_OFFSET 16
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#define DSR_CHG_INT_ENA_MASK 0x00010000
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#define RXFIFO_OVF_INT_ENA_OFFSET 15
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#define RXFIFO_OVF_INT_ENA_MASK 0x00008000
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#define FRM_ERR_INT_ENA_OFFSET 14
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#define FRM_ERR_INT_ENA_MASK 0x00004000
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#define PARITY_ERR_INT_ENA_OFFSET 13
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#define PARITY_ERR_INT_ENA_MASK 0x00002000
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#define TXFIFO_EMPTY_INT_ENA_OFFSET 12
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#define TXFIFO_EMPTY_INT_ENA_MASK 0x00001000
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#define RXFIFO_FULL_INT_ENA_OFFSET 11
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#define RXFIFO_FULL_INT_ENA_MASK 0x00000800
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#define CMD_AT_CHAR_DET_INT_ENA_OFFSET 10
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#define CMD_AT_CHAR_DET_INT_ENA_MASK 0x00000400
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#define TX_DONE_INT_ENA_OFFSET 9
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#define TX_DONE_INT_ENA_MASK 0x00000200
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#define TX_BRK_IDLE_DONE_INT_ENA_OFFSET 8
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#define TX_BRK_IDLE_DONE_INT_ENA_MASK 0x00000100
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#define TX_BRK_DONE_INT_ENA_OFFSET 7
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#define TX_BRK_DONE_INT_ENA_MASK 0x00000080
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#define GLITCH_DET_INT_ENA_OFFSET 6
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#define GLITCH_DET_INT_ENA_MASK 0x00000040
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#define SW_XOFF_INT_ENA_OFFSET 5
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#define SW_XOFF_INT_ENA_MASK 0x00000020
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#define SW_XON_INT_ENA_OFFSET 4
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#define SW_XON_INT_ENA_MASK 0x00000010
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#define RS485_CLASH_INT_ENA_OFFSET 3
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#define RS485_CLASH_INT_ENA_MASK 0x00000008
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#define RS485_FRM_ERR_INT_ENA_OFFSET 2
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#define RS485_FRM_ERR_INT_ENA_MASK 0x00000004
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#define RS485_PARITY_ERR_INT_ENA_OFFSET 1
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#define RS485_PARITY_ERR_INT_ENA_MASK 0x00000002
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#define RXFIFO_TOUT_INT_ENA_OFFSET 0
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#define RXFIFO_TOUT_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_INT_CLR_ADDR 0x8
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#define BRK_DET_INT_CLR_OFFSET 18
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#define BRK_DET_INT_CLR_MASK 0x00040000
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#define CTS_CHG_INT_CLR_OFFSET 17
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#define CTS_CHG_INT_CLR_MASK 0x00020000
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#define DSR_CHG_INT_CLR_OFFSET 16
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#define DSR_CHG_INT_CLR_MASK 0x00010000
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#define RXFIFO_OVF_INT_CLR_OFFSET 15
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#define RXFIFO_OVF_INT_CLR_MASK 0x00008000
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#define FRM_ERR_INT_CLR_OFFSET 14
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#define FRM_ERR_INT_CLR_MASK 0x00004000
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#define PARITY_ERR_INT_CLR_OFFSET 13
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#define PARITY_ERR_INT_CLR_MASK 0x00002000
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#define TXFIFO_EMPTY_INT_CLR_OFFSET 12
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#define TXFIFO_EMPTY_INT_CLR_MASK 0x00001000
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#define RXFIFO_FULL_INT_CLR_OFFSET 11
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#define RXFIFO_FULL_INT_CLR_MASK 0x00000800
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#define CMD_AT_CHAR_DET_INT_CLR_OFFSET 10
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#define CMD_AT_CHAR_DET_INT_CLR_MASK 0x00000400
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#define TX_DONE_INT_CLR_OFFSET 9
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#define TX_DONE_INT_CLR_MASK 0x00000200
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#define TX_BRK_IDLE_DONE_INT_CLR_OFFSET 8
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#define TX_BRK_IDLE_DONE_INT_CLR_MASK 0x00000100
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#define TX_BRK_DONE_INT_CLR_OFFSET 7
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#define TX_BRK_DONE_INT_CLR_MASK 0x00000080
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#define GLITCH_DET_INT_CLR_OFFSET 6
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#define GLITCH_DET_INT_CLR_MASK 0x00000040
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#define SW_XOFF_INT_CLR_OFFSET 5
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#define SW_XOFF_INT_CLR_MASK 0x00000020
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#define SW_XON_INT_CLR_OFFSET 4
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#define SW_XON_INT_CLR_MASK 0x00000010
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#define RS485_CLASH_INT_CLR_OFFSET 3
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#define RS485_CLASH_INT_CLR_MASK 0x00000008
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#define RS485_FRM_ERR_INT_CLR_OFFSET 2
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#define RS485_FRM_ERR_INT_CLR_MASK 0x00000004
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#define RS485_PARITY_ERR_INT_CLR_OFFSET 1
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#define RS485_PARITY_ERR_INT_CLR_MASK 0x00000002
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#define RXFIFO_TOUT_INT_CLR_OFFSET 0
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#define RXFIFO_TOUT_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_INT_RAW_ADDR 0xc
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#define BRK_DET_INT_RAW_OFFSET 18
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#define BRK_DET_INT_RAW_MASK 0x00040000
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#define CTS_CHG_INT_RAW_OFFSET 17
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#define CTS_CHG_INT_RAW_MASK 0x00020000
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#define DSR_CHG_INT_RAW_OFFSET 16
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#define DSR_CHG_INT_RAW_MASK 0x00010000
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#define RXFIFO_OVF_INT_RAW_OFFSET 15
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#define RXFIFO_OVF_INT_RAW_MASK 0x00008000
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#define FRM_ERR_INT_RAW_OFFSET 14
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#define FRM_ERR_INT_RAW_MASK 0x00004000
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#define PARITY_ERR_INT_RAW_OFFSET 13
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#define PARITY_ERR_INT_RAW_MASK 0x00002000
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#define TXFIFO_EMPTY_INT_RAW_OFFSET 12
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#define TXFIFO_EMPTY_INT_RAW_MASK 0x00001000
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#define RXFIFO_FULL_INT_RAW_OFFSET 11
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#define RXFIFO_FULL_INT_RAW_MASK 0x00000800
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#define CMD_AT_CHAR_DET_INT_RAW_OFFSET 10
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#define CMD_AT_CHAR_DET_INT_RAW_MASK 0x00000400
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#define TX_DONE_INT_RAW_OFFSET 9
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#define TX_DONE_INT_RAW_MASK 0x00000200
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#define TX_BRK_IDLE_DONE_INT_RAW_OFFSET 8
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#define TX_BRK_IDLE_DONE_INT_RAW_MASK 0x00000100
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#define TX_BRK_DONE_INT_RAW_OFFSET 7
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#define TX_BRK_DONE_INT_RAW_MASK 0x00000080
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#define GLITCH_DET_INT_RAW_OFFSET 6
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#define GLITCH_DET_INT_RAW_MASK 0x00000040
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#define SW_XOFF_INT_RAW_OFFSET 5
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#define SW_XOFF_INT_RAW_MASK 0x00000020
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#define SW_XON_INT_RAW_OFFSET 4
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#define SW_XON_INT_RAW_MASK 0x00000010
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#define RS485_CLASH_INT_RAW_OFFSET 3
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#define RS485_CLASH_INT_RAW_MASK 0x00000008
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#define RS485_FRM_ERR_INT_RAW_OFFSET 2
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#define RS485_FRM_ERR_INT_RAW_MASK 0x00000004
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#define RS485_PARITY_ERR_INT_RAW_OFFSET 1
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#define RS485_PARITY_ERR_INT_RAW_MASK 0x00000002
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#define RXFIFO_TOUT_INT_RAW_OFFSET 0
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#define RXFIFO_TOUT_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_INT_ST_ADDR 0x10
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#define BRK_DET_INT_ST_OFFSET 18
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#define BRK_DET_INT_ST_MASK 0x00040000
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#define CTS_CHG_INT_ST_OFFSET 17
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#define CTS_CHG_INT_ST_MASK 0x00020000
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#define DSR_CHG_INT_ST_OFFSET 16
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#define DSR_CHG_INT_ST_MASK 0x00010000
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#define RXFIFO_OVF_INT_ST_OFFSET 15
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#define RXFIFO_OVF_INT_ST_MASK 0x00008000
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#define FRM_ERR_INT_ST_OFFSET 14
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#define FRM_ERR_INT_ST_MASK 0x00004000
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#define PARITY_ERR_INT_ST_OFFSET 13
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#define PARITY_ERR_INT_ST_MASK 0x00002000
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#define TXFIFO_EMPTY_INT_ST_OFFSET 12
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#define TXFIFO_EMPTY_INT_ST_MASK 0x00001000
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#define RXFIFO_FULL_INT_ST_OFFSET 11
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#define RXFIFO_FULL_INT_ST_MASK 0x00000800
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#define CMD_AT_CHAR_DET_INT_ST_OFFSET 10
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#define CMD_AT_CHAR_DET_INT_ST_MASK 0x00000400
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#define TX_DONE_INT_ST_OFFSET 9
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#define TX_DONE_INT_ST_MASK 0x00000200
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#define TX_BRK_IDLE_DONE_INT_ST_OFFSET 8
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#define TX_BRK_IDLE_DONE_INT_ST_MASK 0x00000100
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#define TX_BRK_DONE_INT_ST_OFFSET 7
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#define TX_BRK_DONE_INT_ST_MASK 0x00000080
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#define GLITCH_DET_INT_ST_OFFSET 6
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#define GLITCH_DET_INT_ST_MASK 0x00000040
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#define SW_XOFF_INT_ST_OFFSET 5
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#define SW_XOFF_INT_ST_MASK 0x00000020
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#define SW_XON_INT_ST_OFFSET 4
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#define SW_XON_INT_ST_MASK 0x00000010
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#define RS485_CLASH_INT_ST_OFFSET 3
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#define RS485_CLASH_INT_ST_MASK 0x00000008
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#define RS485_FRM_ERR_INT_ST_OFFSET 2
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#define RS485_FRM_ERR_INT_ST_MASK 0x00000004
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#define RS485_PARITY_ERR_INT_ST_OFFSET 1
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#define RS485_PARITY_ERR_INT_ST_MASK 0x00000002
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#define RXFIFO_TOUT_INT_ST_OFFSET 0
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#define RXFIFO_TOUT_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_CTRL0_ADDR 0x14
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#define FORCE_TXD_BRK_OFFSET 30
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#define FORCE_TXD_BRK_MASK 0x40000000
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#define TX_FLOW_EN_OFFSET 29
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#define TX_FLOW_EN_MASK 0x20000000
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#define UART_LOOPBACK_OFFSET 28
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#define UART_LOOPBACK_MASK 0x10000000
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#define IRDA_RX_INV_OFFSET 27
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#define IRDA_RX_INV_MASK 0x08000000
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#define IRDA_TX_INV_OFFSET 26
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#define IRDA_TX_INV_MASK 0x04000000
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#define IRDA_WCTL_OFFSET 25
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#define IRDA_WCTL_MASK 0x02000000
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#define IRDA_TX_EN_OFFSET 24
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#define IRDA_TX_EN_MASK 0x01000000
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#define IRDA_DPLX_OFFSET 23
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#define IRDA_DPLX_MASK 0x00800000
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#define TXD_BRK_OFFSET 22
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#define TXD_BRK_MASK 0x00400000
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#define SW_DTR_OFFSET 21
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#define SW_DTR_MASK 0x00200000
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#define SW_RTS_OFFSET 20
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#define SW_RTS_MASK 0x00100000
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#define STOP_BIT_NUM_OFFSET 18
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#define STOP_BIT_NUM_MASK 0x000C0000
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#define BIT_NUM_OFFSET 16
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#define BIT_NUM_MASK 0x00030000
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#define PARITY_EN_OFFSET 15
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#define PARITY_EN_MASK 0x00008000
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#define PARITY_OFFSET 14
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#define PARITY_MASK 0x00004000
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#define UART_TICK_REF_ALWAYS_ON_OFFSET 13
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#define UART_TICK_REF_ALWAYS_ON_MASK 0x00002000
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#define UART_ERR_WR_MASK_OFFSET 12
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#define UART_ERR_WR_MASK_MASK 0x00001000
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#define UART_REG_CLK_EN_OFFSET 11
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#define UART_REG_CLK_EN_MASK 0x00000800
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#define UART_DTR_INV_OFFSET 10
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#define UART_DTR_INV_MASK 0x00000400
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#define UART_RTS_INV_OFFSET 9
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#define UART_RTS_INV_MASK 0x00000200
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#define UART_TXD_INV_OFFSET 8
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#define UART_TXD_INV_MASK 0x00000100
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#define UART_DSR_INV_OFFSET 7
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#define UART_DSR_INV_MASK 0x00000080
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#define UART_CTS_INV_OFFSET 6
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#define UART_CTS_INV_MASK 0x00000040
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#define UART_RXD_INV_OFFSET 3
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#define UART_RXD_INV_MASK 0x00000008
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#define TXFIFO_RST_OFFSET 2
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#define TXFIFO_RST_MASK 0x00000004
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#define RXFIFO_RST_OFFSET 1
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#define RXFIFO_RST_MASK 0x00000002
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#define IRDA_EN_OFFSET 0
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#define IRDA_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_CTRL1_ADDR 0x18
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#define RX_TOUT_EN_OFFSET 31
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#define RX_TOUT_EN_MASK 0x80000000
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#define RX_TOUT_THRHD_OFFSET 24
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#define RX_TOUT_THRHD_MASK 0x7F000000
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#define RX_FLOW_EN_OFFSET 23
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#define RX_FLOW_EN_MASK 0x00800000
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#define RX_FLOW_THRHD_OFFSET 16
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#define RX_FLOW_THRHD_MASK 0x007F0000
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#define TXFIFO_EMPTY_THRHD_OFFSET 8
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#define TXFIFO_EMPTY_THRHD_MASK 0x00007F00
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#define RXFIFO_FULL_THRHD_OFFSET 0
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#define RXFIFO_FULL_THRHD_MASK 0x0000007F
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//-----------------------------------
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#define CFG_UART_CLK_CFG_ADDR 0x1c
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#define UART_CLKDIV_FRAG_OFFSET 20
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#define UART_CLKDIV_FRAG_MASK 0x00F00000
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#define UART_CLKDIV_OFFSET 0
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#define UART_CLKDIV_MASK 0x000FFFFF
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//-----------------------------------
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#define CFG_UART_BAUD_CFG_ADDR 0x20
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#define GLITCH_FILT_OFFSET 8
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#define GLITCH_FILT_MASK 0x0000FF00
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#define AUTOBAUD_EN_OFFSET 0
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#define AUTOBAUD_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_STS_ADDR 0x24
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#define TXD_OFFSET 31
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#define TXD_MASK 0x80000000
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#define RTSN_OFFSET 30
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#define RTSN_MASK 0x40000000
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#define DTRN_OFFSET 29
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#define DTRN_MASK 0x20000000
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#define ST_UTX_OUT_OFFSET 24
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#define ST_UTX_OUT_MASK 0x0F000000
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#define TXFIFO_CNT_OFFSET 16
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#define TXFIFO_CNT_MASK 0x00FF0000
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#define RXD_OFFSET 14
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#define RXD_MASK 0x00004000
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#define CTSN_OFFSET 13
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#define CTSN_MASK 0x00002000
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#define DSRN_OFFSET 12
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#define DSRN_MASK 0x00001000
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#define ST_URX_OUT_OFFSET 8
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#define ST_URX_OUT_MASK 0x00000F00
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#define RXFIFO_CNT_OFFSET 0
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#define RXFIFO_CNT_MASK 0x000000FF
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//-----------------------------------
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#define CFG_UART_RAM_TX_STS_ADDR 0x28
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#define MEM_TX_STATUS_OFFSET 0
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#define MEM_TX_STATUS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_UART_RAM_RX_STS_ADDR 0x2c
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#define MEM_RX_STATUS_OFFSET 0
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#define MEM_RX_STATUS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_UART_RAM_CNT_STS_ADDR 0x30
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#define TX_MEM_CNT_OFFSET 3
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#define TX_MEM_CNT_MASK 0x00000038
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#define RX_MEM_CNT_OFFSET 0
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#define RX_MEM_CNT_MASK 0x00000007
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//-----------------------------------
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#define CFG_UART_LOW_PULSE_ADDR 0x34
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#define LOWPULSE_MIN_CNT_OFFSET 0
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#define LOWPULSE_MIN_CNT_MASK 0x000FFFFF
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//-----------------------------------
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#define CFG_UART_HIG_HPULSE_ADDR 0x38
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#define HIGHPULSE_MIN_CNT_OFFSET 0
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#define HIGHPULSE_MIN_CNT_MASK 0x000FFFFF
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//-----------------------------------
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#define CFG_UART_RXD_COUNT_ADDR 0x3c
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#define RXD_EDGE_CNT_OFFSET 0
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#define RXD_EDGE_CNT_MASK 0x000003FF
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//-----------------------------------
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#define CFG_UART_FLOW_CFG_ADDR 0x40
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#define UART_FORCE_XOFF_OFFSET 5
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#define UART_FORCE_XOFF_MASK 0x00000020
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#define UART_FORCE_XON_OFFSET 4
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#define UART_FORCE_XON_MASK 0x00000010
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#define UART_SEND_XOFF_OFFSET 3
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#define UART_SEND_XOFF_MASK 0x00000008
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#define UART_SEND_XON_OFFSET 2
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#define UART_SEND_XON_MASK 0x00000004
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#define UART_XONOFF_DEL_OFFSET 1
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#define UART_XONOFF_DEL_MASK 0x00000002
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#define UART_SW_FLOW_CON_EN_OFFSET 0
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#define UART_SW_FLOW_CON_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_SLEEP_CFG_ADDR 0x44
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#define UART_ACTIVE_THRESHOLD_OFFSET 0
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#define UART_ACTIVE_THRESHOLD_MASK 0x000003FF
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//-----------------------------------
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#define CFG_UART_SWFC_CFG_ADDR 0x48
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#define UART_XOFF_CHAR_OFFSET 24
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#define UART_XOFF_CHAR_MASK 0xFF000000
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#define UART_XON_CHAR_OFFSET 16
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#define UART_XON_CHAR_MASK 0x00FF0000
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#define UART_XOFF_THRESHOLD_OFFSET 8
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#define UART_XOFF_THRESHOLD_MASK 0x0000FF00
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#define UART_XON_THRESHOLD_OFFSET 0
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#define UART_XON_THRESHOLD_MASK 0x000000FF
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//-----------------------------------
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#define CFG_UART_IDLE_CFG_ADDR 0x4c
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#define UART_TX_BRK_NUM_OFFSET 20
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#define UART_TX_BRK_NUM_MASK 0x0FF00000
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#define UART_TX_IDLE_NUM_OFFSET 10
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#define UART_TX_IDLE_NUM_MASK 0x000FFC00
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#define RX_IDLE_THRHD_OFFSET 0
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#define RX_IDLE_THRHD_MASK 0x000003FF
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//-----------------------------------
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#define CFG_UART_RS485_CFG_ADDR 0x50
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#define RS485_TX_DLY_NUM_OFFSET 6
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#define RS485_TX_DLY_NUM_MASK 0x000003C0
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#define RS485_RX_DLY_NUM_OFFSET 5
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#define RS485_RX_DLY_NUM_MASK 0x00000020
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#define RS485RXBY_TX_EN_OFFSET 4
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#define RS485RXBY_TX_EN_MASK 0x00000010
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#define RS485TX_RX_EN_OFFSET 3
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#define RS485TX_RX_EN_MASK 0x00000008
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#define DL1_EN_OFFSET 2
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#define DL1_EN_MASK 0x00000004
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#define DL0_EN_OFFSET 1
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#define DL0_EN_MASK 0x00000002
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#define RS485_EN_OFFSET 0
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#define RS485_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_UART_ATCMD_PRE_CNT_ADDR 0x54
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#define PRE_IDLE_NUM_OFFSET 0
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#define PRE_IDLE_NUM_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_UART_ATCMD_POST_CNT_ADDR 0x58
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#define POST_IDLE_NUM_OFFSET 0
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#define POST_IDLE_NUM_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_UART_ATCMD_GAP_TOUT_ADDR 0x5c
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#define RX_GAP_TOUT_OFFSET 0
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#define RX_GAP_TOUT_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_UART_ATCMD_CHAR_ADDR 0x60
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#define CHAR_NUM_OFFSET 8
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#define CHAR_NUM_MASK 0x0000FF00
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#define AT_CMD_CHAR_OFFSET 0
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#define AT_CMD_CHAR_MASK 0x000000FF
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//-----------------------------------
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#define CFG_UART_RAM_CFG_ADDR 0x64
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#define TX_MEM_EMPTY_THRHD_OFFSET 28
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#define TX_MEM_EMPTY_THRHD_MASK 0x70000000
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#define RX_MEM_FULL_THRHD_OFFSET 25
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#define RX_MEM_FULL_THRHD_MASK 0x0E000000
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#define UART_XOFF_THRESHOLD_H2_OFFSET 23
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#define UART_XOFF_THRESHOLD_H2_MASK 0x01800000
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#define UART_XON_THRESHOLD_H2_OFFSET 21
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#define UART_XON_THRESHOLD_H2_MASK 0x00600000
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#define RX_TOUT_THRHD_H3_OFFSET 18
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#define RX_TOUT_THRHD_H3_MASK 0x001C0000
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#define RX_FLOW_THRHD_H3_OFFSET 15
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#define RX_FLOW_THRHD_H3_MASK 0x00038000
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#define REG_TX_SIZE_OFFSET 8
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#define REG_TX_SIZE_MASK 0x00000F00
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#define REG_RX_SIZE_OFFSET 4
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#define REG_RX_SIZE_MASK 0x000000F0
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#define REG_MEM_PD_OFFSET 0
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#define REG_MEM_PD_MASK 0x00000001
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//HW module read/write macro
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#define APB_UART_READ_REG(addr) SOC_READ_REG(APB_UART0_BASEADDR + addr)
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#define APB_UART_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART0_BASEADDR + addr,value)
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#define APB_UART1_READ_REG(addr) SOC_READ_REG(APB_UART1_BASEADDR + addr)
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#define APB_UART1_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART1_BASEADDR + addr,value)
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#define APB_UART2_READ_REG(addr) SOC_READ_REG(APB_UART2_BASEADDR + addr)
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#define APB_UART2_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART2_BASEADDR + addr,value)
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#define APB_UART3_READ_REG(addr) SOC_READ_REG(APB_UART3_BASEADDR + addr)
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#define APB_UART3_WRITE_REG(addr,value) SOC_WRITE_REG(APB_UART3_BASEADDR + addr,value)
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