1656 lines
50 KiB
C
Executable File
1656 lines
50 KiB
C
Executable File
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//-----------------------------------
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#define CFG_SIG0_IN_CFG_ADDR 0x0
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#define SIG0_IN_CORE_SEL_OFFSET 12
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#define SIG0_IN_CORE_SEL_MASK 0x00001000
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#define SIG0_IN_DEF_SEL_OFFSET 8
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#define SIG0_IN_DEF_SEL_MASK 0x00000300
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#define SIG0_IN_GPIO_SEL_OFFSET 0
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#define SIG0_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG1_IN_CFG_ADDR 0x4
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#define SIG1_IN_CORE_SEL_OFFSET 12
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#define SIG1_IN_CORE_SEL_MASK 0x00001000
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#define SIG1_IN_DEF_SEL_OFFSET 8
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#define SIG1_IN_DEF_SEL_MASK 0x00000300
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#define SIG1_IN_GPIO_SEL_OFFSET 0
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#define SIG1_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG2_IN_CFG_ADDR 0x8
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#define SIG2_IN_CORE_SEL_OFFSET 12
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#define SIG2_IN_CORE_SEL_MASK 0x00001000
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#define SIG2_IN_DEF_SEL_OFFSET 8
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#define SIG2_IN_DEF_SEL_MASK 0x00000300
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#define SIG2_IN_GPIO_SEL_OFFSET 0
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#define SIG2_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG3_IN_CFG_ADDR 0xc
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#define SIG3_IN_CORE_SEL_OFFSET 12
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#define SIG3_IN_CORE_SEL_MASK 0x00001000
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#define SIG3_IN_DEF_SEL_OFFSET 8
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#define SIG3_IN_DEF_SEL_MASK 0x00000300
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#define SIG3_IN_GPIO_SEL_OFFSET 0
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#define SIG3_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG4_IN_CFG_ADDR 0x10
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#define SIG4_IN_CORE_SEL_OFFSET 12
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#define SIG4_IN_CORE_SEL_MASK 0x00001000
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#define SIG4_IN_DEF_SEL_OFFSET 8
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#define SIG4_IN_DEF_SEL_MASK 0x00000300
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#define SIG4_IN_GPIO_SEL_OFFSET 0
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#define SIG4_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG5_IN_CFG_ADDR 0x14
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#define SIG5_IN_CORE_SEL_OFFSET 12
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#define SIG5_IN_CORE_SEL_MASK 0x00001000
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#define SIG5_IN_DEF_SEL_OFFSET 8
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#define SIG5_IN_DEF_SEL_MASK 0x00000300
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#define SIG5_IN_GPIO_SEL_OFFSET 0
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#define SIG5_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG6_IN_CFG_ADDR 0x18
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#define SIG6_IN_CORE_SEL_OFFSET 12
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#define SIG6_IN_CORE_SEL_MASK 0x00001000
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#define SIG6_IN_DEF_SEL_OFFSET 8
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#define SIG6_IN_DEF_SEL_MASK 0x00000300
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#define SIG6_IN_GPIO_SEL_OFFSET 0
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#define SIG6_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG7_IN_CFG_ADDR 0x1c
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#define SIG7_IN_CORE_SEL_OFFSET 12
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#define SIG7_IN_CORE_SEL_MASK 0x00001000
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#define SIG7_IN_DEF_SEL_OFFSET 8
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#define SIG7_IN_DEF_SEL_MASK 0x00000300
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#define SIG7_IN_GPIO_SEL_OFFSET 0
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#define SIG7_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG8_IN_CFG_ADDR 0x20
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#define SIG8_IN_DEF_SEL_OFFSET 8
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#define SIG8_IN_DEF_SEL_MASK 0x00000300
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#define SIG8_IN_GPIO_SEL_OFFSET 0
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#define SIG8_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG9_IN_CFG_ADDR 0x24
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#define SIG9_IN_CORE_SEL_OFFSET 12
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#define SIG9_IN_CORE_SEL_MASK 0x00001000
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#define SIG9_IN_DEF_SEL_OFFSET 8
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#define SIG9_IN_DEF_SEL_MASK 0x00000300
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#define SIG9_IN_GPIO_SEL_OFFSET 0
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#define SIG9_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG10_IN_CFG_ADDR 0x28
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#define SIG10_IN_DEF_SEL_OFFSET 8
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#define SIG10_IN_DEF_SEL_MASK 0x00000300
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#define SIG10_IN_GPIO_SEL_OFFSET 0
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#define SIG10_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG11_IN_CFG_ADDR 0x2c
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#define SIG11_IN_DEF_SEL_OFFSET 8
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#define SIG11_IN_DEF_SEL_MASK 0x00000300
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#define SIG11_IN_GPIO_SEL_OFFSET 0
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#define SIG11_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG12_IN_CFG_ADDR 0x30
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#define SIG12_IN_DEF_SEL_OFFSET 8
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#define SIG12_IN_DEF_SEL_MASK 0x00000300
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#define SIG12_IN_GPIO_SEL_OFFSET 0
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#define SIG12_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG13_IN_CFG_ADDR 0x34
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#define SIG13_IN_DEF_SEL_OFFSET 8
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#define SIG13_IN_DEF_SEL_MASK 0x00000300
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#define SIG13_IN_GPIO_SEL_OFFSET 0
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#define SIG13_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG14_IN_CFG_ADDR 0x38
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#define SIG14_IN_DEF_SEL_OFFSET 8
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#define SIG14_IN_DEF_SEL_MASK 0x00000300
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#define SIG14_IN_GPIO_SEL_OFFSET 0
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#define SIG14_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG15_IN_CFG_ADDR 0x3c
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#define SIG15_IN_DEF_SEL_OFFSET 8
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#define SIG15_IN_DEF_SEL_MASK 0x00000300
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#define SIG15_IN_GPIO_SEL_OFFSET 0
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#define SIG15_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG16_IN_CFG_ADDR 0x40
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#define SIG16_IN_DEF_SEL_OFFSET 8
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#define SIG16_IN_DEF_SEL_MASK 0x00000300
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#define SIG16_IN_GPIO_SEL_OFFSET 0
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#define SIG16_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG17_IN_CFG_ADDR 0x44
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#define SIG17_IN_DEF_SEL_OFFSET 8
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#define SIG17_IN_DEF_SEL_MASK 0x00000300
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#define SIG17_IN_GPIO_SEL_OFFSET 0
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#define SIG17_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG18_IN_CFG_ADDR 0x48
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#define SIG18_IN_DEF_SEL_OFFSET 8
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#define SIG18_IN_DEF_SEL_MASK 0x00000300
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#define SIG18_IN_GPIO_SEL_OFFSET 0
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#define SIG18_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG19_IN_CFG_ADDR 0x4c
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#define SIG19_IN_DEF_SEL_OFFSET 8
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#define SIG19_IN_DEF_SEL_MASK 0x00000300
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#define SIG19_IN_GPIO_SEL_OFFSET 0
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#define SIG19_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG20_IN_CFG_ADDR 0x50
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#define SIG20_IN_DEF_SEL_OFFSET 8
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#define SIG20_IN_DEF_SEL_MASK 0x00000300
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#define SIG20_IN_GPIO_SEL_OFFSET 0
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#define SIG20_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG21_IN_CFG_ADDR 0x54
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#define SIG21_IN_DEF_SEL_OFFSET 8
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#define SIG21_IN_DEF_SEL_MASK 0x00000300
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#define SIG21_IN_GPIO_SEL_OFFSET 0
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#define SIG21_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG22_IN_CFG_ADDR 0x58
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#define SIG22_IN_DEF_SEL_OFFSET 8
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#define SIG22_IN_DEF_SEL_MASK 0x00000300
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#define SIG22_IN_GPIO_SEL_OFFSET 0
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#define SIG22_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG23_IN_CFG_ADDR 0x5c
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#define SIG23_IN_DEF_SEL_OFFSET 8
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#define SIG23_IN_DEF_SEL_MASK 0x00000300
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#define SIG23_IN_GPIO_SEL_OFFSET 0
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#define SIG23_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG24_IN_CFG_ADDR 0x60
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#define SIG24_IN_DEF_SEL_OFFSET 8
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#define SIG24_IN_DEF_SEL_MASK 0x00000300
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#define SIG24_IN_GPIO_SEL_OFFSET 0
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#define SIG24_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG25_IN_CFG_ADDR 0x64
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#define SIG25_IN_DEF_SEL_OFFSET 8
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#define SIG25_IN_DEF_SEL_MASK 0x00000300
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#define SIG25_IN_GPIO_SEL_OFFSET 0
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#define SIG25_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG26_IN_CFG_ADDR 0x68
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#define SIG26_IN_DEF_SEL_OFFSET 8
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#define SIG26_IN_DEF_SEL_MASK 0x00000300
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#define SIG26_IN_GPIO_SEL_OFFSET 0
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#define SIG26_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG27_IN_CFG_ADDR 0x6c
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#define SIG27_IN_DEF_SEL_OFFSET 8
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#define SIG27_IN_DEF_SEL_MASK 0x00000300
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#define SIG27_IN_GPIO_SEL_OFFSET 0
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#define SIG27_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG28_IN_CFG_ADDR 0x70
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#define SIG28_IN_DEF_SEL_OFFSET 8
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#define SIG28_IN_DEF_SEL_MASK 0x00000300
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#define SIG28_IN_GPIO_SEL_OFFSET 0
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#define SIG28_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG29_IN_CFG_ADDR 0x74
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#define SIG29_IN_DEF_SEL_OFFSET 8
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#define SIG29_IN_DEF_SEL_MASK 0x00000300
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#define SIG29_IN_GPIO_SEL_OFFSET 0
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#define SIG29_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG30_IN_CFG_ADDR 0x78
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#define SIG30_IN_DEF_SEL_OFFSET 8
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#define SIG30_IN_DEF_SEL_MASK 0x00000300
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#define SIG30_IN_GPIO_SEL_OFFSET 0
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#define SIG30_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG31_IN_CFG_ADDR 0x7c
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#define SIG31_IN_DEF_SEL_OFFSET 8
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#define SIG31_IN_DEF_SEL_MASK 0x00000300
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#define SIG31_IN_GPIO_SEL_OFFSET 0
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#define SIG31_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG32_IN_CFG_ADDR 0x80
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#define SIG32_IN_DEF_SEL_OFFSET 8
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#define SIG32_IN_DEF_SEL_MASK 0x00000300
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#define SIG32_IN_GPIO_SEL_OFFSET 0
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#define SIG32_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG33_IN_CFG_ADDR 0x84
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#define SIG33_IN_DEF_SEL_OFFSET 8
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#define SIG33_IN_DEF_SEL_MASK 0x00000300
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#define SIG33_IN_GPIO_SEL_OFFSET 0
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#define SIG33_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG34_IN_CFG_ADDR 0x88
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#define SIG34_IN_DEF_SEL_OFFSET 8
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#define SIG34_IN_DEF_SEL_MASK 0x00000300
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#define SIG34_IN_GPIO_SEL_OFFSET 0
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#define SIG34_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG35_IN_CFG_ADDR 0x8c
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#define SIG35_IN_DEF_SEL_OFFSET 8
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#define SIG35_IN_DEF_SEL_MASK 0x00000300
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#define SIG35_IN_GPIO_SEL_OFFSET 0
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#define SIG35_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG36_IN_CFG_ADDR 0x90
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#define SIG36_IN_DEF_SEL_OFFSET 8
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#define SIG36_IN_DEF_SEL_MASK 0x00000300
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#define SIG36_IN_GPIO_SEL_OFFSET 0
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#define SIG36_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG37_IN_CFG_ADDR 0x94
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#define SIG37_IN_DEF_SEL_OFFSET 8
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#define SIG37_IN_DEF_SEL_MASK 0x00000300
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#define SIG37_IN_GPIO_SEL_OFFSET 0
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#define SIG37_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG38_IN_CFG_ADDR 0x98
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#define SIG38_IN_DEF_SEL_OFFSET 8
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#define SIG38_IN_DEF_SEL_MASK 0x00000300
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#define SIG38_IN_GPIO_SEL_OFFSET 0
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#define SIG38_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG39_IN_CFG_ADDR 0x9c
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#define SIG39_IN_DEF_SEL_OFFSET 8
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#define SIG39_IN_DEF_SEL_MASK 0x00000300
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#define SIG39_IN_GPIO_SEL_OFFSET 0
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#define SIG39_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG40_IN_CFG_ADDR 0xa0
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#define SIG40_IN_DEF_SEL_OFFSET 8
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#define SIG40_IN_DEF_SEL_MASK 0x00000300
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#define SIG40_IN_GPIO_SEL_OFFSET 0
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#define SIG40_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG41_IN_CFG_ADDR 0xa4
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#define SIG41_IN_DEF_SEL_OFFSET 8
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#define SIG41_IN_DEF_SEL_MASK 0x00000300
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#define SIG41_IN_GPIO_SEL_OFFSET 0
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#define SIG41_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG42_IN_CFG_ADDR 0xa8
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#define SIG42_IN_DEF_SEL_OFFSET 8
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#define SIG42_IN_DEF_SEL_MASK 0x00000300
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#define SIG42_IN_GPIO_SEL_OFFSET 0
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#define SIG42_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG43_IN_CFG_ADDR 0xac
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#define SIG43_IN_DEF_SEL_OFFSET 8
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#define SIG43_IN_DEF_SEL_MASK 0x00000300
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#define SIG43_IN_GPIO_SEL_OFFSET 0
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#define SIG43_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG44_IN_CFG_ADDR 0xb0
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#define SIG44_IN_DEF_SEL_OFFSET 8
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#define SIG44_IN_DEF_SEL_MASK 0x00000300
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#define SIG44_IN_GPIO_SEL_OFFSET 0
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#define SIG44_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG45_IN_CFG_ADDR 0xb4
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#define SIG45_IN_DEF_SEL_OFFSET 8
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#define SIG45_IN_DEF_SEL_MASK 0x00000300
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#define SIG45_IN_GPIO_SEL_OFFSET 0
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#define SIG45_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG46_IN_CFG_ADDR 0xb8
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#define SIG46_IN_DEF_SEL_OFFSET 8
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#define SIG46_IN_DEF_SEL_MASK 0x00000300
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#define SIG46_IN_GPIO_SEL_OFFSET 0
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#define SIG46_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG47_IN_CFG_ADDR 0xbc
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#define SIG47_IN_DEF_SEL_OFFSET 8
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#define SIG47_IN_DEF_SEL_MASK 0x00000300
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#define SIG47_IN_GPIO_SEL_OFFSET 0
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#define SIG47_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG48_IN_CFG_ADDR 0xc0
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#define SIG48_IN_DEF_SEL_OFFSET 8
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#define SIG48_IN_DEF_SEL_MASK 0x00000300
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#define SIG48_IN_GPIO_SEL_OFFSET 0
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#define SIG48_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG49_IN_CFG_ADDR 0xc4
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#define SIG49_IN_DEF_SEL_OFFSET 8
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#define SIG49_IN_DEF_SEL_MASK 0x00000300
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#define SIG49_IN_GPIO_SEL_OFFSET 0
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#define SIG49_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG50_IN_CFG_ADDR 0xc8
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#define SIG50_IN_DEF_SEL_OFFSET 8
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#define SIG50_IN_DEF_SEL_MASK 0x00000300
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#define SIG50_IN_GPIO_SEL_OFFSET 0
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#define SIG50_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG51_IN_CFG_ADDR 0xcc
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#define SIG51_IN_DEF_SEL_OFFSET 8
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#define SIG51_IN_DEF_SEL_MASK 0x00000300
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#define SIG51_IN_GPIO_SEL_OFFSET 0
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#define SIG51_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG52_IN_CFG_ADDR 0xd0
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#define SIG52_IN_DEF_SEL_OFFSET 8
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#define SIG52_IN_DEF_SEL_MASK 0x00000300
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#define SIG52_IN_GPIO_SEL_OFFSET 0
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#define SIG52_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG53_IN_CFG_ADDR 0xd4
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#define SIG53_IN_DEF_SEL_OFFSET 8
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#define SIG53_IN_DEF_SEL_MASK 0x00000300
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#define SIG53_IN_GPIO_SEL_OFFSET 0
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#define SIG53_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG54_IN_CFG_ADDR 0xd8
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#define SIG54_IN_DEF_SEL_OFFSET 8
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#define SIG54_IN_DEF_SEL_MASK 0x00000300
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#define SIG54_IN_GPIO_SEL_OFFSET 0
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#define SIG54_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG55_IN_CFG_ADDR 0xdc
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#define SIG55_IN_DEF_SEL_OFFSET 8
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#define SIG55_IN_DEF_SEL_MASK 0x00000300
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#define SIG55_IN_GPIO_SEL_OFFSET 0
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#define SIG55_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG56_IN_CFG_ADDR 0xe0
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#define SIG56_IN_DEF_SEL_OFFSET 8
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#define SIG56_IN_DEF_SEL_MASK 0x00000300
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#define SIG56_IN_GPIO_SEL_OFFSET 0
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#define SIG56_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG57_IN_CFG_ADDR 0xe4
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#define SIG57_IN_DEF_SEL_OFFSET 8
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#define SIG57_IN_DEF_SEL_MASK 0x00000300
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#define SIG57_IN_GPIO_SEL_OFFSET 0
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#define SIG57_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG58_IN_CFG_ADDR 0xe8
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#define SIG58_IN_DEF_SEL_OFFSET 8
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#define SIG58_IN_DEF_SEL_MASK 0x00000300
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#define SIG58_IN_GPIO_SEL_OFFSET 0
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#define SIG58_IN_GPIO_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SIG59_IN_CFG_ADDR 0xec
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#define SIG59_IN_DEF_SEL_OFFSET 8
|
|
#define SIG59_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG59_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG59_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG60_IN_CFG_ADDR 0xf0
|
|
#define SIG60_IN_DEF_SEL_OFFSET 8
|
|
#define SIG60_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG60_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG60_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG61_IN_CFG_ADDR 0xf4
|
|
#define SIG61_IN_DEF_SEL_OFFSET 8
|
|
#define SIG61_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG61_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG61_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG62_IN_CFG_ADDR 0xf8
|
|
#define SIG62_IN_CORE_SEL_OFFSET 12
|
|
#define SIG62_IN_CORE_SEL_MASK 0x00001000
|
|
#define SIG62_IN_DEF_SEL_OFFSET 8
|
|
#define SIG62_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG62_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG62_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG63_IN_CFG_ADDR 0xfc
|
|
#define SIG63_IN_CORE_SEL_OFFSET 12
|
|
#define SIG63_IN_CORE_SEL_MASK 0x00001000
|
|
#define SIG63_IN_DEF_SEL_OFFSET 8
|
|
#define SIG63_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG63_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG63_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG64_IN_CFG_ADDR 0x100
|
|
#define SIG64_IN_CORE_SEL_OFFSET 12
|
|
#define SIG64_IN_CORE_SEL_MASK 0x00001000
|
|
#define SIG64_IN_DEF_SEL_OFFSET 8
|
|
#define SIG64_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG64_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG64_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG65_IN_CFG_ADDR 0x104
|
|
#define SIG65_IN_CORE_SEL_OFFSET 12
|
|
#define SIG65_IN_CORE_SEL_MASK 0x00001000
|
|
#define SIG65_IN_DEF_SEL_OFFSET 8
|
|
#define SIG65_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG65_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG65_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG66_IN_CFG_ADDR 0x108
|
|
#define SIG66_IN_DEF_SEL_OFFSET 8
|
|
#define SIG66_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG66_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG66_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG67_IN_CFG_ADDR 0x10c
|
|
#define SIG67_IN_DEF_SEL_OFFSET 8
|
|
#define SIG67_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG67_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG67_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG68_IN_CFG_ADDR 0x110
|
|
#define SIG68_IN_DEF_SEL_OFFSET 8
|
|
#define SIG68_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG68_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG68_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG69_IN_CFG_ADDR 0x114
|
|
#define SIG69_IN_DEF_SEL_OFFSET 8
|
|
#define SIG69_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG69_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG69_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG70_IN_CFG_ADDR 0x118
|
|
#define SIG70_IN_DEF_SEL_OFFSET 8
|
|
#define SIG70_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG70_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG70_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG71_IN_CFG_ADDR 0x11c
|
|
#define SIG71_IN_DEF_SEL_OFFSET 8
|
|
#define SIG71_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG71_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG71_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG72_IN_CFG_ADDR 0x120
|
|
#define SIG72_IN_DEF_SEL_OFFSET 8
|
|
#define SIG72_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG72_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG72_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG73_IN_CFG_ADDR 0x124
|
|
#define SIG73_IN_DEF_SEL_OFFSET 8
|
|
#define SIG73_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG73_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG73_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG74_IN_CFG_ADDR 0x128
|
|
#define SIG74_IN_DEF_SEL_OFFSET 8
|
|
#define SIG74_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG74_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG74_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG75_IN_CFG_ADDR 0x12c
|
|
#define SIG75_IN_DEF_SEL_OFFSET 8
|
|
#define SIG75_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG75_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG75_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG76_IN_CFG_ADDR 0x130
|
|
#define SIG76_IN_DEF_SEL_OFFSET 8
|
|
#define SIG76_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG76_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG76_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG77_IN_CFG_ADDR 0x134
|
|
#define SIG77_IN_DEF_SEL_OFFSET 8
|
|
#define SIG77_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG77_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG77_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG78_IN_CFG_ADDR 0x138
|
|
#define SIG78_IN_DEF_SEL_OFFSET 8
|
|
#define SIG78_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG78_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG78_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG79_IN_CFG_ADDR 0x13c
|
|
#define SIG79_IN_DEF_SEL_OFFSET 8
|
|
#define SIG79_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG79_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG79_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG80_IN_CFG_ADDR 0x140
|
|
#define SIG80_IN_DEF_SEL_OFFSET 8
|
|
#define SIG80_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG80_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG80_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG81_IN_CFG_ADDR 0x144
|
|
#define SIG81_IN_DEF_SEL_OFFSET 8
|
|
#define SIG81_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG81_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG81_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG82_IN_CFG_ADDR 0x148
|
|
#define SIG82_IN_DEF_SEL_OFFSET 8
|
|
#define SIG82_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG82_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG82_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG83_IN_CFG_ADDR 0x14c
|
|
#define SIG83_IN_DEF_SEL_OFFSET 8
|
|
#define SIG83_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG83_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG83_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG84_IN_CFG_ADDR 0x150
|
|
#define SIG84_IN_DEF_SEL_OFFSET 8
|
|
#define SIG84_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG84_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG84_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG85_IN_CFG_ADDR 0x154
|
|
#define SIG85_IN_DEF_SEL_OFFSET 8
|
|
#define SIG85_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG85_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG85_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG86_IN_CFG_ADDR 0x158
|
|
#define SIG86_IN_DEF_SEL_OFFSET 8
|
|
#define SIG86_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG86_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG86_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG87_IN_CFG_ADDR 0x15c
|
|
#define SIG87_IN_DEF_SEL_OFFSET 8
|
|
#define SIG87_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG87_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG87_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG88_IN_CFG_ADDR 0x160
|
|
#define SIG88_IN_DEF_SEL_OFFSET 8
|
|
#define SIG88_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG88_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG88_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG89_IN_CFG_ADDR 0x164
|
|
#define SIG89_IN_DEF_SEL_OFFSET 8
|
|
#define SIG89_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG89_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG89_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG90_IN_CFG_ADDR 0x168
|
|
#define SIG90_IN_DEF_SEL_OFFSET 8
|
|
#define SIG90_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG90_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG90_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG91_IN_CFG_ADDR 0x16c
|
|
#define SIG91_IN_DEF_SEL_OFFSET 8
|
|
#define SIG91_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG91_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG91_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG92_IN_CFG_ADDR 0x170
|
|
#define SIG92_IN_DEF_SEL_OFFSET 8
|
|
#define SIG92_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG92_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG92_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG93_IN_CFG_ADDR 0x174
|
|
#define SIG93_IN_DEF_SEL_OFFSET 8
|
|
#define SIG93_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG93_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG93_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG94_IN_CFG_ADDR 0x178
|
|
#define SIG94_IN_DEF_SEL_OFFSET 8
|
|
#define SIG94_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG94_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG94_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG95_IN_CFG_ADDR 0x17c
|
|
#define SIG95_IN_DEF_SEL_OFFSET 8
|
|
#define SIG95_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG95_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG95_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG96_IN_CFG_ADDR 0x180
|
|
#define SIG96_IN_DEF_SEL_OFFSET 8
|
|
#define SIG96_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG96_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG96_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG97_IN_CFG_ADDR 0x184
|
|
#define SIG97_IN_DEF_SEL_OFFSET 8
|
|
#define SIG97_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG97_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG97_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG98_IN_CFG_ADDR 0x188
|
|
#define SIG98_IN_DEF_SEL_OFFSET 8
|
|
#define SIG98_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG98_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG98_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG99_IN_CFG_ADDR 0x18c
|
|
#define SIG99_IN_DEF_SEL_OFFSET 8
|
|
#define SIG99_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG99_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG99_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG100_IN_CFG_ADDR 0x190
|
|
#define SIG100_IN_DEF_SEL_OFFSET 8
|
|
#define SIG100_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG100_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG100_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG101_IN_CFG_ADDR 0x194
|
|
#define SIG101_IN_DEF_SEL_OFFSET 8
|
|
#define SIG101_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG101_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG101_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG102_IN_CFG_ADDR 0x198
|
|
#define SIG102_IN_DEF_SEL_OFFSET 8
|
|
#define SIG102_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG102_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG102_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG103_IN_CFG_ADDR 0x19c
|
|
#define SIG103_IN_DEF_SEL_OFFSET 8
|
|
#define SIG103_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG103_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG103_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG104_IN_CFG_ADDR 0x1a0
|
|
#define SIG104_IN_DEF_SEL_OFFSET 8
|
|
#define SIG104_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG104_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG104_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG105_IN_CFG_ADDR 0x1a4
|
|
#define SIG105_IN_DEF_SEL_OFFSET 8
|
|
#define SIG105_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG105_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG105_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG106_IN_CFG_ADDR 0x1a8
|
|
#define SIG106_IN_DEF_SEL_OFFSET 8
|
|
#define SIG106_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG106_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG106_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG107_IN_CFG_ADDR 0x1ac
|
|
#define SIG107_IN_DEF_SEL_OFFSET 8
|
|
#define SIG107_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG107_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG107_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG108_IN_CFG_ADDR 0x1b0
|
|
#define SIG108_IN_DEF_SEL_OFFSET 8
|
|
#define SIG108_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG108_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG108_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SIG109_IN_CFG_ADDR 0x1b4
|
|
#define SIG109_IN_DEF_SEL_OFFSET 8
|
|
#define SIG109_IN_DEF_SEL_MASK 0x00000300
|
|
#define SIG109_IN_GPIO_SEL_OFFSET 0
|
|
#define SIG109_IN_GPIO_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO0_OUT_CFG_ADDR 0x400
|
|
#define GPIO0_OUT_SEL_OFFSET 0
|
|
#define GPIO0_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO1_OUT_CFG_ADDR 0x404
|
|
#define GPIO1_OUT_SEL_OFFSET 0
|
|
#define GPIO1_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO2_OUT_CFG_ADDR 0x408
|
|
#define GPIO2_OUT_SEL_OFFSET 0
|
|
#define GPIO2_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO3_OUT_CFG_ADDR 0x40c
|
|
#define GPIO3_OUT_SEL_OFFSET 0
|
|
#define GPIO3_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO4_OUT_CFG_ADDR 0x410
|
|
#define GPIO4_OUT_SEL_OFFSET 0
|
|
#define GPIO4_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO5_OUT_CFG_ADDR 0x414
|
|
#define GPIO5_OUT_SEL_OFFSET 0
|
|
#define GPIO5_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO6_OUT_CFG_ADDR 0x418
|
|
#define GPIO6_OUT_SEL_OFFSET 0
|
|
#define GPIO6_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO7_OUT_CFG_ADDR 0x41c
|
|
#define GPIO7_OUT_SEL_OFFSET 0
|
|
#define GPIO7_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO8_OUT_CFG_ADDR 0x420
|
|
#define GPIO8_OUT_SEL_OFFSET 0
|
|
#define GPIO8_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO9_OUT_CFG_ADDR 0x424
|
|
#define GPIO9_OUT_SEL_OFFSET 0
|
|
#define GPIO9_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO10_OUT_CFG_ADDR 0x428
|
|
#define GPIO10_OUT_SEL_OFFSET 0
|
|
#define GPIO10_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO11_OUT_CFG_ADDR 0x42c
|
|
#define GPIO11_OUT_SEL_OFFSET 0
|
|
#define GPIO11_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO12_OUT_CFG_ADDR 0x430
|
|
#define GPIO12_OUT_SEL_OFFSET 0
|
|
#define GPIO12_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO13_OUT_CFG_ADDR 0x434
|
|
#define GPIO13_OUT_SEL_OFFSET 0
|
|
#define GPIO13_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO14_OUT_CFG_ADDR 0x438
|
|
#define GPIO14_OUT_SEL_OFFSET 0
|
|
#define GPIO14_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO15_OUT_CFG_ADDR 0x43c
|
|
#define GPIO15_OUT_SEL_OFFSET 0
|
|
#define GPIO15_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO16_OUT_CFG_ADDR 0x440
|
|
#define GPIO16_OUT_SEL_OFFSET 0
|
|
#define GPIO16_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO17_OUT_CFG_ADDR 0x444
|
|
#define GPIO17_OUT_SEL_OFFSET 0
|
|
#define GPIO17_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO18_OUT_CFG_ADDR 0x448
|
|
#define GPIO18_OUT_SEL_OFFSET 0
|
|
#define GPIO18_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO19_OUT_CFG_ADDR 0x44c
|
|
#define GPIO19_OUT_SEL_OFFSET 0
|
|
#define GPIO19_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO20_OUT_CFG_ADDR 0x450
|
|
#define GPIO20_OUT_SEL_OFFSET 0
|
|
#define GPIO20_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO21_OUT_CFG_ADDR 0x454
|
|
#define GPIO21_OUT_SEL_OFFSET 0
|
|
#define GPIO21_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO22_OUT_CFG_ADDR 0x458
|
|
#define GPIO22_OUT_SEL_OFFSET 0
|
|
#define GPIO22_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO23_OUT_CFG_ADDR 0x45c
|
|
#define GPIO23_OUT_SEL_OFFSET 0
|
|
#define GPIO23_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO24_OUT_CFG_ADDR 0x460
|
|
#define GPIO24_OUT_SEL_OFFSET 0
|
|
#define GPIO24_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO25_OUT_CFG_ADDR 0x464
|
|
#define GPIO25_OUT_SEL_OFFSET 0
|
|
#define GPIO25_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO26_OUT_CFG_ADDR 0x468
|
|
#define GPIO26_OUT_SEL_OFFSET 0
|
|
#define GPIO26_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO27_OUT_CFG_ADDR 0x46c
|
|
#define GPIO27_OUT_SEL_OFFSET 0
|
|
#define GPIO27_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO28_OUT_CFG_ADDR 0x470
|
|
#define GPIO28_OUT_SEL_OFFSET 0
|
|
#define GPIO28_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO29_OUT_CFG_ADDR 0x474
|
|
#define GPIO29_OUT_SEL_OFFSET 0
|
|
#define GPIO29_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO30_OUT_CFG_ADDR 0x478
|
|
#define GPIO30_OUT_SEL_OFFSET 0
|
|
#define GPIO30_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO31_OUT_CFG_ADDR 0x47c
|
|
#define GPIO31_OUT_SEL_OFFSET 0
|
|
#define GPIO31_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO32_OUT_CFG_ADDR 0x480
|
|
#define GPIO32_OUT_SEL_OFFSET 0
|
|
#define GPIO32_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO33_OUT_CFG_ADDR 0x484
|
|
#define GPIO33_OUT_SEL_OFFSET 0
|
|
#define GPIO33_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO34_OUT_CFG_ADDR 0x488
|
|
#define GPIO34_OUT_SEL_OFFSET 0
|
|
#define GPIO34_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO35_OUT_CFG_ADDR 0x48c
|
|
#define GPIO35_OUT_SEL_OFFSET 0
|
|
#define GPIO35_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO36_OUT_CFG_ADDR 0x490
|
|
#define GPIO36_OUT_SEL_OFFSET 0
|
|
#define GPIO36_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO37_OUT_CFG_ADDR 0x494
|
|
#define GPIO37_OUT_SEL_OFFSET 0
|
|
#define GPIO37_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO38_OUT_CFG_ADDR 0x498
|
|
#define GPIO38_OUT_SEL_OFFSET 0
|
|
#define GPIO38_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO39_OUT_CFG_ADDR 0x49c
|
|
#define GPIO39_OUT_SEL_OFFSET 0
|
|
#define GPIO39_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO40_OUT_CFG_ADDR 0x4a0
|
|
#define GPIO40_OUT_SEL_OFFSET 0
|
|
#define GPIO40_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO41_OUT_CFG_ADDR 0x4a4
|
|
#define GPIO41_OUT_SEL_OFFSET 0
|
|
#define GPIO41_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO42_OUT_CFG_ADDR 0x4a8
|
|
#define GPIO42_OUT_SEL_OFFSET 0
|
|
#define GPIO42_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO43_OUT_CFG_ADDR 0x4ac
|
|
#define GPIO43_OUT_SEL_OFFSET 0
|
|
#define GPIO43_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO44_OUT_CFG_ADDR 0x4b0
|
|
#define GPIO44_OUT_SEL_OFFSET 0
|
|
#define GPIO44_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO45_OUT_CFG_ADDR 0x4b4
|
|
#define GPIO45_OUT_SEL_OFFSET 0
|
|
#define GPIO45_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO46_OUT_CFG_ADDR 0x4b8
|
|
#define GPIO46_OUT_SEL_OFFSET 0
|
|
#define GPIO46_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO47_OUT_CFG_ADDR 0x4bc
|
|
#define GPIO47_OUT_SEL_OFFSET 0
|
|
#define GPIO47_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO48_OUT_CFG_ADDR 0x4c0
|
|
#define GPIO48_OUT_SEL_OFFSET 0
|
|
#define GPIO48_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO49_OUT_CFG_ADDR 0x4c4
|
|
#define GPIO49_OUT_SEL_OFFSET 0
|
|
#define GPIO49_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO50_OUT_CFG_ADDR 0x4c8
|
|
#define GPIO50_OUT_SEL_OFFSET 0
|
|
#define GPIO50_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO51_OUT_CFG_ADDR 0x4cc
|
|
#define GPIO51_OUT_SEL_OFFSET 0
|
|
#define GPIO51_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO52_OUT_CFG_ADDR 0x4d0
|
|
#define GPIO52_OUT_SEL_OFFSET 0
|
|
#define GPIO52_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO53_OUT_CFG_ADDR 0x4d4
|
|
#define GPIO53_OUT_SEL_OFFSET 0
|
|
#define GPIO53_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO54_OUT_CFG_ADDR 0x4d8
|
|
#define GPIO54_OUT_SEL_OFFSET 0
|
|
#define GPIO54_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO55_OUT_CFG_ADDR 0x4dc
|
|
#define GPIO55_OUT_SEL_OFFSET 0
|
|
#define GPIO55_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO56_OUT_CFG_ADDR 0x4e0
|
|
#define GPIO56_OUT_SEL_OFFSET 0
|
|
#define GPIO56_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO57_OUT_CFG_ADDR 0x4e4
|
|
#define GPIO57_OUT_SEL_OFFSET 0
|
|
#define GPIO57_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO58_OUT_CFG_ADDR 0x4e8
|
|
#define GPIO58_OUT_SEL_OFFSET 0
|
|
#define GPIO58_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO59_OUT_CFG_ADDR 0x4ec
|
|
#define GPIO59_OUT_SEL_OFFSET 0
|
|
#define GPIO59_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO60_OUT_CFG_ADDR 0x4f0
|
|
#define GPIO60_OUT_SEL_OFFSET 0
|
|
#define GPIO60_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO61_OUT_CFG_ADDR 0x4f4
|
|
#define GPIO61_OUT_SEL_OFFSET 0
|
|
#define GPIO61_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO62_OUT_CFG_ADDR 0x4f8
|
|
#define GPIO62_OUT_SEL_OFFSET 0
|
|
#define GPIO62_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO63_OUT_CFG_ADDR 0x4fc
|
|
#define GPIO63_OUT_SEL_OFFSET 0
|
|
#define GPIO63_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO64_OUT_CFG_ADDR 0x500
|
|
#define GPIO64_OUT_SEL_OFFSET 0
|
|
#define GPIO64_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO65_OUT_CFG_ADDR 0x504
|
|
#define GPIO65_OUT_SEL_OFFSET 0
|
|
#define GPIO65_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO66_OUT_CFG_ADDR 0x508
|
|
#define GPIO66_OUT_SEL_OFFSET 0
|
|
#define GPIO66_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO67_OUT_CFG_ADDR 0x50c
|
|
#define GPIO67_OUT_SEL_OFFSET 0
|
|
#define GPIO67_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO68_OUT_CFG_ADDR 0x510
|
|
#define GPIO68_OUT_SEL_OFFSET 0
|
|
#define GPIO68_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO69_OUT_CFG_ADDR 0x514
|
|
#define GPIO69_OUT_SEL_OFFSET 0
|
|
#define GPIO69_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO70_OUT_CFG_ADDR 0x518
|
|
#define GPIO70_OUT_SEL_OFFSET 0
|
|
#define GPIO70_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO71_OUT_CFG_ADDR 0x51c
|
|
#define GPIO71_OUT_SEL_OFFSET 0
|
|
#define GPIO71_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO72_OUT_CFG_ADDR 0x520
|
|
#define GPIO72_OUT_SEL_OFFSET 0
|
|
#define GPIO72_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO73_OUT_CFG_ADDR 0x524
|
|
#define GPIO73_OUT_SEL_OFFSET 0
|
|
#define GPIO73_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO74_OUT_CFG_ADDR 0x528
|
|
#define GPIO74_OUT_SEL_OFFSET 0
|
|
#define GPIO74_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO75_OUT_CFG_ADDR 0x52c
|
|
#define GPIO75_OUT_SEL_OFFSET 0
|
|
#define GPIO75_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO76_OUT_CFG_ADDR 0x530
|
|
#define GPIO76_OUT_SEL_OFFSET 0
|
|
#define GPIO76_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO77_OUT_CFG_ADDR 0x534
|
|
#define GPIO77_OUT_SEL_OFFSET 0
|
|
#define GPIO77_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO78_OUT_CFG_ADDR 0x538
|
|
#define GPIO78_OUT_SEL_OFFSET 0
|
|
#define GPIO78_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO79_OUT_CFG_ADDR 0x53c
|
|
#define GPIO79_OUT_SEL_OFFSET 0
|
|
#define GPIO79_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO80_OUT_CFG_ADDR 0x540
|
|
#define GPIO80_OUT_SEL_OFFSET 0
|
|
#define GPIO80_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO81_OUT_CFG_ADDR 0x544
|
|
#define GPIO81_OUT_SEL_OFFSET 0
|
|
#define GPIO81_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO82_OUT_CFG_ADDR 0x548
|
|
#define GPIO82_OUT_SEL_OFFSET 0
|
|
#define GPIO82_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO83_OUT_CFG_ADDR 0x54c
|
|
#define GPIO83_OUT_SEL_OFFSET 0
|
|
#define GPIO83_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO84_OUT_CFG_ADDR 0x550
|
|
#define GPIO84_OUT_SEL_OFFSET 0
|
|
#define GPIO84_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO85_OUT_CFG_ADDR 0x554
|
|
#define GPIO85_OUT_SEL_OFFSET 0
|
|
#define GPIO85_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO86_OUT_CFG_ADDR 0x558
|
|
#define GPIO86_OUT_SEL_OFFSET 0
|
|
#define GPIO86_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO87_OUT_CFG_ADDR 0x55c
|
|
#define GPIO87_OUT_SEL_OFFSET 0
|
|
#define GPIO87_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO88_OUT_CFG_ADDR 0x560
|
|
#define GPIO88_OUT_SEL_OFFSET 0
|
|
#define GPIO88_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO89_OUT_CFG_ADDR 0x564
|
|
#define GPIO89_OUT_SEL_OFFSET 0
|
|
#define GPIO89_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO90_OUT_CFG_ADDR 0x568
|
|
#define GPIO90_OUT_SEL_OFFSET 0
|
|
#define GPIO90_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO91_OUT_CFG_ADDR 0x56c
|
|
#define GPIO91_OUT_SEL_OFFSET 0
|
|
#define GPIO91_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO92_OUT_CFG_ADDR 0x570
|
|
#define GPIO92_OUT_SEL_OFFSET 0
|
|
#define GPIO92_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO93_OUT_CFG_ADDR 0x574
|
|
#define GPIO93_OUT_SEL_OFFSET 0
|
|
#define GPIO93_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO94_OUT_CFG_ADDR 0x578
|
|
#define GPIO94_OUT_SEL_OFFSET 0
|
|
#define GPIO94_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO95_OUT_CFG_ADDR 0x57c
|
|
#define GPIO95_OUT_SEL_OFFSET 0
|
|
#define GPIO95_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO96_OUT_CFG_ADDR 0x580
|
|
#define GPIO96_OUT_SEL_OFFSET 0
|
|
#define GPIO96_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO97_OUT_CFG_ADDR 0x584
|
|
#define GPIO97_OUT_SEL_OFFSET 0
|
|
#define GPIO97_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO98_OUT_CFG_ADDR 0x588
|
|
#define GPIO98_OUT_SEL_OFFSET 0
|
|
#define GPIO98_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO99_OUT_CFG_ADDR 0x58c
|
|
#define GPIO99_OUT_SEL_OFFSET 0
|
|
#define GPIO99_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO100_OUT_CFG_ADDR 0x590
|
|
#define GPIO100_OUT_SEL_OFFSET 0
|
|
#define GPIO100_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO101_OUT_CFG_ADDR 0x594
|
|
#define GPIO101_OUT_SEL_OFFSET 0
|
|
#define GPIO101_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO102_OUT_CFG_ADDR 0x598
|
|
#define GPIO102_OUT_SEL_OFFSET 0
|
|
#define GPIO102_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO103_OUT_CFG_ADDR 0x59c
|
|
#define GPIO103_OUT_SEL_OFFSET 0
|
|
#define GPIO103_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO104_OUT_CFG_ADDR 0x5a0
|
|
#define GPIO104_OUT_SEL_OFFSET 0
|
|
#define GPIO104_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO105_OUT_CFG_ADDR 0x5a4
|
|
#define GPIO105_OUT_SEL_OFFSET 0
|
|
#define GPIO105_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO106_OUT_CFG_ADDR 0x5a8
|
|
#define GPIO106_OUT_SEL_OFFSET 0
|
|
#define GPIO106_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO107_OUT_CFG_ADDR 0x5ac
|
|
#define GPIO107_OUT_SEL_OFFSET 0
|
|
#define GPIO107_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO108_OUT_CFG_ADDR 0x5b0
|
|
#define GPIO108_OUT_SEL_OFFSET 0
|
|
#define GPIO108_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO109_OUT_CFG_ADDR 0x5b4
|
|
#define GPIO109_OUT_SEL_OFFSET 0
|
|
#define GPIO109_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO110_OUT_CFG_ADDR 0x5b8
|
|
#define GPIO110_OUT_SEL_OFFSET 0
|
|
#define GPIO110_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO111_OUT_CFG_ADDR 0x5bc
|
|
#define GPIO111_OUT_SEL_OFFSET 0
|
|
#define GPIO111_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO112_OUT_CFG_ADDR 0x5c0
|
|
#define GPIO112_OUT_SEL_OFFSET 0
|
|
#define GPIO112_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO113_OUT_CFG_ADDR 0x5c4
|
|
#define GPIO113_OUT_SEL_OFFSET 0
|
|
#define GPIO113_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO114_OUT_CFG_ADDR 0x5c8
|
|
#define GPIO114_OUT_SEL_OFFSET 0
|
|
#define GPIO114_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO115_OUT_CFG_ADDR 0x5cc
|
|
#define GPIO115_OUT_SEL_OFFSET 0
|
|
#define GPIO115_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO116_OUT_CFG_ADDR 0x5d0
|
|
#define GPIO116_OUT_SEL_OFFSET 0
|
|
#define GPIO116_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO117_OUT_CFG_ADDR 0x5d4
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#define GPIO117_OUT_SEL_OFFSET 0
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#define GPIO117_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO118_OUT_CFG_ADDR 0x5d8
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#define GPIO118_OUT_SEL_OFFSET 0
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#define GPIO118_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO119_OUT_CFG_ADDR 0x5dc
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#define GPIO119_OUT_SEL_OFFSET 0
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#define GPIO119_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO120_OUT_CFG_ADDR 0x5e0
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#define GPIO120_OUT_SEL_OFFSET 0
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#define GPIO120_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO121_OUT_CFG_ADDR 0x5e4
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#define GPIO121_OUT_SEL_OFFSET 0
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#define GPIO121_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO122_OUT_CFG_ADDR 0x5e8
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#define GPIO122_OUT_SEL_OFFSET 0
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#define GPIO122_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO123_OUT_CFG_ADDR 0x5ec
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#define GPIO123_OUT_SEL_OFFSET 0
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#define GPIO123_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO124_OUT_CFG_ADDR 0x5f0
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#define GPIO124_OUT_SEL_OFFSET 0
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#define GPIO124_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO125_OUT_CFG_ADDR 0x5f4
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#define GPIO125_OUT_SEL_OFFSET 0
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#define GPIO125_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO126_OUT_CFG_ADDR 0x5f8
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#define GPIO126_OUT_SEL_OFFSET 0
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#define GPIO126_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO127_OUT_CFG_ADDR 0x5fc
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#define GPIO127_OUT_SEL_OFFSET 0
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#define GPIO127_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO128_OUT_CFG_ADDR 0x600
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#define GPIO128_OUT_SEL_OFFSET 0
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#define GPIO128_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO129_OUT_CFG_ADDR 0x604
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#define GPIO129_OUT_SEL_OFFSET 0
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#define GPIO129_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO130_OUT_CFG_ADDR 0x608
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#define GPIO130_OUT_SEL_OFFSET 0
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#define GPIO130_OUT_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GPIO131_OUT_CFG_ADDR 0x60c
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#define GPIO131_OUT_SEL_OFFSET 0
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#define GPIO131_OUT_SEL_MASK 0x000000FF
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|
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//-----------------------------------
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#define CFG_GPIO132_OUT_CFG_ADDR 0x610
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#define GPIO132_OUT_SEL_OFFSET 0
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#define GPIO132_OUT_SEL_MASK 0x000000FF
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|
|
|
//-----------------------------------
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#define CFG_GPIO133_OUT_CFG_ADDR 0x614
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#define GPIO133_OUT_SEL_OFFSET 0
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#define GPIO133_OUT_SEL_MASK 0x000000FF
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|
|
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//-----------------------------------
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#define CFG_GPIO134_OUT_CFG_ADDR 0x618
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#define GPIO134_OUT_SEL_OFFSET 0
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#define GPIO134_OUT_SEL_MASK 0x000000FF
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|
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//-----------------------------------
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|
#define CFG_GPIO135_OUT_CFG_ADDR 0x61c
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#define GPIO135_OUT_SEL_OFFSET 0
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|
#define GPIO135_OUT_SEL_MASK 0x000000FF
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|
|
|
//-----------------------------------
|
|
#define CFG_GPIO136_OUT_CFG_ADDR 0x620
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|
#define GPIO136_OUT_SEL_OFFSET 0
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|
#define GPIO136_OUT_SEL_MASK 0x000000FF
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|
|
|
//-----------------------------------
|
|
#define CFG_GPIO137_OUT_CFG_ADDR 0x624
|
|
#define GPIO137_OUT_SEL_OFFSET 0
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|
#define GPIO137_OUT_SEL_MASK 0x000000FF
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|
|
|
//-----------------------------------
|
|
#define CFG_GPIO138_OUT_CFG_ADDR 0x628
|
|
#define GPIO138_OUT_SEL_OFFSET 0
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|
#define GPIO138_OUT_SEL_MASK 0x000000FF
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|
|
|
//-----------------------------------
|
|
#define CFG_GPIO139_OUT_CFG_ADDR 0x62c
|
|
#define GPIO139_OUT_SEL_OFFSET 0
|
|
#define GPIO139_OUT_SEL_MASK 0x000000FF
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|
|
|
//-----------------------------------
|
|
#define CFG_GPIO140_OUT_CFG_ADDR 0x630
|
|
#define GPIO140_OUT_SEL_OFFSET 0
|
|
#define GPIO140_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO141_OUT_CFG_ADDR 0x634
|
|
#define GPIO141_OUT_SEL_OFFSET 0
|
|
#define GPIO141_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO142_OUT_CFG_ADDR 0x638
|
|
#define GPIO142_OUT_SEL_OFFSET 0
|
|
#define GPIO142_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO143_OUT_CFG_ADDR 0x63c
|
|
#define GPIO143_OUT_SEL_OFFSET 0
|
|
#define GPIO143_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO144_OUT_CFG_ADDR 0x640
|
|
#define GPIO144_OUT_SEL_OFFSET 0
|
|
#define GPIO144_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO145_OUT_CFG_ADDR 0x644
|
|
#define GPIO145_OUT_SEL_OFFSET 0
|
|
#define GPIO145_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO146_OUT_CFG_ADDR 0x648
|
|
#define GPIO146_OUT_SEL_OFFSET 0
|
|
#define GPIO146_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO147_OUT_CFG_ADDR 0x64c
|
|
#define GPIO147_OUT_SEL_OFFSET 0
|
|
#define GPIO147_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO148_OUT_CFG_ADDR 0x650
|
|
#define GPIO148_OUT_SEL_OFFSET 0
|
|
#define GPIO148_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO149_OUT_CFG_ADDR 0x654
|
|
#define GPIO149_OUT_SEL_OFFSET 0
|
|
#define GPIO149_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO150_OUT_CFG_ADDR 0x658
|
|
#define GPIO150_OUT_SEL_OFFSET 0
|
|
#define GPIO150_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO151_OUT_CFG_ADDR 0x65c
|
|
#define GPIO151_OUT_SEL_OFFSET 0
|
|
#define GPIO151_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO152_OUT_CFG_ADDR 0x660
|
|
#define GPIO152_OUT_SEL_OFFSET 0
|
|
#define GPIO152_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO153_OUT_CFG_ADDR 0x664
|
|
#define GPIO153_OUT_SEL_OFFSET 0
|
|
#define GPIO153_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO154_OUT_CFG_ADDR 0x668
|
|
#define GPIO154_OUT_SEL_OFFSET 0
|
|
#define GPIO154_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO155_OUT_CFG_ADDR 0x66c
|
|
#define GPIO155_OUT_SEL_OFFSET 0
|
|
#define GPIO155_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO156_OUT_CFG_ADDR 0x670
|
|
#define GPIO156_OUT_SEL_OFFSET 0
|
|
#define GPIO156_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO157_OUT_CFG_ADDR 0x674
|
|
#define GPIO157_OUT_SEL_OFFSET 0
|
|
#define GPIO157_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO158_OUT_CFG_ADDR 0x678
|
|
#define GPIO158_OUT_SEL_OFFSET 0
|
|
#define GPIO158_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO159_OUT_CFG_ADDR 0x67c
|
|
#define GPIO159_OUT_SEL_OFFSET 0
|
|
#define GPIO159_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO160_OUT_CFG_ADDR 0x680
|
|
#define GPIO160_OUT_SEL_OFFSET 0
|
|
#define GPIO160_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO161_OUT_CFG_ADDR 0x684
|
|
#define GPIO161_OUT_SEL_OFFSET 0
|
|
#define GPIO161_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO162_OUT_CFG_ADDR 0x688
|
|
#define GPIO162_OUT_SEL_OFFSET 0
|
|
#define GPIO162_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO163_OUT_CFG_ADDR 0x68c
|
|
#define GPIO163_OUT_SEL_OFFSET 0
|
|
#define GPIO163_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO164_OUT_CFG_ADDR 0x690
|
|
#define GPIO164_OUT_SEL_OFFSET 0
|
|
#define GPIO164_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO165_OUT_CFG_ADDR 0x694
|
|
#define GPIO165_OUT_SEL_OFFSET 0
|
|
#define GPIO165_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO166_OUT_CFG_ADDR 0x698
|
|
#define GPIO166_OUT_SEL_OFFSET 0
|
|
#define GPIO166_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO167_OUT_CFG_ADDR 0x69c
|
|
#define GPIO167_OUT_SEL_OFFSET 0
|
|
#define GPIO167_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO168_OUT_CFG_ADDR 0x6a0
|
|
#define GPIO168_OUT_SEL_OFFSET 0
|
|
#define GPIO168_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO169_OUT_CFG_ADDR 0x6a4
|
|
#define GPIO169_OUT_SEL_OFFSET 0
|
|
#define GPIO169_OUT_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO170_OUT_CFG_ADDR 0x6a8
|
|
#define GPIO170_OUT_SEL_OFFSET 0
|
|
#define GPIO170_OUT_SEL_MASK 0x000000FF
|
|
|
|
//HW module read/write macro
|
|
#define GPIO_MTX_READ_REG(addr) SOC_READ_REG(GPIO_MTX_BASEADDR + addr)
|
|
#define GPIO_MTX_WRITE_REG(addr,value) SOC_WRITE_REG(GPIO_MTX_BASEADDR + addr,value)
|