826 lines
29 KiB
C
Executable File
826 lines
29 KiB
C
Executable File
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//-----------------------------------
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#define CFG_PMU_CLK_ENABLE_ADDR 0x0000
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#define WDG_DTOP_EB_OFFSET 30
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#define WDG_DTOP_EB_MASK 0x40000000
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#define EFUSE_EB_OFFSET 29
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#define EFUSE_EB_MASK 0x20000000
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#define ANTI_ATTACK_EB_OFFSET 17
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#define ANTI_ATTACK_EB_MASK 0x00020000
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#define SPWM_EB_OFFSET 16
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#define SPWM_EB_MASK 0x00010000
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#define PMU_ANAREG_EB_OFFSET 7
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#define PMU_ANAREG_EB_MASK 0x00000080
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#define PMU_WDG_EB_OFFSET 6
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#define PMU_WDG_EB_MASK 0x00000040
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#define GPIO_TOPA_EB_OFFSET 5
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#define GPIO_TOPA_EB_MASK 0x00000020
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#define IO_MUXA_EB_OFFSET 4
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#define IO_MUXA_EB_MASK 0x00000010
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#define RTC_TMR_EB_OFFSET 3
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#define RTC_TMR_EB_MASK 0x00000008
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#define I2C_EB_OFFSET 2
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#define I2C_EB_MASK 0x00000004
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#define INTC_EB_OFFSET 1
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#define INTC_EB_MASK 0x00000002
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#define GTMR_EB_OFFSET 0
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#define GTMR_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_SOFT_RESET_ADDR 0x0004
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#define PMU_SOFT_RST_OFFSET 31
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#define PMU_SOFT_RST_MASK 0x80000000
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#define WDG_DTOP_SOFT_RST_OFFSET 30
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#define WDG_DTOP_SOFT_RST_MASK 0x40000000
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#define ANTI_ATTACK_SOFT_RST_OFFSET 17
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#define ANTI_ATTACK_SOFT_RST_MASK 0x00020000
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#define SADC_PWM_SOFT_RST_OFFSET 16
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#define SADC_PWM_SOFT_RST_MASK 0x00010000
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#define SADC_CH2_SOFT_RST_OFFSET 15
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#define SADC_CH2_SOFT_RST_MASK 0x00008000
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#define SADC_CH1_SOFT_RST_OFFSET 14
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#define SADC_CH1_SOFT_RST_MASK 0x00004000
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#define MIPIPLL_LOCK_SOFT_RST_OFFSET 13
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#define MIPIPLL_LOCK_SOFT_RST_MASK 0x00002000
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#define MIPIVCO_CALIB_SOFT_RST_OFFSET 12
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#define MIPIVCO_CALIB_SOFT_RST_MASK 0x00001000
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#define PLL_LOCK_SOFT_RST_OFFSET 11
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#define PLL_LOCK_SOFT_RST_MASK 0x00000800
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#define VCO_CALIB_SOFT_RST_OFFSET 10
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#define VCO_CALIB_SOFT_RST_MASK 0x00000400
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#define DTOP_SOFT_RST_OFFSET 9
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#define DTOP_SOFT_RST_MASK 0x00000200
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#define PCORE_CPU_SOFT_RST_OFFSET 8
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#define PCORE_CPU_SOFT_RST_MASK 0x00000100
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#define PMU_ANAREG_SOFT_RST_OFFSET 7
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#define PMU_ANAREG_SOFT_RST_MASK 0x00000080
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#define PMU_WDG_SOFT_RST_OFFSET 6
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#define PMU_WDG_SOFT_RST_MASK 0x00000040
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#define GPIO_TOPA_SOFT_RST_OFFSET 5
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#define GPIO_TOPA_SOFT_RST_MASK 0x00000020
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#define IO_MUXA_SOFT_RST_OFFSET 4
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#define IO_MUXA_SOFT_RST_MASK 0x00000010
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#define RTC_TMR_SOFT_RST_OFFSET 3
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#define RTC_TMR_SOFT_RST_MASK 0x00000008
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#define I2C_SOFT_RST_OFFSET 2
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#define I2C_SOFT_RST_MASK 0x00000004
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#define INTC_SOFT_RST_OFFSET 1
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#define INTC_SOFT_RST_MASK 0x00000002
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#define GTMR_SOFT_RST_OFFSET 0
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#define GTMR_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_CLK_FORCE_ON_ADDR 0x0008
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#define PMU_FUNCTST_FORCE_EB_OFFSET 3
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#define PMU_FUNCTST_FORCE_EB_MASK 0x00000008
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#define RAM_16K_CLK_FORCE_ON_OFFSET 2
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#define RAM_16K_CLK_FORCE_ON_MASK 0x00000004
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#define RAM_2K_CLK_FORCE_ON_OFFSET 1
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#define RAM_2K_CLK_FORCE_ON_MASK 0x00000002
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#define PMU_ROM_FORCE_ON_OFFSET 0
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#define PMU_ROM_FORCE_ON_MASK 0x00000001
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//-----------------------------------
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#define CFG_RAM_16KB_LP_CTRL_ADDR 0x000C
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#define RAM_16K_ISO_OFFSET 12
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#define RAM_16K_ISO_MASK 0x00001000
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#define RAM_16K_LS_OFFSET 8
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#define RAM_16K_LS_MASK 0x00000100
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#define RAM_16K_DS_AUTO_EN_OFFSET 5
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#define RAM_16K_DS_AUTO_EN_MASK 0x00000020
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#define RAM_16K_DS_OFFSET 4
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#define RAM_16K_DS_MASK 0x00000010
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#define RAM_16K_SD_OFFSET 0
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#define RAM_16K_SD_MASK 0x00000001
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//-----------------------------------
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#define CFG_RAM_2KB_LP_CTRL_ADDR 0x0010
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#define RAM_2K_LS_OFFSET 8
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#define RAM_2K_LS_MASK 0x00000100
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#define RAM_2K_DS_AUTO_EN_OFFSET 5
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#define RAM_2K_DS_AUTO_EN_MASK 0x00000020
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#define RAM_2K_DS_OFFSET 4
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#define RAM_2K_DS_MASK 0x00000010
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#define RAM_2K_SD_OFFSET 0
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#define RAM_2K_SD_MASK 0x00000001
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//-----------------------------------
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#define CFG_DTOP_CPU1_BOOT_ADDR_ADDR 0x0014
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#define DTOP_CPU1_BOOT_ADDR_OFFSET 0
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#define DTOP_CPU1_BOOT_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PMU_CORE_FSM_CFG0_ADDR 0x0018
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#define PMU_CORE_CGM_ON_DLY_OFFSET 24
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#define PMU_CORE_CGM_ON_DLY_MASK 0xFF000000
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#define PMU_CORE_CGM_OFF_DLY_OFFSET 16
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#define PMU_CORE_CGM_OFF_DLY_MASK 0x00FF0000
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#define PMU_CORE_RST_ASSERT_DLY_OFFSET 8
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#define PMU_CORE_RST_ASSERT_DLY_MASK 0x0000FF00
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#define PMU_CORE_SHUTDOWN_DLY_OFFSET 0
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#define PMU_CORE_SHUTDOWN_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_CORE_FSM_CFG1_ADDR 0x001c
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#define PMU_CORE_PWR_ON_SEQ_DLY_OFFSET 24
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#define PMU_CORE_PWR_ON_SEQ_DLY_MASK 0xFF000000
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#define PMU_CORE_PWR_ON_DLY_OFFSET 16
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#define PMU_CORE_PWR_ON_DLY_MASK 0x00FF0000
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#define PMU_CORE_RST_DEASSERT_DLY_OFFSET 8
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#define PMU_CORE_RST_DEASSERT_DLY_MASK 0x0000FF00
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#define PMU_CORE_ISO_OFF_DLY_OFFSET 0
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#define PMU_CORE_ISO_OFF_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_CORE_FSM_CFG2_ADDR 0x0020
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#define PMU_CORE_CLK_AUTO_GATE_OFFSET 20
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#define PMU_CORE_CLK_AUTO_GATE_MASK 0x00100000
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#define PMU_CORE_ISO_ON_DLY_OFFSET 0
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#define PMU_CORE_ISO_ON_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_DIG_FSM_CFG0_ADDR 0x0024
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#define PMU_DIG_CGM_ON_DLY_OFFSET 24
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#define PMU_DIG_CGM_ON_DLY_MASK 0xFF000000
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#define PMU_DIG_CGM_OFF_DLY_OFFSET 16
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#define PMU_DIG_CGM_OFF_DLY_MASK 0x00FF0000
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#define PMU_DIG_RST_ASSERT_DLY_OFFSET 8
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#define PMU_DIG_RST_ASSERT_DLY_MASK 0x0000FF00
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#define PMU_DIG_SHUTDOWN_DLY_OFFSET 0
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#define PMU_DIG_SHUTDOWN_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_DIG_FSM_CFG1_ADDR 0x0028
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#define PMU_DIG_PWR_ON_SEQ_DLY_OFFSET 24
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#define PMU_DIG_PWR_ON_SEQ_DLY_MASK 0xFF000000
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#define PMU_DIG_PWR_ON_DLY_OFFSET 16
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#define PMU_DIG_PWR_ON_DLY_MASK 0x00FF0000
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#define PMU_DIG_RST_DEASSERT_DLY_OFFSET 8
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#define PMU_DIG_RST_DEASSERT_DLY_MASK 0x0000FF00
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#define PMU_DIG_ISO_OFF_DLY_OFFSET 0
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#define PMU_DIG_ISO_OFF_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_DIG_FSM_CFG2_ADDR 0x002C
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#define PMU_DIG_CLK_AUTO_GATE_OFFSET 20
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#define PMU_DIG_CLK_AUTO_GATE_MASK 0x00100000
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#define PMU_DIG_SLP_POWOFF_AUTO_EN_OFFSET 16
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#define PMU_DIG_SLP_POWOFF_AUTO_EN_MASK 0x00010000
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#define PMU_DIG_POW_FORCE_PD_OFFSET 8
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#define PMU_DIG_POW_FORCE_PD_MASK 0x00000100
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#define PMU_DIG_ISO_ON_DLY_OFFSET 0
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#define PMU_DIG_ISO_ON_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_TOP_FSM_CFG_ADDR 0x0030
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#define PMU_TOP_ST_CLK_DIV_CFG_OFFSET 0
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#define PMU_TOP_ST_CLK_DIV_CFG_MASK 0x000003FF
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//-----------------------------------
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#define CFG_FDMA_STATUS_ADDR 0x0034
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#define PMU_FDMA_AHB_FSM_OFFSET 4
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#define PMU_FDMA_AHB_FSM_MASK 0x00000070
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#define PMU_FDMA_IO_MODE_OFFSET 0
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#define PMU_FDMA_IO_MODE_MASK 0x00000007
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//-----------------------------------
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#define CFG_PMU_CLOCK_CFG_ADDR 0x0038
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#define CLK_32K_SEL_OFFSET 14
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#define CLK_32K_SEL_MASK 0x00004000
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#define CGM_DIV_CLK_1M_OFFSET 9
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#define CGM_DIV_CLK_1M_MASK 0x00003E00
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#define PMU_CLK_DIV_OFFSET 5
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#define PMU_CLK_DIV_MASK 0x000001E0
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#define CLK_1M_SEL_OFFSET 4
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#define CLK_1M_SEL_MASK 0x00000010
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#define CLK_POWER_SEL_OFFSET 3
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#define CLK_POWER_SEL_MASK 0x00000008
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#define CLK_25M_EN_OFFSET 2
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#define CLK_25M_EN_MASK 0x00000004
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#define PMU_CLK_SEL_OFFSET 0
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#define PMU_CLK_SEL_MASK 0x00000003
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//-----------------------------------
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#define CFG_PMU_CFG_ADDR 0x003C
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#define PMU_TICK_1M_REF_LIMIT_OFFSET 6
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#define PMU_TICK_1M_REF_LIMIT_MASK 0x000007C0
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#define CLK_TEST_SEL_OFFSET 4
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#define CLK_TEST_SEL_MASK 0x00000030
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#define DIG_WDG_CPURST_EB_OFFSET 3
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#define DIG_WDG_CPURST_EB_MASK 0x00000008
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#define UART_SRC_SEL_OFFSET 2
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#define UART_SRC_SEL_MASK 0x00000004
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#define PMU_REG_OWNER_SEL_OFFSET 1
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#define PMU_REG_OWNER_SEL_MASK 0x00000002
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#define PMU_REG_SOFT_SEL_EN_OFFSET 0
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#define PMU_REG_SOFT_SEL_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_PCORE_DTOP_SHUTDOWN_CFG_ADDR 0x0040
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#define PCORE_FORCE_ISO_OFFSET 18
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#define PCORE_FORCE_ISO_MASK 0x00040000
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#define PCORE_FORCE_PD_OFFSET 17
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#define PCORE_FORCE_PD_MASK 0x00020000
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#define PCORE_AUTO_PD_OFFSET 16
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#define PCORE_AUTO_PD_MASK 0x00010000
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#define DTOP_FORCE_ISO_OFFSET 2
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#define DTOP_FORCE_ISO_MASK 0x00000004
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#define DTOP_FORCE_PD_OFFSET 1
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#define DTOP_FORCE_PD_MASK 0x00000002
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#define DTOP_AUTO_PD_OFFSET 0
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#define DTOP_AUTO_PD_MASK 0x00000001
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//-----------------------------------
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#define CFG_PCORE_CFG_ADDR 0x0044
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#define START_PC_OFFSET 0
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#define START_PC_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PMU_TOP_LP_CTRL_ADDR 0x0048
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#define CLK_8M_EN_OFFSET 17
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#define CLK_8M_EN_MASK 0x00020000
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#define CLK_PMU_EN_OFFSET 16
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#define CLK_PMU_EN_MASK 0x00010000
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#define PMU_CORE_SLP_POWOFF_AUTO_EN_OFFSET 15
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#define PMU_CORE_SLP_POWOFF_AUTO_EN_MASK 0x00008000
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#define HIBER_MODE_ENA_OFFSET 14
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#define HIBER_MODE_ENA_MASK 0x00004000
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#define PB_MODE_ENA_OFFSET 13
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#define PB_MODE_ENA_MASK 0x00002000
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#define PMU_CORE_POW_FORCE_PD_OFFSET 12
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#define PMU_CORE_POW_FORCE_PD_MASK 0x00001000
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#define FORCE_PCORE_AP_SYS_STOP_OFFSET 9
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#define FORCE_PCORE_AP_SYS_STOP_MASK 0x00000200
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#define PCORE_AP_SYS_STOP_ENA_OFFSET 8
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#define PCORE_AP_SYS_STOP_ENA_MASK 0x00000100
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#define FORCE_PCORE_AP_DEEP_SLEEP_OFFSET 5
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#define FORCE_PCORE_AP_DEEP_SLEEP_MASK 0x00000020
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#define PCORE_AP_DEEP_SLEEP_ENA_OFFSET 4
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#define PCORE_AP_DEEP_SLEEP_ENA_MASK 0x00000010
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#define PCORE_ENA_OFFSET 2
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#define PCORE_ENA_MASK 0x00000004
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#define PCORE_SLEEP_ENA_OFFSET 1
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#define PCORE_SLEEP_ENA_MASK 0x00000002
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#define FORCE_PCORE_STOP_OFFSET 0
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#define FORCE_PCORE_STOP_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_TOP_LP_STATUS_ADDR 0x004C
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#define DTOP_SUBDOM_DEEP_SLEEP_OFFSET 21
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#define DTOP_SUBDOM_DEEP_SLEEP_MASK 0x00200000
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#define DIG_TOP_PD_STATUS_OFFSET 16
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#define DIG_TOP_PD_STATUS_MASK 0x001F0000
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#define PMU_CORE_PD_STATUS_OFFSET 0
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#define PMU_CORE_PD_STATUS_MASK 0x0000001F
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//-----------------------------------
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#define CFG_PMU_16KB_SHUTDOWN_ADDR 0x0050
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#define PMU_16K_FORCE_ISO_OFFSET 8
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#define PMU_16K_FORCE_ISO_MASK 0x00000100
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#define PMU_16K_AUTO_PD_OFFSET 4
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#define PMU_16K_AUTO_PD_MASK 0x00000010
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#define PMU_16K_FORCE_PD_OFFSET 0
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#define PMU_16K_FORCE_PD_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_LP_CTRL1_ADDR 0x0054
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#define XTAL_PD_WITH_DCDC_EB_OFFSET 31
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#define XTAL_PD_WITH_DCDC_EB_MASK 0x80000000
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#define PMU_ACCESS_DTOP_OFFSET 30
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#define PMU_ACCESS_DTOP_MASK 0x40000000
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#define PCORE_CHIP_LIGHT_SLEEP_EB_OFFSET 29
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#define PCORE_CHIP_LIGHT_SLEEP_EB_MASK 0x20000000
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#define PCORE_CHIP_DEEP_SLEEP_EB_OFFSET 28
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#define PCORE_CHIP_DEEP_SLEEP_EB_MASK 0x10000000
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#define PD_DTOP_CGM_AUTO_EN_OFFSET 27
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#define PD_DTOP_CGM_AUTO_EN_MASK 0x08000000
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#define PD_PCORE_CGM_AUTO_EN_OFFSET 20
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#define PD_PCORE_CGM_AUTO_EN_MASK 0x00100000
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#define CLR_DTOP_WAKEUP_PMU_OFFSET 16
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#define CLR_DTOP_WAKEUP_PMU_MASK 0x00010000
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#define PCORE_INT_MASK_OFFSET 12
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#define PCORE_INT_MASK_MASK 0x00001000
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#define RC8M_PD_WITH_PMU_DSLEEP_EB_OFFSET 11
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#define RC8M_PD_WITH_PMU_DSLEEP_EB_MASK 0x00000800
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#define DIG_GPIO_WAKEUP_CLR_OFFSET 10
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#define DIG_GPIO_WAKEUP_CLR_MASK 0x00000400
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#define DIG_GPIO_WAKEUP_OFFSET 9
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#define DIG_GPIO_WAKEUP_MASK 0x00000200
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#define DIG_RTC_TIMER_INT1_OFFSET 8
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#define DIG_RTC_TIMER_INT1_MASK 0x00000100
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#define DIG_RTC_TIMER_INT0_OFFSET 7
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#define DIG_RTC_TIMER_INT0_MASK 0x00000080
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#define DIG_GPIO_WAKEUP_EB_OFFSET 6
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#define DIG_GPIO_WAKEUP_EB_MASK 0x00000040
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#define DIG_RTC_WAKEUP_EB_OFFSET 5
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#define DIG_RTC_WAKEUP_EB_MASK 0x00000020
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#define PMU_RTC_WAKEUP_EB_OFFSET 4
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#define PMU_RTC_WAKEUP_EB_MASK 0x00000010
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#define PMU_GPIO_WAKEUP_EB_OFFSET 3
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#define PMU_GPIO_WAKEUP_EB_MASK 0x00000008
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#define CLR_PMU_GPIO_WAKEUP_OFFSET 2
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#define CLR_PMU_GPIO_WAKEUP_MASK 0x00000004
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#define PMU_WAKEUP_CPU1_OFFSET 1
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#define PMU_WAKEUP_CPU1_MASK 0x00000002
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#define PMU_WAKEUP_DTOP_OFFSET 0
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#define PMU_WAKEUP_DTOP_MASK 0x00000001
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//-----------------------------------
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#define CFG_ROM_4KB_LP_CTRL_ADDR 0x005C
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#define ROM_4K_SD_OFFSET 4
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#define ROM_4K_SD_MASK 0x00000010
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#define ROM_4K_LS_OFFSET 0
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#define ROM_4K_LS_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_FSM_CFG1_ADDR 0x0060
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#define PWR_ST_CGM_PMU_SEL_OFFSET 12
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#define PWR_ST_CGM_PMU_SEL_MASK 0x00001000
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#define PWR_ST_CLK_DIV_OFFSET 0
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#define PWR_ST_CLK_DIV_MASK 0x000003FF
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//-----------------------------------
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#define CFG_PCORE_MTX_STS_ADDR 0x0064
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#define PMU_MTX_HREADY_STS_CLR_OFFSET 8
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#define PMU_MTX_HREADY_STS_CLR_MASK 0x00000100
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#define PMU_MTX_SLV_HREADY_STS_OFFSET 4
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#define PMU_MTX_SLV_HREADY_STS_MASK 0x00000030
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#define PMU_MTX_MST_HREADY_STS_OFFSET 0
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#define PMU_MTX_MST_HREADY_STS_MASK 0x0000000F
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//-----------------------------------
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#define CFG_CALIB_32K_CFG0_ADDR 0x0068
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#define CALIB_32K_SWH_TIME_OFFSET 16
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#define CALIB_32K_SWH_TIME_MASK 0xFFFF0000
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#define CALIB_32K_DONE_OFFSET 14
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#define CALIB_32K_DONE_MASK 0x00004000
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#define CALIB_32K_CNT_DONE_OFFSET 13
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#define CALIB_32K_CNT_DONE_MASK 0x00002000
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#define CALIB_32K_CNT_CLR_OFFSET 12
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#define CALIB_32K_CNT_CLR_MASK 0x00001000
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#define RCO_32K_FREQ_CTRL_C_LIMIT_OFFSET 9
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#define RCO_32K_FREQ_CTRL_C_LIMIT_MASK 0x00000E00
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#define CALIB_32K_SOFT_F_OFFSET 6
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#define CALIB_32K_SOFT_F_MASK 0x000001C0
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#define CALIB_32K_SOFT_C_OFFSET 3
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#define CALIB_32K_SOFT_C_MASK 0x00000038
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#define CALIB_32K_SOFT_TUNE_OFFSET 2
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#define CALIB_32K_SOFT_TUNE_MASK 0x00000004
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#define CALIB_32K_SOFT_RST_OFFSET 1
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#define CALIB_32K_SOFT_RST_MASK 0x00000002
|
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#define CALIB_32K_SOFT_START_OFFSET 0
|
|
#define CALIB_32K_SOFT_START_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_32K_CFG1_ADDR 0x006C
|
|
#define RCO_32K_SIG_DBG_BUS_OFFSET 0
|
|
#define RCO_32K_SIG_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_32K_CFG2_ADDR 0x0070
|
|
#define CALIB_32K_CNT_REFER_OFFSET 20
|
|
#define CALIB_32K_CNT_REFER_MASK 0x0FF00000
|
|
#define CALIB_32K_CNT_LIMIT_OFFSET 0
|
|
#define CALIB_32K_CNT_LIMIT_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_VCO_CFG0_ADDR 0x0074
|
|
#define VCO_CALIB_PRECISION_CYCLE_NUM_OFFSET 16
|
|
#define VCO_CALIB_PRECISION_CYCLE_NUM_MASK 0xFFFF0000
|
|
#define PLL_VCO_CALIB_READY_MANU_OFFSET 14
|
|
#define PLL_VCO_CALIB_READY_MANU_MASK 0x00004000
|
|
#define PLL_VCO_CALIB_RESTART_OFFSET 13
|
|
#define PLL_VCO_CALIB_RESTART_MASK 0x00002000
|
|
#define PLL_VCO_CALIB_MANU_CAL_OFFSET 7
|
|
#define PLL_VCO_CALIB_MANU_CAL_MASK 0x00001F80
|
|
#define PLL_VCO_CALIB_MANU_EN_OFFSET 6
|
|
#define PLL_VCO_CALIB_MANU_EN_MASK 0x00000040
|
|
#define PLL_VCO_CALIB_CODE_INITIAL_OFFSET 0
|
|
#define PLL_VCO_CALIB_CODE_INITIAL_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_VCO_CFG1_ADDR 0x0078
|
|
#define PLL_VCO_CALIB_CODE_OFFSET 18
|
|
#define PLL_VCO_CALIB_CODE_MASK 0x00FC0000
|
|
#define PLL_VCO_CALIB_READY_OFFSET 17
|
|
#define PLL_VCO_CALIB_READY_MASK 0x00020000
|
|
#define PLL_VCO_CALIB_ERR_OFFSET 12
|
|
#define PLL_VCO_CALIB_ERR_MASK 0x0001F000
|
|
#define VCO_CALIB_DONE_OFFSET 11
|
|
#define VCO_CALIB_DONE_MASK 0x00000800
|
|
#define PLL_VCO_CALIB_READY_CLR_OFFSET 10
|
|
#define PLL_VCO_CALIB_READY_CLR_MASK 0x00000400
|
|
#define VCO_PLL_FB_CNT_CLR_OFFSET 9
|
|
#define VCO_PLL_FB_CNT_CLR_MASK 0x00000200
|
|
#define VCO_CALIB_DONE_CLR_OFFSET 8
|
|
#define VCO_CALIB_DONE_CLR_MASK 0x00000100
|
|
#define VCO_CALIB_CODE_SWH_WAIT_CN_OFFSET 0
|
|
#define VCO_CALIB_CODE_SWH_WAIT_CN_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_VCO_CFG2_ADDR 0x007C
|
|
#define VCO_SIG_DBG_BUS_OFFSET 0
|
|
#define VCO_SIG_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_VCO_CFG3_ADDR 0x0080
|
|
#define PLL_VCO_CALIB_ABSOLUTE_DVALUE_OFFSET 0
|
|
#define PLL_VCO_CALIB_ABSOLUTE_DVALUE_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PLL_LCKDT_CFG0_ADDR 0x0084
|
|
#define PLL_LCK_DBG_BUS_OFFSET 0
|
|
#define PLL_LCK_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PLL_LCKDT_CFG1_ADDR 0x0088
|
|
#define PLL_LCKDT_OFFSET 18
|
|
#define PLL_LCKDT_MASK 0x00040000
|
|
#define PPM_DOWN_LIMIT_OFFSET 10
|
|
#define PPM_DOWN_LIMIT_MASK 0x0003FC00
|
|
#define PPM_UP_LIMIT_OFFSET 2
|
|
#define PPM_UP_LIMIT_MASK 0x000003FC
|
|
#define PLL_LCKDT_SOFT_EN_OFFSET 1
|
|
#define PLL_LCKDT_SOFT_EN_MASK 0x00000002
|
|
#define PLL_LOCK_SOFT_LCKDT_OFFSET 0
|
|
#define PLL_LOCK_SOFT_LCKDT_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PLL_LCKDT_CFG2_ADDR 0x008C
|
|
#define PLL_LOCK_CNT_LIMIT_OFFSET 0
|
|
#define PLL_LOCK_CNT_LIMIT_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_MIPIVCO_CFG0_ADDR 0x0090
|
|
#define MIPIVCO_CALIB_PRECISION_CYCLE_NUM_OFFSET 16
|
|
#define MIPIVCO_CALIB_PRECISION_CYCLE_NUM_MASK 0xFFFF0000
|
|
#define MIPIPLL_VCO_CALIB_READY_MANU_OFFSET 14
|
|
#define MIPIPLL_VCO_CALIB_READY_MANU_MASK 0x00004000
|
|
#define MIPIPLL_VCO_CALIB_RESTART_OFFSET 13
|
|
#define MIPIPLL_VCO_CALIB_RESTART_MASK 0x00002000
|
|
#define MIPIPLL_VCO_CALIB_MANU_CAL_OFFSET 7
|
|
#define MIPIPLL_VCO_CALIB_MANU_CAL_MASK 0x00001F80
|
|
#define MIPIPLL_VCO_CALIB_MANU_EN_OFFSET 6
|
|
#define MIPIPLL_VCO_CALIB_MANU_EN_MASK 0x00000040
|
|
#define MIPIPLL_VCO_CALIB_CODE_INITIAL_OFFSET 0
|
|
#define MIPIPLL_VCO_CALIB_CODE_INITIAL_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_MIPIVCO_CFG1_ADDR 0x0094
|
|
#define MIPIPLL_VCO_CALIB_CODE_OFFSET 18
|
|
#define MIPIPLL_VCO_CALIB_CODE_MASK 0x00FC0000
|
|
#define MIPIPLL_VCO_CALIB_READY_OFFSET 17
|
|
#define MIPIPLL_VCO_CALIB_READY_MASK 0x00020000
|
|
#define MIPIPLL_VCO_CALIB_ERR_OFFSET 12
|
|
#define MIPIPLL_VCO_CALIB_ERR_MASK 0x0001F000
|
|
#define MIPIVCO_CALIB_DONE_OFFSET 11
|
|
#define MIPIVCO_CALIB_DONE_MASK 0x00000800
|
|
#define MIPIPLL_VCO_CALIB_READY_CLR_OFFSET 10
|
|
#define MIPIPLL_VCO_CALIB_READY_CLR_MASK 0x00000400
|
|
#define MIPIVCO_PLL_FB_CNT_CLR_OFFSET 9
|
|
#define MIPIVCO_PLL_FB_CNT_CLR_MASK 0x00000200
|
|
#define MIPIVCO_CALIB_DONE_CLR_OFFSET 8
|
|
#define MIPIVCO_CALIB_DONE_CLR_MASK 0x00000100
|
|
#define MIPIVCO_CALIB_CODE_SWH_WAIT_CN_OFFSET 0
|
|
#define MIPIVCO_CALIB_CODE_SWH_WAIT_CN_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_MIPIVCO_CFG2_ADDR 0x0098
|
|
#define MIPIVCO_SIG_DBG_BUS_OFFSET 0
|
|
#define MIPIVCO_SIG_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_MIPIVCO_CFG3_ADDR 0x009c
|
|
#define MIPIPLL_VCO_CALIB_ABSOLUTE_DVALUE_OFFSET 0
|
|
#define MIPIPLL_VCO_CALIB_ABSOLUTE_DVALUE_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MIPIPLL_LCKDT_CFG0_ADDR 0x00A0
|
|
#define MIPIPLL_LCK_DBG_BUS_OFFSET 0
|
|
#define MIPIPLL_LCK_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_MIPIPLL_LCKDT_CFG1_ADDR 0x00A4
|
|
#define MIPIPLL_LCKDT_OFFSET 18
|
|
#define MIPIPLL_LCKDT_MASK 0x00040000
|
|
#define MIPIPPM_DOWN_LIMIT_OFFSET 10
|
|
#define MIPIPPM_DOWN_LIMIT_MASK 0x0003FC00
|
|
#define MIPIPPM_UP_LIMIT_OFFSET 2
|
|
#define MIPIPPM_UP_LIMIT_MASK 0x000003FC
|
|
#define MIPIPLL_LCKDT_SOFT_EN_OFFSET 1
|
|
#define MIPIPLL_LCKDT_SOFT_EN_MASK 0x00000002
|
|
#define MIPIPLL_LOCK_SOFT_LCKDT_OFFSET 0
|
|
#define MIPIPLL_LOCK_SOFT_LCKDT_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_MIPIPLL_LCKDT_CFG2_ADDR 0x00A8
|
|
#define MIPIPLL_LOCK_CNT_LIMIT_OFFSET 0
|
|
#define MIPIPLL_LOCK_CNT_LIMIT_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_WDG_CFG_ADDR 0x00AC
|
|
#define DIG_CHIP_RST_REQ_FLAG_OFFSET 9
|
|
#define DIG_CHIP_RST_REQ_FLAG_MASK 0x00000200
|
|
#define DIG_CHIP_RST_REQ_FLAG_CLR_OFFSET 8
|
|
#define DIG_CHIP_RST_REQ_FLAG_CLR_MASK 0x00000100
|
|
#define WDG_DTOP_CPURST_FLAG_OFFSET 7
|
|
#define WDG_DTOP_CPURST_FLAG_MASK 0x00000080
|
|
#define WDG_DTOP_FULLRST_FLAG_OFFSET 6
|
|
#define WDG_DTOP_FULLRST_FLAG_MASK 0x00000040
|
|
#define WDG_DTOP_CPURST_FLAG_CLR_OFFSET 5
|
|
#define WDG_DTOP_CPURST_FLAG_CLR_MASK 0x00000020
|
|
#define WDG_DTOP_FULLRST_FLAG_CLR_OFFSET 4
|
|
#define WDG_DTOP_FULLRST_FLAG_CLR_MASK 0x00000010
|
|
#define WDG_CPURST_FLAG_OFFSET 3
|
|
#define WDG_CPURST_FLAG_MASK 0x00000008
|
|
#define WDG_FULLRST_FLAG_OFFSET 2
|
|
#define WDG_FULLRST_FLAG_MASK 0x00000004
|
|
#define WDG_CPURST_FLAG_CLR_OFFSET 1
|
|
#define WDG_CPURST_FLAG_CLR_MASK 0x00000002
|
|
#define WDG_FULLRST_FLAG_CLR_OFFSET 0
|
|
#define WDG_FULLRST_FLAG_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_8M_CFG0_ADDR 0x00B0
|
|
#define CALIB_8M_SWH_TIME_OFFSET 16
|
|
#define CALIB_8M_SWH_TIME_MASK 0xFFFF0000
|
|
#define CALIB_8M_DONE_OFFSET 14
|
|
#define CALIB_8M_DONE_MASK 0x00004000
|
|
#define CALIB_8M_CNT_DONE_OFFSET 13
|
|
#define CALIB_8M_CNT_DONE_MASK 0x00002000
|
|
#define CALIB_8M_CNT_CLR_OFFSET 12
|
|
#define CALIB_8M_CNT_CLR_MASK 0x00001000
|
|
#define RCO_8M_FREQ_CTRL_C_LIMIT_OFFSET 9
|
|
#define RCO_8M_FREQ_CTRL_C_LIMIT_MASK 0x00000E00
|
|
#define CALIB_8M_SOFT_F_OFFSET 6
|
|
#define CALIB_8M_SOFT_F_MASK 0x000001C0
|
|
#define CALIB_8M_SOFT_C_OFFSET 3
|
|
#define CALIB_8M_SOFT_C_MASK 0x00000038
|
|
#define CALIB_8M_SOFT_TUNE_OFFSET 2
|
|
#define CALIB_8M_SOFT_TUNE_MASK 0x00000004
|
|
#define CALIB_8M_SOFT_RST_OFFSET 1
|
|
#define CALIB_8M_SOFT_RST_MASK 0x00000002
|
|
#define CALIB_8M_SOFT_START_OFFSET 0
|
|
#define CALIB_8M_SOFT_START_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_8M_CFG1_ADDR 0x00B4
|
|
#define RCO_8M_SIG_DBG_BUS_OFFSET 0
|
|
#define RCO_8M_SIG_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CALIB_8M_CFG2_ADDR 0x00B8
|
|
#define CALIB_8M_CNT_REFER_OFFSET 16
|
|
#define CALIB_8M_CNT_REFER_MASK 0x03FF0000
|
|
#define CALIB_8M_CNT_LIMIT_OFFSET 0
|
|
#define CALIB_8M_CNT_LIMIT_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_ANA_TOP_CFG0_ADDR 0x00BC
|
|
#define PMU_LDO_CURRENT_SEL_MUX_OFFSET 23
|
|
#define PMU_LDO_CURRENT_SEL_MUX_MASK 0x00800000
|
|
#define PMU_LDO_CURRENT_SEL_OFFSET 20
|
|
#define PMU_LDO_CURRENT_SEL_MASK 0x00700000
|
|
#define BANDGAP_PD_AUTO_EN_OFFSET 17
|
|
#define BANDGAP_PD_AUTO_EN_MASK 0x00020000
|
|
#define DCDC_PD_AUTO_EN_OFFSET 16
|
|
#define DCDC_PD_AUTO_EN_MASK 0x00010000
|
|
#define BANDGAP_PD_FORCE_OFFSET 1
|
|
#define BANDGAP_PD_FORCE_MASK 0x00000002
|
|
#define DCDC_PD_FORCE_OFFSET 0
|
|
#define DCDC_PD_FORCE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_ANA_TOP_CFG1_ADDR 0x00C0
|
|
#define MIPIPLL_SOFT_RST_OFFSET 1
|
|
#define MIPIPLL_SOFT_RST_MASK 0x00000002
|
|
#define PLL_SOFT_RST_OFFSET 0
|
|
#define PLL_SOFT_RST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_PKG_TYPE_ADDR 0x00C4
|
|
#define DIG_BOOT_FROM_PMU_OFFSET 3
|
|
#define DIG_BOOT_FROM_PMU_MASK 0x00000008
|
|
#define PMU_IR_MODE_OFFSET 2
|
|
#define PMU_IR_MODE_MASK 0x00000004
|
|
#define PMU_PKG_TYPE_OFFSET 0
|
|
#define PMU_PKG_TYPE_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_FDMA_DBG_BUS0_ADDR 0x00D0
|
|
#define FUNCTST_DBG_BUS0_OFFSET 0
|
|
#define FUNCTST_DBG_BUS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_FDMA_DBG_BUS1_ADDR 0x00D4
|
|
#define FUNCTST_DBG_BUS1_OFFSET 0
|
|
#define FUNCTST_DBG_BUS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_FDMA_DBG_BUS2_ADDR 0x00D8
|
|
#define FUNCTST_DBG_BUS2_OFFSET 0
|
|
#define FUNCTST_DBG_BUS2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_FDMA_DBG_BUS3_ADDR 0x00DC
|
|
#define FUNCTST_DBG_BUS3_OFFSET 0
|
|
#define FUNCTST_DBG_BUS3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_WDG_RST_CFG_ADDR 0x00E0
|
|
#define WDG_DTOP_PMU_RST_ENA_OFFSET 5
|
|
#define WDG_DTOP_PMU_RST_ENA_MASK 0x00000020
|
|
#define WDG_PMU_RST_ENA_OFFSET 4
|
|
#define WDG_PMU_RST_ENA_MASK 0x00000010
|
|
#define WDG_DTOP_CHIP_RST_ENA_OFFSET 1
|
|
#define WDG_DTOP_CHIP_RST_ENA_MASK 0x00000002
|
|
#define WDG_CHIP_RST_ENA_OFFSET 0
|
|
#define WDG_CHIP_RST_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_AHB_PCORE_IEXPT_CFG0_ADDR 0x00E4
|
|
#define PCORE_I_EXPT_MASK_OFFSET 24
|
|
#define PCORE_I_EXPT_MASK_MASK 0x01000000
|
|
#define PCORE_I_ACCESS_EN_OFFSET 0
|
|
#define PCORE_I_ACCESS_EN_MASK 0x0001FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AHB_PCORE_DEXPT_CFG0_ADDR 0x00E8
|
|
#define PCORE_D_EXPT_MASK_OFFSET 24
|
|
#define PCORE_D_EXPT_MASK_MASK 0x3F000000
|
|
#define PCORE_D_ACCESS_EN_OFFSET 0
|
|
#define PCORE_D_ACCESS_EN_MASK 0x0001FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_CLK_ENABLE_SET_ADDR 0x00F0
|
|
#define WDG_DTOP_EB_SET_OFFSET 30
|
|
#define WDG_DTOP_EB_SET_MASK 0x40000000
|
|
#define EFUSE_EB_SET_OFFSET 29
|
|
#define EFUSE_EB_SET_MASK 0x20000000
|
|
#define ANTI_ATTACK_EB_SET_OFFSET 17
|
|
#define ANTI_ATTACK_EB_SET_MASK 0x00020000
|
|
#define SPWM_EB_SET_OFFSET 16
|
|
#define SPWM_EB_SET_MASK 0x00010000
|
|
#define PMU_ANAREG_EB_SET_OFFSET 7
|
|
#define PMU_ANAREG_EB_SET_MASK 0x00000080
|
|
#define PMU_WDG_EB_SET_OFFSET 6
|
|
#define PMU_WDG_EB_SET_MASK 0x00000040
|
|
#define GPIO_TOPA_EB_SET_OFFSET 5
|
|
#define GPIO_TOPA_EB_SET_MASK 0x00000020
|
|
#define IO_MUXA_EB_SET_OFFSET 4
|
|
#define IO_MUXA_EB_SET_MASK 0x00000010
|
|
#define RTC_TMR_EB_SET_OFFSET 3
|
|
#define RTC_TMR_EB_SET_MASK 0x00000008
|
|
#define I2C_EB_SET_OFFSET 2
|
|
#define I2C_EB_SET_MASK 0x00000004
|
|
#define INTC_EB_SET_OFFSET 1
|
|
#define INTC_EB_SET_MASK 0x00000002
|
|
#define GTMR_EB_SET_OFFSET 0
|
|
#define GTMR_EB_SET_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_CLK_ENABLE_CLR_ADDR 0x00F4
|
|
#define WDG_DTOP_EB_CLR_OFFSET 30
|
|
#define WDG_DTOP_EB_CLR_MASK 0x40000000
|
|
#define EFUSE_EB_CLR_OFFSET 29
|
|
#define EFUSE_EB_CLR_MASK 0x20000000
|
|
#define ANTI_ATTACK_EB_CLR_OFFSET 17
|
|
#define ANTI_ATTACK_EB_CLR_MASK 0x00020000
|
|
#define SPWM_EB_CLR_OFFSET 16
|
|
#define SPWM_EB_CLR_MASK 0x00010000
|
|
#define PMU_ANAREG_EB_CLR_OFFSET 7
|
|
#define PMU_ANAREG_EB_CLR_MASK 0x00000080
|
|
#define PMU_WDG_EB_CLR_OFFSET 6
|
|
#define PMU_WDG_EB_CLR_MASK 0x00000040
|
|
#define GPIO_TOPA_EB_CLR_OFFSET 5
|
|
#define GPIO_TOPA_EB_CLR_MASK 0x00000020
|
|
#define IO_MUXA_EB_CLR_OFFSET 4
|
|
#define IO_MUXA_EB_CLR_MASK 0x00000010
|
|
#define RTC_TMR_EB_CLR_OFFSET 3
|
|
#define RTC_TMR_EB_CLR_MASK 0x00000008
|
|
#define I2C_EB_CLR_OFFSET 2
|
|
#define I2C_EB_CLR_MASK 0x00000004
|
|
#define INTC_EB_CLR_OFFSET 1
|
|
#define INTC_EB_CLR_MASK 0x00000002
|
|
#define GTMR_EB_CLR_OFFSET 0
|
|
#define GTMR_EB_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_PMU_SOFT_RESET_SET_ADDR 0x00F8
|
|
#define PMU_SOFT_RST_SET_OFFSET 31
|
|
#define PMU_SOFT_RST_SET_MASK 0x80000000
|
|
#define WDG_DTOP_SOFT_RST_SET_OFFSET 30
|
|
#define WDG_DTOP_SOFT_RST_SET_MASK 0x40000000
|
|
#define ANTI_ATTACK_SOFT_RST_SET_OFFSET 17
|
|
#define ANTI_ATTACK_SOFT_RST_SET_MASK 0x00020000
|
|
#define SADC_PWM_SOFT_RST_SET_OFFSET 16
|
|
#define SADC_PWM_SOFT_RST_SET_MASK 0x00010000
|
|
#define SADC_CH2_SOFT_RST_SET_OFFSET 15
|
|
#define SADC_CH2_SOFT_RST_SET_MASK 0x00008000
|
|
#define SADC_CH1_SOFT_RST_SET_OFFSET 14
|
|
#define SADC_CH1_SOFT_RST_SET_MASK 0x00004000
|
|
#define MIPIPLL_LOCK_SOFT_RST_SET_OFFSET 13
|
|
#define MIPIPLL_LOCK_SOFT_RST_SET_MASK 0x00002000
|
|
#define MIPIVCO_CALIB_SOFT_RST_SET_OFFSET 12
|
|
#define MIPIVCO_CALIB_SOFT_RST_SET_MASK 0x00001000
|
|
#define PLL_LOCK_SOFT_RST_SET_OFFSET 11
|
|
#define PLL_LOCK_SOFT_RST_SET_MASK 0x00000800
|
|
#define VCO_CALIB_SOFT_RST_SET_OFFSET 10
|
|
#define VCO_CALIB_SOFT_RST_SET_MASK 0x00000400
|
|
#define DTOP_SOFT_RST_SET_OFFSET 9
|
|
#define DTOP_SOFT_RST_SET_MASK 0x00000200
|
|
#define PMU_ANAREG_SOFT_RST_SET_OFFSET 7
|
|
#define PMU_ANAREG_SOFT_RST_SET_MASK 0x00000080
|
|
#define PMU_WDG_SOFT_RST_SET_OFFSET 6
|
|
#define PMU_WDG_SOFT_RST_SET_MASK 0x00000040
|
|
#define GPIO_TOPA_SOFT_RST_SET_OFFSET 5
|
|
#define GPIO_TOPA_SOFT_RST_SET_MASK 0x00000020
|
|
#define IO_MUXA_SOFT_RST_SET_OFFSET 4
|
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#define IO_MUXA_SOFT_RST_SET_MASK 0x00000010
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#define RTC_TMR_SOFT_RST_SET_OFFSET 3
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#define RTC_TMR_SOFT_RST_SET_MASK 0x00000008
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#define I2C_SOFT_RST_SET_OFFSET 2
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#define I2C_SOFT_RST_SET_MASK 0x00000004
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#define INTC_SOFT_RST_SET_OFFSET 1
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#define INTC_SOFT_RST_SET_MASK 0x00000002
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#define GTMR_SOFT_RST_SET_OFFSET 0
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#define GTMR_SOFT_RST_SET_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_SOFT_RESET_CLR_ADDR 0x00FC
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#define PMU_SOFT_RST_CLR_OFFSET 31
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#define PMU_SOFT_RST_CLR_MASK 0x80000000
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#define WDG_DTOP_SOFT_RST_CLR_OFFSET 30
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#define WDG_DTOP_SOFT_RST_CLR_MASK 0x40000000
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#define ANTI_ATTACK_SOFT_RST_CLR_OFFSET 17
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#define ANTI_ATTACK_SOFT_RST_CLR_MASK 0x00020000
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#define SADC_PWM_SOFT_RST_CLR_OFFSET 16
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#define SADC_PWM_SOFT_RST_CLR_MASK 0x00010000
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#define SADC_CH2_SOFT_RST_CLR_OFFSET 15
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#define SADC_CH2_SOFT_RST_CLR_MASK 0x00008000
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#define SADC_CH1_SOFT_RST_CLR_OFFSET 14
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#define SADC_CH1_SOFT_RST_CLR_MASK 0x00004000
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#define MIPIPLL_LOCK_SOFT_RST_CLR_OFFSET 13
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#define MIPIPLL_LOCK_SOFT_RST_CLR_MASK 0x00002000
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#define MIPIVCO_CALIB_SOFT_RST_CLR_OFFSET 12
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#define MIPIVCO_CALIB_SOFT_RST_CLR_MASK 0x00001000
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#define PLL_LOCK_SOFT_RST_CLR_OFFSET 11
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#define PLL_LOCK_SOFT_RST_CLR_MASK 0x00000800
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#define VCO_CALIB_SOFT_RST_CLR_OFFSET 10
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#define VCO_CALIB_SOFT_RST_CLR_MASK 0x00000400
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#define DTOP_SOFT_RST_CLR_OFFSET 9
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#define DTOP_SOFT_RST_CLR_MASK 0x00000200
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#define PMU_ANAREG_SOFT_RST_CLR_OFFSET 7
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#define PMU_ANAREG_SOFT_RST_CLR_MASK 0x00000080
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#define PMU_WDG_SOFT_RST_CLR_OFFSET 6
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#define PMU_WDG_SOFT_RST_CLR_MASK 0x00000040
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#define GPIO_TOPA_SOFT_RST_CLR_OFFSET 5
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#define GPIO_TOPA_SOFT_RST_CLR_MASK 0x00000020
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#define IO_MUXA_SOFT_RST_CLR_OFFSET 4
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#define IO_MUXA_SOFT_RST_CLR_MASK 0x00000010
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#define RTC_TMR_SOFT_RST_CLR_OFFSET 3
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#define RTC_TMR_SOFT_RST_CLR_MASK 0x00000008
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#define I2C_SOFT_RST_CLR_OFFSET 2
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#define I2C_SOFT_RST_CLR_MASK 0x00000004
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#define INTC_SOFT_RST_CLR_OFFSET 1
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#define INTC_SOFT_RST_CLR_MASK 0x00000002
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#define GTMR_SOFT_RST_CLR_OFFSET 0
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#define GTMR_SOFT_RST_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_ANTI_ATTACK_CFG_ADDR 0x0100
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#define ANTI_ATTACK_SOFT_START_OFFSET 5
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#define ANTI_ATTACK_SOFT_START_MASK 0x00000020
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#define ANTI_ATTACK_MISMATCH_CLR_OFFSET 4
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#define ANTI_ATTACK_MISMATCH_CLR_MASK 0x00000010
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#define ANTI_ATTACK_MISMATCH_OFFSET 0
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#define ANTI_ATTACK_MISMATCH_MASK 0x00000001
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//-----------------------------------
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#define CFG_PMU_DEBUG_CFG0_ADDR 0x0104
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#define PMU_DBG_CTRL_EB_OFFSET 16
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#define PMU_DBG_CTRL_EB_MASK 0x00010000
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#define PMU_DBG_MOD_SEL_OFFSET 8
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#define PMU_DBG_MOD_SEL_MASK 0x0000FF00
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#define PMU_DBG_SIG_SEL_OFFSET 0
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#define PMU_DBG_SIG_SEL_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PMU_MTX_CFG_ADDR 0x0108
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#define PMU_MTX_BURST_ENA_OFFSET 0
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#define PMU_MTX_BURST_ENA_MASK 0x0000000F
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//-----------------------------------
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#define CFG_PMU_SCRATCH0_CFG_ADDR 0x08F8
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#define PMU_SCRATCH0_OFFSET 0
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#define PMU_SCRATCH0_MASK 0xFFFFFFFF
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#define CFG_PMU_SCRATCH1_CFG_ADDR 0x08FC
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#define PMU_SCRATCH1_OFFSET 0
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#define PMU_SCRATCH1_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define PMU_RF_READ_REG(addr) SOC_READ_REG(PMU_RF_BASEADDR + addr)
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#define PMU_RF_WRITE_REG(addr,value) SOC_WRITE_REG(PMU_RF_BASEADDR + addr,value)
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