339 lines
11 KiB
C
Executable File
339 lines
11 KiB
C
Executable File
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//-----------------------------------
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#define CFG_IP_VERSION_ADDR 0x0000
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#define MOD_MULTIPLIER_VERSION_OFFSET 0
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#define MOD_MULTIPLIER_VERSION_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_ENABLE_ADDR 0x0004
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#define CONV_EB_OFFSET 7
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#define CONV_EB_MASK 0x00000080
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#define CHACHA_EB_OFFSET 6
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#define CHACHA_EB_MASK 0x00000040
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#define RANDOM_EB_OFFSET 5
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#define RANDOM_EB_MASK 0x00000020
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#define SHA2_EB_OFFSET 4
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#define SHA2_EB_MASK 0x00000010
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#define SM2_EB_OFFSET 3
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#define SM2_EB_MASK 0x00000008
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#define SM3_EB_OFFSET 2
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#define SM3_EB_MASK 0x00000004
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#define SM4_EB_OFFSET 1
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#define SM4_EB_MASK 0x00000002
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#define AES_EB_OFFSET 0
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#define AES_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_START_ADDR 0x0008
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#define CONV_START_OFFSET 5
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#define CONV_START_MASK 0x00000020
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#define CHACHA_START_OFFSET 4
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#define CHACHA_START_MASK 0x00000010
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#define RANDOM_START_OFFSET 3
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#define RANDOM_START_MASK 0x00000008
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#define SM2_START_OFFSET 2
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#define SM2_START_MASK 0x00000004
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#define SM3_START_OFFSET 1
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#define SM3_START_MASK 0x00000002
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#define SM4_START_OFFSET 0
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#define SM4_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_SOFT_RST_ADDR 0x000C
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#define CRYPTO_SOFT_RST_OFFSET 8
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#define CRYPTO_SOFT_RST_MASK 0x00000100
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#define CONV_SOFT_RST_OFFSET 7
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#define CONV_SOFT_RST_MASK 0x00000080
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#define CHACHA_SOFT_RST_OFFSET 6
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#define CHACHA_SOFT_RST_MASK 0x00000040
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#define RANDOM_SOFT_RST_OFFSET 5
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#define RANDOM_SOFT_RST_MASK 0x00000020
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#define AES_SOFT_RST_OFFSET 4
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#define AES_SOFT_RST_MASK 0x00000010
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#define SM4_SOFT_RST_OFFSET 3
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#define SM4_SOFT_RST_MASK 0x00000008
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#define SHA2_SOFT_RST_OFFSET 2
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#define SHA2_SOFT_RST_MASK 0x00000004
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#define SM3_SOFT_RST_OFFSET 1
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#define SM3_SOFT_RST_MASK 0x00000002
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#define SM2_SOFT_RST_OFFSET 0
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#define SM2_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_INT_CLR_ADDR 0x0010
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#define CONV_INT_CLR_OFFSET 5
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#define CONV_INT_CLR_MASK 0x00000020
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#define CHACHA_INT_CLR_OFFSET 4
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#define CHACHA_INT_CLR_MASK 0x00000010
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#define RANDOM_INT_CLR_OFFSET 3
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#define RANDOM_INT_CLR_MASK 0x00000008
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#define SM2_INT_CLR_OFFSET 2
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#define SM2_INT_CLR_MASK 0x00000004
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#define SM3_INT_CLR_OFFSET 1
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#define SM3_INT_CLR_MASK 0x00000002
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#define SM4_INT_CLR_OFFSET 0
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#define SM4_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_SM2_MOD_MULTIPLY_CTRL_ADDR 0x0014
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#define MOD_R2_MEM_SET_VALUE_OFFSET 12
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#define MOD_R2_MEM_SET_VALUE_MASK 0x00001000
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#define MOD_M_MEM_SET_VALUE_OFFSET 11
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#define MOD_M_MEM_SET_VALUE_MASK 0x00000800
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#define MOD_Y_MEM_SET_VALUE_OFFSET 10
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#define MOD_Y_MEM_SET_VALUE_MASK 0x00000400
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#define MOD_X_MEM_SET_VALUE_OFFSET 9
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#define MOD_X_MEM_SET_VALUE_MASK 0x00000200
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#define MOD_STORE_SWH_OFFSET 8
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#define MOD_STORE_SWH_MASK 0x00000100
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#define ENCRYPTION_MOD_OFFSET 0
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#define ENCRYPTION_MOD_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SM2_M_DASH_ADDR 0x0018
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#define M_DASH_OFFSET 0
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#define M_DASH_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SM3_SHA2_MODE_ADDR 0x001C
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#define SHA_DMA_OUT_BIT_ORDER_SEL_OFFSET 7
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#define SHA_DMA_OUT_BIT_ORDER_SEL_MASK 0x00000080
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#define SHA_DMA_OUT_BYTE_ORDER_SEL_OFFSET 6
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#define SHA_DMA_OUT_BYTE_ORDER_SEL_MASK 0x00000040
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#define SHA_DMA_IN_BIT_ORDER_SEL_OFFSET 5
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#define SHA_DMA_IN_BIT_ORDER_SEL_MASK 0x00000020
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#define SHA_DMA_IN_BYTE_ORDER_SEL_OFFSET 4
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#define SHA_DMA_IN_BYTE_ORDER_SEL_MASK 0x00000010
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#define HASH_VALUE_FROM_MEM_OFFSET 3
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#define HASH_VALUE_FROM_MEM_MASK 0x00000008
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#define SM3_SHA2_MODE_OFFSET 2
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#define SM3_SHA2_MODE_MASK 0x00000004
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#define SHA2_MODE_OFFSET 0
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#define SHA2_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_SM3_SHA2_SOURCE_ADDR_ADDR 0x0020
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#define SM3_SHA2_SOURCE_ADDR_OFFSET 0
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#define SM3_SHA2_SOURCE_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SM3_SHA2_ENCRYPT_LEN_ADDR 0x0024
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#define SM3_SHA2_DATA_LEN_OFFSET 0
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#define SM3_SHA2_DATA_LEN_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SM4_AES_CONTROL_ADDR 0x0028
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#define CHACHA_MODE_SEL_OFFSET 31
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#define CHACHA_MODE_SEL_MASK 0x80000000
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#define MULT_GF_MANUAL_RST_OFFSET 30
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#define MULT_GF_MANUAL_RST_MASK 0x40000000
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#define MULT_GF_MANUAL_EN_OFFSET 29
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#define MULT_GF_MANUAL_EN_MASK 0x20000000
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#define MULT_GF_MANUAL_START_OFFSET 28
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#define MULT_GF_MANUAL_START_MASK 0x10000000
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#define CRYPT_DMA_OUT_BIT_ORDER_SEL_OFFSET 27
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#define CRYPT_DMA_OUT_BIT_ORDER_SEL_MASK 0x08000000
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#define CRYPT_DMA_OUT_BYTE_ORDER_SEL_OFFSET 26
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#define CRYPT_DMA_OUT_BYTE_ORDER_SEL_MASK 0x04000000
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#define CRYPT_DMA_IN_BIT_ORDER_SEL_OFFSET 25
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#define CRYPT_DMA_IN_BIT_ORDER_SEL_MASK 0x02000000
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#define CRYPT_DMA_IN_BYTE_ORDER_SEL_OFFSET 24
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#define CRYPT_DMA_IN_BYTE_ORDER_SEL_MASK 0x01000000
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#define GCM_IV_SW_HANDLE_OFFSET 23
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#define GCM_IV_SW_HANDLE_MASK 0x00800000
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#define GCM_VERIFY_EB_OFFSET 22
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#define GCM_VERIFY_EB_MASK 0x00400000
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#define SM4_DECRY_SPEED_UP_OFFSET 21
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#define SM4_DECRY_SPEED_UP_MASK 0x00200000
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#define GCM_SW_IV_LEN_OFFSET 16
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#define GCM_SW_IV_LEN_MASK 0x001F0000
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#define GCM_SW_CTRL_OFFSET 13
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#define GCM_SW_CTRL_MASK 0x0000E000
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#define START_2ST_OFFSET 12
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#define START_2ST_MASK 0x00001000
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#define GCM_SW_AUTH_LEN_OFFSET 7
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#define GCM_SW_AUTH_LEN_MASK 0x00000F80
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#define CRYPTO_SEL_OFFSET 5
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#define CRYPTO_SEL_MASK 0x00000060
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#define ENCRY_MODE_OFFSET 3
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#define ENCRY_MODE_MASK 0x00000018
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#define ENCRY_DECRY_SEL_OFFSET 2
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#define ENCRY_DECRY_SEL_MASK 0x00000004
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#define KEY_MODE_OFFSET 0
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#define KEY_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_SM4_INPUT_START_ADDR_ADDR 0x002C
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#define INPUT_START_ADDR_OFFSET 0
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#define INPUT_START_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SM4_INPUT_DATA_LENGTH_ADDR 0x0030
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#define DATA_LENGTH_OFFSET 0
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#define DATA_LENGTH_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SM4_OUTPUT_START_ADDR_ADDR 0x0034
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#define OUTPUT_START_ADDR_OFFSET 0
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#define OUTPUT_START_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_RANDOM_CONTROL_ADDR 0x0038
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#define RANDOM_UPDATE_MARK_OFFSET 14
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#define RANDOM_UPDATE_MARK_MASK 0x00004000
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#define RANDOM_UPDATE_MARK_SET_OFFSET 13
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#define RANDOM_UPDATE_MARK_SET_MASK 0x00002000
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#define RANDOM_MAX_NUMBER_OFFSET 4
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#define RANDOM_MAX_NUMBER_MASK 0x00001FF0
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#define RANDOM_SAMPLE_WID_OFFSET 0
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#define RANDOM_SAMPLE_WID_MASK 0x0000000F
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//-----------------------------------
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#define CFG_SM4_AES_CTR_RANDOM_ADDR 0x003C
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#define CTR_RANDOM_OFFSET 0
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#define CTR_RANDOM_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SM4_AES_CTR_COUNTER_ADDR 0x0040
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#define CTR_CNT_OFFSET 0
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#define CTR_CNT_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_INT_STATUS_ADDR 0x0044
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#define CONV_INT_OFFSET 5
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#define CONV_INT_MASK 0x00000020
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#define CHACHA_INT_OFFSET 4
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#define CHACHA_INT_MASK 0x00000010
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#define RANDOM_INT_OFFSET 3
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#define RANDOM_INT_MASK 0x00000008
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#define SM2_INT_OFFSET 2
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#define SM2_INT_MASK 0x00000004
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#define SM3_INT_OFFSET 1
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#define SM3_INT_MASK 0x00000002
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#define SM4_INT_OFFSET 0
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#define SM4_INT_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_ENDIAN_CONFIG_ADDR 0x0048
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#define CRYPTO_IN_WORD_ENDIAN_SEL_OFFSET 17
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#define CRYPTO_IN_WORD_ENDIAN_SEL_MASK 0x00020000
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#define CRYPTO_OUT_WORD_ENDIAN_SEL_OFFSET 16
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#define CRYPTO_OUT_WORD_ENDIAN_SEL_MASK 0x00010000
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#define SHA512_2WORD_ORDER_SEL_OFFSET 10
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#define SHA512_2WORD_ORDER_SEL_MASK 0x00000400
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#define GCM_TAG_ENDIAN_SEL_OFFSET 9
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#define GCM_TAG_ENDIAN_SEL_MASK 0x00000200
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#define RANDOM_OUT_ENDIAN_SEL_OFFSET 8
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#define RANDOM_OUT_ENDIAN_SEL_MASK 0x00000100
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#define SM2_OUT_ENDIAN_SEL_OFFSET 7
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#define SM2_OUT_ENDIAN_SEL_MASK 0x00000080
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#define SM3_OUT_ENDIAN_SEL_OFFSET 6
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#define SM3_OUT_ENDIAN_SEL_MASK 0x00000040
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#define SM4_OUT_ENDIAN_SEL_OFFSET 5
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#define SM4_OUT_ENDIAN_SEL_MASK 0x00000020
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#define CHACHA_ENDIAN_SEL_OFFSET 4
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#define CHACHA_ENDIAN_SEL_MASK 0x00000010
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#define RANDOM_ENDIAN_SEL_OFFSET 3
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#define RANDOM_ENDIAN_SEL_MASK 0x00000008
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#define SM2_ENDIAN_SEL_OFFSET 2
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#define SM2_ENDIAN_SEL_MASK 0x00000004
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#define SM3_ENDIAN_SEL_OFFSET 1
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#define SM3_ENDIAN_SEL_MASK 0x00000002
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#define SM4_ENDIAN_SEL_OFFSET 0
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#define SM4_ENDIAN_SEL_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_MEM_CLOCK_FORCE_ADDR 0x004C
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#define CHACHA_MEM_CLOCK_FORCE_OFFSET 4
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#define CHACHA_MEM_CLOCK_FORCE_MASK 0x00000010
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#define RANDOM_MEM_CLOCK_FORCE_OFFSET 3
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#define RANDOM_MEM_CLOCK_FORCE_MASK 0x00000008
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#define SM2_MEM_CLOCK_FORCE_OFFSET 2
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#define SM2_MEM_CLOCK_FORCE_MASK 0x00000004
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#define SM3_MEM_CLOCK_FORCE_OFFSET 1
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#define SM3_MEM_CLOCK_FORCE_MASK 0x00000002
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#define SM4_MEM_CLOCK_FORCE_OFFSET 0
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#define SM4_MEM_CLOCK_FORCE_MASK 0x00000001
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//-----------------------------------
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#define CFG_RANDOM_NONCE_ADDR 0x0050
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#define RANDOM_NONCE_OFFSET 0
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#define RANDOM_NONCE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GCM_AUTH_LEN_ADDR 0x0054
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#define GCM_AUTH_LEN_OFFSET 0
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#define GCM_AUTH_LEN_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GCM_AUTH_START_ADDR_ADDR 0x0058
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#define GCM_AUTH_START_ADDR_OFFSET 0
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#define GCM_AUTH_START_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GCM_IV_LEN_ADDR 0x005C
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#define GCM_IV_LEN_OFFSET 0
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#define GCM_IV_LEN_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GCM_IV_START_ADDR_ADDR 0x0060
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#define GCM_IV_START_ADDR_OFFSET 0
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#define GCM_IV_START_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CONV_CONFIG_ADDR 0x0064
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#define CONV_SIGNED_SWH_OFFSET 18
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#define CONV_SIGNED_SWH_MASK 0x00040000
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#define CONV_SHIFT_NUM_OFFSET 10
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#define CONV_SHIFT_NUM_MASK 0x0003FC00
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#define CONV_PROC_WID_OFFSET 2
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#define CONV_PROC_WID_MASK 0x000003FC
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#define CONV_RESERVE_OFFSET 1
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#define CONV_RESERVE_MASK 0x00000002
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#define CONV_MODE_OFFSET 0
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#define CONV_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_MOD_ADDR_CFG0_ADDR 0x0068
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#define MOD_X_SADDR_OFFSET 0
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#define MOD_X_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_MOD_ADDR_CFG1_ADDR 0x006C
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#define MOD_Y_SADDR_OFFSET 0
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#define MOD_Y_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_MOD_ADDR_CFG2_ADDR 0x0070
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#define MOD_M_SADDR_OFFSET 0
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#define MOD_M_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_MOD_ADDR_CFG3_ADDR 0x0074
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#define MOD_R2_SADDR_OFFSET 0
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#define MOD_R2_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_MOD_ADDR_CFG4_ADDR 0x0078
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#define MOD_RESULT_SADDR_OFFSET 0
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#define MOD_RESULT_SADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_MOD_ELEM_LEN_CFG0_ADDR 0x007C
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#define MOD_ELEM_LEN_OFFSET 0
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#define MOD_ELEM_LEN_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_SEC_MOD_ELEM_LEN_CFG1_ADDR 0x0080
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#define MOD_RESULT_LEN_OFFSET 0
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#define MOD_RESULT_LEN_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SM4_AES_CONTROL1_ADDR 0x0084
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#define CNT_32B_64B_SEL_OFFSET 0
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#define CNT_32B_64B_SEL_MASK 0x00000001
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//HW module read/write macro
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#define SEC_SYS_RF_READ_REG(addr) SOC_READ_REG(SEC_SYS_RF_BASEADDR + addr)
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#define SEC_SYS_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SEC_SYS_RF_BASEADDR + addr,value)
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