407 lines
10 KiB
C
407 lines
10 KiB
C
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//-----------------------------------
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#define CFG_CTRLR0_ADDR 0x006c
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#define TMOD_OFFSET 14
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#define TMOD_MASK 0x0000C000
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#define SLV_OE_OFFSET 13
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#define SLV_OE_MASK 0x00002000
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#define SRL_OFFSET 12
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#define SRL_MASK 0x00001000
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#define CFS_OFFSET 8
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#define CFS_MASK 0x00000F00
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#define DFS_OFFSET 4
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#define DFS_MASK 0x000000F0
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#define FRF_OFFSET 2
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#define FRF_MASK 0x0000000C
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#define SCPH_OFFSET 1
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#define SCPH_MASK 0x00000002
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#define SCPOL_OFFSET 0
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#define SCPOL_MASK 0x00000001
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//-----------------------------------
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#define CFG_CTRLR1_ADDR 0x0068
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#define NDF_OFFSET 0
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#define NDF_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SSIENR_ADDR 0x0064
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#define HW_TX_EB_OFFSET 2
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#define HW_TX_EB_MASK 0x00000004
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#define HW_RX_EB_OFFSET 1
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#define HW_RX_EB_MASK 0x00000002
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#define SSI_EN_OFFSET 0
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#define SSI_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_MWCR_ADDR 0x0060
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#define MHS_OFFSET 2
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#define MHS_MASK 0x00000004
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#define MDD_OFFSET 1
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#define MDD_MASK 0x00000002
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#define MWMOD_OFFSET 0
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#define MWMOD_MASK 0x00000001
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//-----------------------------------
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#define CFG_SER_ADDR 0x005c
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#define SER_OFFSET 0
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#define SER_MASK 0x00000001
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//-----------------------------------
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#define CFG_BAUDR_ADDR 0x0058
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#define SCKDV_OFFSET 0
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#define SCKDV_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TXFTLR_ADDR 0x0054
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#define TFT_OFFSET 0
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#define TFT_MASK 0x0000000F
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//-----------------------------------
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#define CFG_RXFTLR_ADDR 0x0050
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#define RFT_OFFSET 0
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#define RFT_MASK 0x0000000F
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//-----------------------------------
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#define CFG_TXFLR_ADDR 0x004C
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#define TFFLR_OFFSET 0
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#define TFFLR_MASK 0x0000000F
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//-----------------------------------
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#define CFG_RXFLR_ADDR 0x0048
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#define RFFLR_OFFSET 0
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#define RFFLR_MASK 0x0000000F
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//-----------------------------------
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#define CFG_SR_ADDR 0x0044
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#define DCOL_OFFSET 6
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#define DCOL_MASK 0x00000040
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#define TXE_OFFSET 5
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#define TXE_MASK 0x00000020
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#define RFF_OFFSET 4
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#define RFF_MASK 0x00000010
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#define RFNE_OFFSET 3
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#define RFNE_MASK 0x00000008
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#define TFE_OFFSET 2
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#define TFE_MASK 0x00000004
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#define TFNF_OFFSET 1
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#define TFNF_MASK 0x00000002
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#define BUSY_OFFSET 0
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#define BUSY_MASK 0x00000001
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//-----------------------------------
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#define CFG_IMR_ADDR 0x0040
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#define MSTIM_OFFSET 5
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#define MSTIM_MASK 0x00000020
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#define RXFIM_OFFSET 4
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#define RXFIM_MASK 0x00000010
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#define RXOIM_OFFSET 3
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#define RXOIM_MASK 0x00000008
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#define RXUIM_OFFSET 2
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#define RXUIM_MASK 0x00000004
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#define TXOIM_OFFSET 1
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#define TXOIM_MASK 0x00000002
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#define TXEIM_OFFSET 0
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#define TXEIM_MASK 0x00000001
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//-----------------------------------
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#define CFG_ISR_ADDR 0x003c
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#define MSTIS_OFFSET 5
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#define MSTIS_MASK 0x00000020
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#define RXFIS_OFFSET 4
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#define RXFIS_MASK 0x00000010
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#define RXOIS_OFFSET 3
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#define RXOIS_MASK 0x00000008
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#define RXUIS_OFFSET 2
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#define RXUIS_MASK 0x00000004
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#define TXOIS_OFFSET 1
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#define TXOIS_MASK 0x00000002
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#define TXEIS_OFFSET 0
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#define TXEIS_MASK 0x00000001
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//-----------------------------------
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#define CFG_RISR_ADDR 0x0038
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#define MSTIR_OFFSET 5
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#define MSTIR_MASK 0x00000020
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#define RXFIR_OFFSET 4
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#define RXFIR_MASK 0x00000010
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#define RXOIR_OFFSET 3
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#define RXOIR_MASK 0x00000008
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#define RXUIR_OFFSET 2
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#define RXUIR_MASK 0x00000004
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#define TXOIR_OFFSET 1
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#define TXOIR_MASK 0x00000002
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#define TXEIR_OFFSET 0
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#define TXEIR_MASK 0x00000001
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//-----------------------------------
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#define CFG_TXOICR_ADDR 0x0034
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#define TXOCIR_OFFSET 0
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#define TXOCIR_MASK 0x00000001
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//-----------------------------------
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#define CFG_RXOICR_ADDR 0x0030
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#define RXOCIR_OFFSET 0
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#define RXOCIR_MASK 0x00000001
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//-----------------------------------
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#define CFG_RXUICR_ADDR 0x002c
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#define RXUCIR_OFFSET 0
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#define RXUCIR_MASK 0x00000001
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//-----------------------------------
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#define CFG_MXTICR_ADDR 0x0028
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#define MSTCIR_OFFSET 0
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#define MSTCIR_MASK 0x00000001
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//-----------------------------------
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#define CFG_ICR_ADDR 0x0024
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#define ICR_OFFSET 0
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#define ICR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMACR_ADDR 0x0020
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#define TDMAE_OFFSET 1
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#define TDMAE_MASK 0x00000002
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#define RDMAE_OFFSET 0
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#define RDMAE_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMATDLR_ADDR 0x001C
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#define DMATDL_OFFSET 0
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#define DMATDL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DMARDLR_ADDR 0x0018
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#define DMARDL_OFFSET 0
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#define DMARDL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_IDR_ADDR 0x0014
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//-----------------------------------
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#define CFG_SSI_VERSION_ID_ADDR 0x0010
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//-----------------------------------
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#define CFG_RX_SAMPLE_DLY_ADDR 0x000c
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#define RSD_OFFSET 0
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#define RSD_MASK 0x000000FF
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//-----------------------------------
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#define CFG_SPI_CTRLR0_ADDR 0x0008
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#define RSVD_SPI_CTRLR0_OFFSET 19
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#define RSVD_SPI_CTRLR0_MASK 0xFFF80000
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#define SPI_RXDS_EN_OFFSET 18
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#define SPI_RXDS_EN_MASK 0x00040000
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#define INST_DDR_EN_OFFSET 17
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#define INST_DDR_EN_MASK 0x00020000
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#define SPI_DDR_EN_OFFSET 16
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#define SPI_DDR_EN_MASK 0x00010000
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#define WAIT_CYCLES_OFFSET 11
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#define WAIT_CYCLES_MASK 0x0000F800
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#define RSVD_SPI_CTRLR0_10_OFFSET 10
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#define RSVD_SPI_CTRLR0_10_MASK 0x00000400
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#define INST_L_OFFSET 8
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#define INST_L_MASK 0x00000300
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#define RSVD_SPI_CTRLR0_6_7_OFFSET 6
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#define RSVD_SPI_CTRLR0_6_7_MASK 0x000000C0
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#define ADDR_L_OFFSET 2
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#define ADDR_L_MASK 0x0000003C
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#define TRANS_TYPE_OFFSET 0
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#define TRANS_TYPE_MASK 0x00000003
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//-----------------------------------
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#define CFG_TXD_DRIVE_EDGE_ADDR 0x0004
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#define TDE_OFFSET 0
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#define TDE_MASK 0x000000FF
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//-----------------------------------
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#define CFG_RSVD_ADDR 0x0000
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//-----------------------------------
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#define CFG_DR0_ADDR 0x0070
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#define DR0_OFFSET 0
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#define DR0_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR1_ADDR 0x0074
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#define DR1_OFFSET 0
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#define DR1_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR2_ADDR 0x0078
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#define DR2_OFFSET 0
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#define DR2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR3_ADDR 0x007c
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#define DR3_OFFSET 0
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#define DR3_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR4_ADDR 0x0080
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#define DR4_OFFSET 0
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#define DR4_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR5_ADDR 0x0084
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#define DR5_OFFSET 0
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#define DR5_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR6_ADDR 0x0088
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#define DR6_OFFSET 0
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#define DR6_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR7_ADDR 0x008c
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#define DR7_OFFSET 0
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#define DR7_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR8_ADDR 0x0090
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#define DR8_OFFSET 0
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#define DR8_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR9_ADDR 0x0094
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#define DR9_OFFSET 0
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#define DR9_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR10_ADDR 0x0098
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#define DR10_OFFSET 0
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#define DR10_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR11_ADDR 0x009c
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#define DR11_OFFSET 0
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#define DR11_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR12_ADDR 0x00a0
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#define DR12_OFFSET 0
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#define DR12_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR13_ADDR 0x00a4
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#define DR13_OFFSET 0
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#define DR13_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR14_ADDR 0x00a8
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#define DR14_OFFSET 0
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#define DR14_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR15_ADDR 0x00ac
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#define DR15_OFFSET 0
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#define DR15_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR16_ADDR 0x00b0
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#define DR16_OFFSET 0
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#define DR16_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR17_ADDR 0x00b4
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#define DR17_OFFSET 0
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#define DR17_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR18_ADDR 0x00b8
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#define DR18_OFFSET 0
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#define DR18_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR19_ADDR 0x00bc
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#define DR19_OFFSET 0
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#define DR19_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR20_ADDR 0x00c0
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#define DR20_OFFSET 0
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#define DR20_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR21_ADDR 0x00c4
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#define DR21_OFFSET 0
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#define DR21_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR22_ADDR 0x00c8
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#define DR22_OFFSET 0
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#define DR22_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR23_ADDR 0x00cc
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#define DR23_OFFSET 0
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#define DR23_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR24_ADDR 0x00d0
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#define DR24_OFFSET 0
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#define DR24_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR25_ADDR 0x00d4
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#define DR25_OFFSET 0
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#define DR25_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR26_ADDR 0x00d8
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#define DR26_OFFSET 0
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#define DR26_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR27_ADDR 0x00dc
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#define DR27_OFFSET 0
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#define DR27_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR28_ADDR 0x00e0
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#define DR28_OFFSET 0
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#define DR28_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR29_ADDR 0x00e4
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#define DR29_OFFSET 0
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#define DR29_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR30_ADDR 0x00e8
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#define DR30_OFFSET 0
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#define DR30_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR31_ADDR 0x00ec
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#define DR31_OFFSET 0
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#define DR31_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR32_ADDR 0x00f0
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#define DR32_OFFSET 0
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#define DR32_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR33_ADDR 0x00f4
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#define DR33_OFFSET 0
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#define DR33_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR34_ADDR 0x00f8
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#define DR34_OFFSET 0
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#define DR34_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_DR35_ADDR 0x00fc
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#define DR35_OFFSET 0
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#define DR35_MASK 0x0000FFFF
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//HW module read/write macro
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#define SPI_READ_REG(addr) SOC_READ_REG(SPI_BASEADDR + addr)
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#define SPI_WRITE_REG(addr,value) SOC_WRITE_REG(SPI_BASEADDR + addr,value)
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#define SPI1_READ_REG(addr) SOC_READ_REG(SPI1_BASEADDR + addr)
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#define SPI1_WRITE_REG(addr,value) SOC_WRITE_REG(SPI1_BASEADDR + addr,value)
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#define SPI2_READ_REG(addr) SOC_READ_REG(SPI2_BASEADDR + addr)
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#define SPI2_WRITE_REG(addr,value) SOC_WRITE_REG(SPI2_BASEADDR + addr,value)
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