144 lines
4.6 KiB
C
144 lines
4.6 KiB
C
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//-----------------------------------
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#define CFG_AUDIO_FFT_VER_ADDR 0x0000
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#define SW_AFFT_VERSION_OFFSET 0
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#define SW_AFFT_VERSION_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_AFFT_CMD_ADDR 0x0004
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#define SW_FFT_EN_OFFSET 4
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#define SW_FFT_EN_MASK 0x00000010
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#define SW_FFT_INIT_DONE_OFFSET 3
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#define SW_FFT_INIT_DONE_MASK 0x00000008
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#define SW_FFT_SRST_OFFSET 2
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#define SW_FFT_SRST_MASK 0x00000004
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#define SW_FFT_DONE_OFFSET 1
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#define SW_FFT_DONE_MASK 0x00000002
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#define SW_TRIG_IN_OFFSET 0
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#define SW_TRIG_IN_MASK 0x00000001
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//-----------------------------------
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#define CFG_AFFT_CFG_ADDR 0x0008
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#define SW_FFT_CORE_ST_OFFSET 29
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#define SW_FFT_CORE_ST_MASK 0xE0000000
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#define SW_FFT_CTRL_ST_OFFSET 26
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#define SW_FFT_CTRL_ST_MASK 0x1C000000
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#define SW_FFT_WIN_SEL_OFFSET 24
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#define SW_FFT_WIN_SEL_MASK 0x03000000
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#define SW_INVERT_IFFT_DATA_N_OFFSET 18
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#define SW_INVERT_IFFT_DATA_N_MASK 0x00040000
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#define SW_DISABLE_SQRT_OFFSET 17
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#define SW_DISABLE_SQRT_MASK 0x00020000
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#define SW_INIT_ALL_MEM_OFFSET 16
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#define SW_INIT_ALL_MEM_MASK 0x00010000
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#define SW_AHB_BYTES_OFFSET 13
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#define SW_AHB_BYTES_MASK 0x0000E000
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#define SW_IS_SIGNED_EXT_OFFSET 12
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#define SW_IS_SIGNED_EXT_MASK 0x00001000
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#define SW_CLK_FORCE_ON_OFFSET 8
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#define SW_CLK_FORCE_ON_MASK 0x00000100
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#define SW_DATA_MODE_OFFSET 5
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#define SW_DATA_MODE_MASK 0x000000E0
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#define SW_IS_COMPLEX_OFFSET 4
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#define SW_IS_COMPLEX_MASK 0x00000010
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#define SW_IS_FFT_OFFSET 3
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#define SW_IS_FFT_MASK 0x00000008
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#define SW_FFT_SIZE_OFFSET 0
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#define SW_FFT_SIZE_MASK 0x00000007
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//-----------------------------------
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#define CFG_AFFT_SHIFT_ADDR 0x000C
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#define SW_IN_LSH_BIT_SEL_OFFSET 13
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#define SW_IN_LSH_BIT_SEL_MASK 0x00006000
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#define SW_OUT_RSH_BIT_SEL_OFFSET 10
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#define SW_OUT_RSH_BIT_SEL_MASK 0x00001C00
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#define SW_FFT_STAGE4_SHIFT_OFFSET 8
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#define SW_FFT_STAGE4_SHIFT_MASK 0x00000300
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#define SW_FFT_STAGE3_SHIFT_OFFSET 6
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#define SW_FFT_STAGE3_SHIFT_MASK 0x000000C0
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#define SW_FFT_STAGE2_SHIFT_OFFSET 4
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#define SW_FFT_STAGE2_SHIFT_MASK 0x00000030
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#define SW_FFT_STAGE1_SHIFT_OFFSET 2
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#define SW_FFT_STAGE1_SHIFT_MASK 0x0000000C
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#define SW_FFT_STAGE0_SHIFT_OFFSET 0
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#define SW_FFT_STAGE0_SHIFT_MASK 0x00000003
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//-----------------------------------
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#define CFG_AFFT_FLT_ADDR 0x0010
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#define SW_I2FLT_ST_OFFSET 24
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#define SW_I2FLT_ST_MASK 0xFF000000
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#define SW_FLT2I_ST_OFFSET 16
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#define SW_FLT2I_ST_MASK 0x00FF0000
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#define SW_IGNORE_FLT2I_ST_OFFSET 8
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#define SW_IGNORE_FLT2I_ST_MASK 0x00000100
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#define SW_FLT_ST_CLR_OFFSET 4
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#define SW_FLT_ST_CLR_MASK 0x00000010
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#define SW_FLT_RND_SEL_OFFSET 0
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#define SW_FLT_RND_SEL_MASK 0x00000007
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//-----------------------------------
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#define CFG_AFFT_FLT_EXP_ADDR 0x0014
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#define SW_FLTOUT_EXP_BIAS_OFFSET 18
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#define SW_FLTOUT_EXP_BIAS_MASK 0x03FC0000
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#define SW_FLT_EXP_BIAS_OVR_EN_OFFSET 17
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#define SW_FLT_EXP_BIAS_OVR_EN_MASK 0x00020000
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#define FLT_EXP_BIAS_OFFSET 8
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#define FLT_EXP_BIAS_MASK 0x0001FF00
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#define SW_FLT_EXP_THRE_OFFSET 0
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#define SW_FLT_EXP_THRE_MASK 0x000000FF
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//-----------------------------------
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#define CFG_AFFT_FLT2I_REG0_ADDR 0x0020
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#define SW_FLT2I_REG0_OFFSET 0
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#define SW_FLT2I_REG0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AFFT_FLT2I_REG1_ADDR 0x0024
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#define SW_FLT2I_REG1_OFFSET 0
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#define SW_FLT2I_REG1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AFFT_FLT2I_REG2_ADDR 0x0028
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#define SW_FLT2I_REG2_OFFSET 0
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#define SW_FLT2I_REG2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AFFT_FLT2I_REG3_ADDR 0x002C
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#define SW_FLT2I_REG3_OFFSET 0
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#define SW_FLT2I_REG3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AFFT_AHB_RD_ADDR_ADDR 0x0030
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#define SW_AHB_RD_ADDR_OFFSET 0
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#define SW_AHB_RD_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AFFT_AHB_WR_ADDR_ADDR 0x0034
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#define SW_AHB_WR_ADDR_OFFSET 0
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#define SW_AHB_WR_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AFFT_INT_RAW_ADDR 0x0040
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#define FFT_DONE_INT_RAW_OFFSET 0
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#define FFT_DONE_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_AFFT_INT_ST_ADDR 0x0044
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#define FFT_DONE_INT_ST_OFFSET 0
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#define FFT_DONE_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_AFFT_INT_ENA_ADDR 0x0048
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#define FFT_DONE_INT_ENA_OFFSET 0
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#define FFT_DONE_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_AFFT_INT_CLR_ADDR 0x004C
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#define FFT_DONE_INT_CLR_OFFSET 0
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#define FFT_DONE_INT_CLR_MASK 0x00000001
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//HW module read/write macro
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#define AFFT_READ_REG(addr) SOC_READ_REG(AFFT_REG_BASEADDR + addr)
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#define AFFT_WRITE_REG(addr,value) SOC_WRITE_REG(AFFT_REG_BASEADDR + addr,value)
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