581 lines
19 KiB
C
581 lines
19 KiB
C
|
|
//-----------------------------------
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|
#define CFG_AHB_RVER_ADDR 0x0000
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|
#define AHB_RF_VER_OFFSET 0
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|
#define AHB_RF_VER_MASK 0x0000FFFF
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|
|
|
//-----------------------------------
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|
#define CFG_AHB_REG0_ADDR 0x0004
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|
#define FFT_SOFT_RST_OFFSET 31
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|
#define FFT_SOFT_RST_MASK 0x80000000
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|
#define GMAC_SOFT_RST_OFFSET 29
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|
#define GMAC_SOFT_RST_MASK 0x20000000
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#define RFPLC_MAC_SOFT_RST_OFFSET 28
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|
#define RFPLC_MAC_SOFT_RST_MASK 0x10000000
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#define RFPLC_MAC_REG_SOFT_RST_OFFSET 27
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#define RFPLC_MAC_REG_SOFT_RST_MASK 0x08000000
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#define RFPLC_PHY_SOFT_RST_OFFSET 26
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#define RFPLC_PHY_SOFT_RST_MASK 0x04000000
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#define RFPLC_PHY_REG_SOFT_RST_OFFSET 25
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#define RFPLC_PHY_REG_SOFT_RST_MASK 0x02000000
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#define RFPLC_ANA_SOFT_RST_OFFSET 24
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#define RFPLC_ANA_SOFT_RST_MASK 0x01000000
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#define FDMA_SLV_SOFT_RST_OFFSET 22
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|
#define FDMA_SLV_SOFT_RST_MASK 0x00400000
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#define RFPLL_SDM_SOFT_RST_OFFSET 21
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#define RFPLL_SDM_SOFT_RST_MASK 0x00200000
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#define SW_DMA2_SOFT_RST_OFFSET 20
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#define SW_DMA2_SOFT_RST_MASK 0x00100000
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#define MAC_SOFT_RST_OFFSET 19
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#define MAC_SOFT_RST_MASK 0x00080000
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#define MAC_REG_SOFT_RST_OFFSET 18
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#define MAC_REG_SOFT_RST_MASK 0x00040000
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#define PHY_SOFT_RST_OFFSET 17
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#define PHY_SOFT_RST_MASK 0x00020000
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#define PHY_REG_SOFT_RST_OFFSET 16
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#define PHY_REG_SOFT_RST_MASK 0x00010000
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#define PHY_ANA_SOFT_RST_OFFSET 15
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#define PHY_ANA_SOFT_RST_MASK 0x00008000
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#define ADA_SOFT_RST_OFFSET 14
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#define ADA_SOFT_RST_MASK 0x00004000
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#define SW_DMA1_SOFT_RST_OFFSET 13
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#define SW_DMA1_SOFT_RST_MASK 0x00002000
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#define SW_DMA0_SOFT_RST_OFFSET 12
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#define SW_DMA0_SOFT_RST_MASK 0x00001000
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#define EMC_SOFT_RST_OFFSET 11
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#define EMC_SOFT_RST_MASK 0x00000800
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#define SEC_AES_SOFT_RST_OFFSET 10
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#define SEC_AES_SOFT_RST_MASK 0x00000400
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#define SEC0_SOFT_RST_OFFSET 9
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#define SEC0_SOFT_RST_MASK 0x00000200
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#define DCACHE1_SOFT_RST_OFFSET 8
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#define DCACHE1_SOFT_RST_MASK 0x00000100
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#define DCACHE0_SOFT_RST_OFFSET 7
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#define DCACHE0_SOFT_RST_MASK 0x00000080
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#define ICACHE2_SOFT_RST_OFFSET 6
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#define ICACHE2_SOFT_RST_MASK 0x00000040
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#define ICACHE1_SOFT_RST_OFFSET 5
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#define ICACHE1_SOFT_RST_MASK 0x00000020
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#define ICACHE0_SOFT_RST_OFFSET 4
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#define ICACHE0_SOFT_RST_MASK 0x00000010
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#define SEC_SM4_SOFT_RST_OFFSET 3
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#define SEC_SM4_SOFT_RST_MASK 0x00000008
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#define CORE2_SOFT_RST_OFFSET 2
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#define CORE2_SOFT_RST_MASK 0x00000004
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#define CORE1_SOFT_RST_OFFSET 1
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#define CORE1_SOFT_RST_MASK 0x00000002
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#define CORE0_SOFT_RST_OFFSET 0
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#define CORE0_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_REG1_ADDR 0x0008
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#define FFT_EB_OFFSET 31
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#define FFT_EB_MASK 0x80000000
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#define USB_EB_OFFSET 30
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#define USB_EB_MASK 0x40000000
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#define GMAC_EB_OFFSET 29
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#define GMAC_EB_MASK 0x20000000
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#define RFPLC_MAC_EB_OFFSET 28
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#define RFPLC_MAC_EB_MASK 0x10000000
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#define RFPLC_MAC_REG_EB_OFFSET 27
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#define RFPLC_MAC_REG_EB_MASK 0x08000000
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#define RFPLC_PHY_EB_OFFSET 26
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#define RFPLC_PHY_EB_MASK 0x04000000
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#define RFPLC_PHY_REG_EB_OFFSET 25
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#define RFPLC_PHY_REG_EB_MASK 0x02000000
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#define RFPLC_ANA_EB_OFFSET 24
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#define RFPLC_ANA_EB_MASK 0x01000000
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#define FDMA_SLV_EB_OFFSET 22
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#define FDMA_SLV_EB_MASK 0x00400000
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#define RFPLL_SDM_EB_OFFSET 21
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#define RFPLL_SDM_EB_MASK 0x00200000
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#define SW_DMA2_EB_OFFSET 20
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#define SW_DMA2_EB_MASK 0x00100000
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#define PLC_MAC_EB_OFFSET 19
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#define PLC_MAC_EB_MASK 0x00080000
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#define PLC_MAC_REG_EB_OFFSET 18
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#define PLC_MAC_REG_EB_MASK 0x00040000
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#define PLC_PHY_EB_OFFSET 17
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#define PLC_PHY_EB_MASK 0x00020000
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#define PLC_PHY_REG_EB_OFFSET 16
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#define PLC_PHY_REG_EB_MASK 0x00010000
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#define PLC_ANA_EB_OFFSET 15
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#define PLC_ANA_EB_MASK 0x00008000
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#define ADA_EB_OFFSET 14
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#define ADA_EB_MASK 0x00004000
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#define SW_DMA1_EB_OFFSET 13
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#define SW_DMA1_EB_MASK 0x00002000
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#define SW_DMA0_EB_OFFSET 12
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#define SW_DMA0_EB_MASK 0x00001000
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#define EMC_EB_OFFSET 11
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#define EMC_EB_MASK 0x00000800
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#define SEC_AES_EB_OFFSET 10
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#define SEC_AES_EB_MASK 0x00000400
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#define SEC0_EB_OFFSET 9
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#define SEC0_EB_MASK 0x00000200
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#define DCACHE1_EB_OFFSET 8
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#define DCACHE1_EB_MASK 0x00000100
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#define DCACHE0_EB_OFFSET 7
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#define DCACHE0_EB_MASK 0x00000080
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#define ICACHE2_EB_OFFSET 6
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#define ICACHE2_EB_MASK 0x00000040
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#define ICACHE1_EB_OFFSET 5
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#define ICACHE1_EB_MASK 0x00000020
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#define ICACHE0_EB_OFFSET 4
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#define ICACHE0_EB_MASK 0x00000010
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#define SEC_SM4_EB_OFFSET 3
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#define SEC_SM4_EB_MASK 0x00000008
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#define CORE2_EB_OFFSET 2
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#define CORE2_EB_MASK 0x00000004
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#define CORE1_EB_OFFSET 1
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#define CORE1_EB_MASK 0x00000002
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#define CORE0_EB_OFFSET 0
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#define CORE0_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_REG2_ADDR 0x000C
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#define USB_SYS_SOFT_RST_OFFSET 4
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#define USB_SYS_SOFT_RST_MASK 0x00000010
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#define USB_MAC_SOFT_RST_OFFSET 3
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#define USB_MAC_SOFT_RST_MASK 0x00000008
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#define USB_MAC_UTMI_SOFT_RST_OFFSET 2
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#define USB_MAC_UTMI_SOFT_RST_MASK 0x00000004
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#define USB_PHY_UTMI_SOFT_RST_OFFSET 1
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#define USB_PHY_UTMI_SOFT_RST_MASK 0x00000002
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#define USB_PHY_SOFT_RST_OFFSET 0
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#define USB_PHY_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_REG_LOCK_ADDR 0x001C
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#define AHB_REG3_UNLOCK_OFFSET 3
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#define AHB_REG3_UNLOCK_MASK 0x00000008
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#define AHB_REG2_UNLOCK_OFFSET 2
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#define AHB_REG2_UNLOCK_MASK 0x00000004
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#define AHB_REG1_UNLOCK_OFFSET 1
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#define AHB_REG1_UNLOCK_MASK 0x00000002
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#define AHB_REG0_UNLOCK_OFFSET 0
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#define AHB_REG0_UNLOCK_MASK 0x00000001
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//-----------------------------------
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#define CFG_CPU0_START_PC_ADDR 0x0020
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#define CORE0_START_PC_OFFSET 0
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#define CORE0_START_PC_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CPU1_START_PC_ADDR 0x0024
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#define CORE1_START_PC_OFFSET 0
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#define CORE1_START_PC_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CPU2_START_PC_ADDR 0x0028
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#define CORE2_START_PC_OFFSET 0
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#define CORE2_START_PC_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLASH_AES_KEY0_ADDR 0x0030
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#define FLASH_AES_KEY0_OFFSET 0
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#define FLASH_AES_KEY0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLASH_AES_KEY1_ADDR 0x0034
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#define FLASH_AES_KEY1_OFFSET 0
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#define FLASH_AES_KEY1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLASH_AES_KEY2_ADDR 0x0038
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#define FLASH_AES_KEY2_OFFSET 0
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#define FLASH_AES_KEY2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLASH_AES_KEY3_ADDR 0x003C
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#define FLASH_AES_KEY3_OFFSET 0
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#define FLASH_AES_KEY3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AHB_DBG_CFG_ADDR 0x0040
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#define CLK_TEST_DIV_OFFSET 18
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#define CLK_TEST_DIV_MASK 0x003C0000
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#define CLK_TEST_SEL_OFFSET 14
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#define CLK_TEST_SEL_MASK 0x0003C000
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#define CHIP_DBG_BUS_SHIFT_OFFSET 8
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#define CHIP_DBG_BUS_SHIFT_MASK 0x00003F00
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#define CHIP_DBG_BUS_SEL1_OFFSET 4
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#define CHIP_DBG_BUS_SEL1_MASK 0x000000F0
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#define CHIP_DBG_BUS_SEL0_OFFSET 0
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#define CHIP_DBG_BUS_SEL0_MASK 0x0000000F
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//-----------------------------------
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#define CFG_AHB_DBG_BUS_ADDR 0x0044
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#define CHIP_STATUS_OUT32_OFFSET 0
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#define CHIP_STATUS_OUT32_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_AHB_CORE0_CFG0_ADDR 0x0048
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#define CORE0_WFI_CLK_ENA_OFFSET 10
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#define CORE0_WFI_CLK_ENA_MASK 0x00000400
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#define CORE0_D_EXP_MASK_OFFSET 4
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#define CORE0_D_EXP_MASK_MASK 0x000003F0
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#define CORE0_I_EXP_MASK_OFFSET 3
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#define CORE0_I_EXP_MASK_MASK 0x00000008
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#define CORE0_SIMD_EB_OFFSET 2
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#define CORE0_SIMD_EB_MASK 0x00000004
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#define CORE0_BTB_EB_OFFSET 1
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#define CORE0_BTB_EB_MASK 0x00000002
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#define CORE0_BIU_PATCH_EN_OFFSET 0
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#define CORE0_BIU_PATCH_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_CORE0_CFG1_ADDR 0x004C
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#define CORE0_D_ACCESS_EN_OFFSET 16
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#define CORE0_D_ACCESS_EN_MASK 0xFFFF0000
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#define CORE0_I_ACCESS_EN_OFFSET 0
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#define CORE0_I_ACCESS_EN_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_AHB_CORE1_CFG0_ADDR 0x0050
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#define CORE1_WFI_CLK_ENA_OFFSET 10
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#define CORE1_WFI_CLK_ENA_MASK 0x00000400
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#define CORE1_D_EXP_MASK_OFFSET 4
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#define CORE1_D_EXP_MASK_MASK 0x000003F0
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#define CORE1_I_EXP_MASK_OFFSET 3
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#define CORE1_I_EXP_MASK_MASK 0x00000008
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#define CORE1_SIMD_EB_OFFSET 2
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#define CORE1_SIMD_EB_MASK 0x00000004
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#define CORE1_BTB_EB_OFFSET 1
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#define CORE1_BTB_EB_MASK 0x00000002
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#define CORE1_BIU_PATCH_EN_OFFSET 0
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#define CORE1_BIU_PATCH_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_AHB_CORE1_CFG1_ADDR 0x0054
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#define CORE1_D_ACCESS_EN_OFFSET 16
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#define CORE1_D_ACCESS_EN_MASK 0xFFFF0000
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#define CORE1_I_ACCESS_EN_OFFSET 0
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#define CORE1_I_ACCESS_EN_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_AHB_CORE2_CFG0_ADDR 0x0058
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#define CORE2_WFI_CLK_ENA_OFFSET 10
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#define CORE2_WFI_CLK_ENA_MASK 0x00000400
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#define CORE2_D_EXP_MASK_OFFSET 4
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#define CORE2_D_EXP_MASK_MASK 0x000003F0
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#define CORE2_I_EXP_MASK_OFFSET 3
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#define CORE2_I_EXP_MASK_MASK 0x00000008
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#define CORE2_SIMD_EB_OFFSET 2
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#define CORE2_SIMD_EB_MASK 0x00000004
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#define CORE2_BTB_EB_OFFSET 1
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#define CORE2_BTB_EB_MASK 0x00000002
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#define CORE2_BIU_PATCH_EN_OFFSET 0
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#define CORE2_BIU_PATCH_EN_MASK 0x00000001
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|
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//-----------------------------------
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#define CFG_AHB_CORE2_CFG1_ADDR 0x005c
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#define CORE2_D_ACCESS_EN_OFFSET 16
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#define CORE2_D_ACCESS_EN_MASK 0xFFFF0000
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#define CORE2_I_ACCESS_EN_OFFSET 0
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#define CORE2_I_ACCESS_EN_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_AHB_AP_CLK_CFG_ADDR 0x0060
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#define D_MDLL_COUT_FRC_EN_OFFSET 22
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#define D_MDLL_COUT_FRC_EN_MASK 0x00400000
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#define D_MDLL_ENLOOP_OFFSET 21
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#define D_MDLL_ENLOOP_MASK 0x00200000
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#define D_MDLL_EN_DIGCLK_OFFSET 20
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#define D_MDLL_EN_DIGCLK_MASK 0x00100000
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#define CLK_APB_FORCE_ON_OFFSET 19
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|
#define CLK_APB_FORCE_ON_MASK 0x00080000
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#define CLK_AHB_FORCE_ON_OFFSET 18
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#define CLK_AHB_FORCE_ON_MASK 0x00040000
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#define PLC_CLK_GEN_FORCE_ON_OFFSET 17
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#define PLC_CLK_GEN_FORCE_ON_MASK 0x00020000
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#define CLK_RFPLC_WAFE_MCLK_SEL_OFFSET 16
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#define CLK_RFPLC_WAFE_MCLK_SEL_MASK 0x00010000
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#define CLK_SOC_FORCE_OFF_OFFSET 15
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#define CLK_SOC_FORCE_OFF_MASK 0x00008000
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#define CLK_PTP_REF_GMAC_DIV_OFFSET 13
|
|
#define CLK_PTP_REF_GMAC_DIV_MASK 0x00006000
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#define CLK_RMII_GMAC_SEL_OFFSET 12
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#define CLK_RMII_GMAC_SEL_MASK 0x00001000
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#define CLK_APB_SEL_OFFSET 9
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#define CLK_APB_SEL_MASK 0x00000200
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#define CLK_APB_DIV_OFFSET 6
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#define CLK_APB_DIV_MASK 0x000001C0
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#define CLK_AHB_SEL_OFFSET 2
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#define CLK_AHB_SEL_MASK 0x0000000C
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|
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//-----------------------------------
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#define CFG_AHB_ANA_PIN_CFG_ADDR 0x0064
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#define EN_DIGPAD1_OFFSET 1
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|
#define EN_DIGPAD1_MASK 0x00000002
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#define EN_DIGPAD0_OFFSET 0
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#define EN_DIGPAD0_MASK 0x00000001
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|
|
|
//-----------------------------------
|
|
#define CFG_AHB_FDMA_SLV_CFG_ADDR 0x0068
|
|
#define FDMA_SLV_RST_CPU_EN_OFFSET 0
|
|
#define FDMA_SLV_RST_CPU_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_EMC_PHY_CFG_ADDR 0x006c
|
|
#define SFC_IO_FROM_GPIO_MTX_OFFSET 26
|
|
#define SFC_IO_FROM_GPIO_MTX_MASK 0x04000000
|
|
#define SFC_SO_BAK_PAD_ENA_OFFSET 25
|
|
#define SFC_SO_BAK_PAD_ENA_MASK 0x02000000
|
|
#define SFC_SI_BAK_PAD_ENA_OFFSET 24
|
|
#define SFC_SI_BAK_PAD_ENA_MASK 0x01000000
|
|
#define SMC_CLK_PAD_SEL_OFFSET 21
|
|
#define SMC_CLK_PAD_SEL_MASK 0x00E00000
|
|
#define SFC_CLK_PAD_SEL_OFFSET 17
|
|
#define SFC_CLK_PAD_SEL_MASK 0x001E0000
|
|
#define SMC_PHY_ENA_OFFSET 9
|
|
#define SMC_PHY_ENA_MASK 0x0001FE00
|
|
#define SFC_PHY_ENA_OFFSET 0
|
|
#define SFC_PHY_ENA_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCRATCH0_ADDR 0x70
|
|
#define SCRATCH0_OFFSET 0
|
|
#define SCRATCH0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCRATCH1_ADDR 0x74
|
|
#define SCRATCH1_OFFSET 0
|
|
#define SCRATCH1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCRATCH2_ADDR 0x78
|
|
#define SCRATCH2_OFFSET 0
|
|
#define SCRATCH2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCRATCH3_ADDR 0x7c
|
|
#define SCRATCH3_OFFSET 0
|
|
#define SCRATCH3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCRATCH4_ADDR 0x80
|
|
#define SCRATCH4_OFFSET 0
|
|
#define SCRATCH4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SCRATCH5_ADDR 0x84
|
|
#define SCRATCH5_OFFSET 0
|
|
#define SCRATCH5_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE0_RNMI_INT_VECTOR_ADDR 0x90
|
|
#define CORE0_RNMI_INT_VECTOR_OFFSET 0
|
|
#define CORE0_RNMI_INT_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE0_RNIM_EXP_VECTOR_ADDR 0x94
|
|
#define CORE0_RNMI_EXP_VECTOR_OFFSET 0
|
|
#define CORE0_RNMI_EXP_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE0_UNMI_INT_VECTOR_ADDR 0x98
|
|
#define CORE0_UNMI_INT_VECTOR_OFFSET 0
|
|
#define CORE0_UNMI_INT_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE0_UNIM_EXP_VECTOR_ADDR 0x9c
|
|
#define CORE0_UNMI_EXP_VECTOR_OFFSET 0
|
|
#define CORE0_UNMI_EXP_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE1_RNMI_INT_VECTOR_ADDR 0xA0
|
|
#define CORE1_RNMI_INT_VECTOR_OFFSET 0
|
|
#define CORE1_RNMI_INT_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE1_RNIM_EXP_VECTOR_ADDR 0xA4
|
|
#define CORE1_RNMI_EXP_VECTOR_OFFSET 0
|
|
#define CORE1_RNMI_EXP_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE1_UNMI_INT_VECTOR_ADDR 0xA8
|
|
#define CORE1_UNMI_INT_VECTOR_OFFSET 0
|
|
#define CORE1_UNMI_INT_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_CORE1_UNIM_EXP_VECTOR_ADDR 0xAc
|
|
#define CORE1_UNMI_EXP_VECTOR_OFFSET 0
|
|
#define CORE1_UNMI_EXP_VECTOR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
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#define CFG_CORE2_RNMI_INT_VECTOR_ADDR 0xB0
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#define CORE2_RNMI_INT_VECTOR_OFFSET 0
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#define CORE2_RNMI_INT_VECTOR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CORE2_RNIM_EXP_VECTOR_ADDR 0xB4
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#define CORE2_RNMI_EXP_VECTOR_OFFSET 0
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#define CORE2_RNMI_EXP_VECTOR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CORE2_UNMI_INT_VECTOR_ADDR 0xB8
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#define CORE2_UNMI_INT_VECTOR_OFFSET 0
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#define CORE2_UNMI_INT_VECTOR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CORE2_UNIM_EXP_VECTOR_ADDR 0xBc
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#define CORE2_UNMI_EXP_VECTOR_OFFSET 0
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#define CORE2_UNMI_EXP_VECTOR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DIG_TOP_ADA_DUMP_MUX_ADDR 0x0100
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#define SW_DIG_TOP_ADA_DUMP_SEL_OFFSET 0
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#define SW_DIG_TOP_ADA_DUMP_SEL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_DCACHE1_MEM_CTRL_ADDR 0x104
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#define DCACHE1_RAM_MODE_OFFSET 0
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#define DCACHE1_RAM_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_MEM_CFG_ADDR 0x0108
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#define MEM_PARA_RELOAD_SW_OFFSET 25
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#define MEM_PARA_RELOAD_SW_MASK 0x02000000
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#define MEM_PARA_RELOAD_SEL_OFFSET 24
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#define MEM_PARA_RELOAD_SEL_MASK 0x01000000
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#define ROM_TEST1_OFFSET 21
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#define ROM_TEST1_MASK 0x00200000
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#define ROM_RM_OFFSET 17
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#define ROM_RM_MASK 0x001E0000
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#define ROM_RME_OFFSET 16
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#define ROM_RME_MASK 0x00010000
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#define RAM_TEST1_OFFSET 13
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#define RAM_TEST1_MASK 0x00002000
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#define RAM_RM_OFFSET 9
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#define RAM_RM_MASK 0x00001E00
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#define RAM_RME_OFFSET 8
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#define RAM_RME_MASK 0x00000100
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#define RAM_RA_OFFSET 6
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#define RAM_RA_MASK 0x000000C0
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#define RAM_WA_OFFSET 3
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#define RAM_WA_MASK 0x00000038
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#define RAM_WPULSE_OFFSET 0
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#define RAM_WPULSE_MASK 0x00000007
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//-----------------------------------
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#define CFG_AHB_MISC_CLK_CFG_ADDR 0x0110
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#define CLK_EFUSE_DIV_OFFSET 24
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#define CLK_EFUSE_DIV_MASK 0x3F000000
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#define CLK_PWM_SEL_OFFSET 20
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#define CLK_PWM_SEL_MASK 0x00100000
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#define CLK_32K_SEL_OFFSET 19
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#define CLK_32K_SEL_MASK 0x00080000
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#define CLK_32K_DIV_OFFSET 8
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#define CLK_32K_DIV_MASK 0x0007FF00
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#define SW_SYSPLL_CLK_EN_OFFSET 5
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#define SW_SYSPLL_CLK_EN_MASK 0x00000020
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#define CLK_SOC_DIV_OFFSET 0
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#define CLK_SOC_DIV_MASK 0x0000001F
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//-----------------------------------
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#define CFG_CHIP_PAD_STRAP_STATUS0_ADDR 0x0114
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#define CHIP_PAD_STRAP_STATUS0_OFFSET 0
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#define CHIP_PAD_STRAP_STATUS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CHIP_PAD_STRAP_STATUS1_ADDR 0x0118
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#define CHIP_PAD_STRAP_STATUS1_OFFSET 0
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#define CHIP_PAD_STRAP_STATUS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CHIP_PAD_STRAP_STATUS2_ADDR 0x011C
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#define CHIP_PAD_STRAP_STATUS2_OFFSET 0
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#define CHIP_PAD_STRAP_STATUS2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PLC_RFPLC_CLK_CFG_ADDR 0x0120
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#define SW_PLC_MST_BRG_F2S_OFFSET 13
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#define SW_PLC_MST_BRG_F2S_MASK 0x00002000
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#define SW_PLC_SLV_BRG_F2S_OFFSET 12
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#define SW_PLC_SLV_BRG_F2S_MASK 0x00001000
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#define SW_RFPLC_MST_BRG_F2S_OFFSET 11
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#define SW_RFPLC_MST_BRG_F2S_MASK 0x00000800
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#define SW_RFPLC_SLV_BRG_F2S_OFFSET 10
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#define SW_RFPLC_SLV_BRG_F2S_MASK 0x00000400
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#define SW_RFPLC_MST_BRG_ASYNC_OFFSET 9
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#define SW_RFPLC_MST_BRG_ASYNC_MASK 0x00000200
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#define SW_RFPLC_SLV_BRG_ASYNC_OFFSET 8
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#define SW_RFPLC_SLV_BRG_ASYNC_MASK 0x00000100
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#define PLC_MST_BRG_F2S_OVER_ON_OFFSET 5
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#define PLC_MST_BRG_F2S_OVER_ON_MASK 0x00000020
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#define PLC_SLV_BRG_F2S_OVER_ON_OFFSET 4
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#define PLC_SLV_BRG_F2S_OVER_ON_MASK 0x00000010
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#define RFPLC_MST_BRG_F2S_OVER_ON_OFFSET 3
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#define RFPLC_MST_BRG_F2S_OVER_ON_MASK 0x00000008
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#define RFPLC_SLV_BRG_F2S_OVER_ON_OFFSET 2
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#define RFPLC_SLV_BRG_F2S_OVER_ON_MASK 0x00000004
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#define RFPLC_MST_BRG_ASYNC_OVER_ON_OFFSET 1
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#define RFPLC_MST_BRG_ASYNC_OVER_ON_MASK 0x00000002
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#define RFPLC_SLV_BRG_ASYNC_OVER_ON_OFFSET 0
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#define RFPLC_SLV_BRG_ASYNC_OVER_ON_MASK 0x00000001
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|
|
|
//-----------------------------------
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#define CFG_AHB_ROM_PATCH_MAGIC_ADDR 0x0124
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#define ROM_PATCH_MAGIC_NUM_OFFSET 0
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#define ROM_PATCH_MAGIC_NUM_MASK 0x000000FF
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|
|
//-----------------------------------
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#define CFG_AHB_ROM_PATCH0_INDEX_ADDR 0x0128
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#define ROM_PATCH0_VLD_FLAG_OFFSET 20
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#define ROM_PATCH0_VLD_FLAG_MASK 0x00100000
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#define ROM_PATCH0_INDEX_OFFSET 0
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#define ROM_PATCH0_INDEX_MASK 0x000FFFFF
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|
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//-----------------------------------
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#define CFG_AHB_ROM_PATCH1_INDEX_ADDR 0x012C
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#define ROM_PATCH1_VLD_FLAG_OFFSET 20
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#define ROM_PATCH1_VLD_FLAG_MASK 0x00100000
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#define ROM_PATCH1_INDEX_OFFSET 0
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#define ROM_PATCH1_INDEX_MASK 0x000FFFFF
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|
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//-----------------------------------
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#define CFG_AHB_ROM_PATCH2_INDEX_ADDR 0x0130
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#define ROM_PATCH2_VLD_FLAG_OFFSET 20
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#define ROM_PATCH2_VLD_FLAG_MASK 0x00100000
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#define ROM_PATCH2_INDEX_OFFSET 0
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#define ROM_PATCH2_INDEX_MASK 0x000FFFFF
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|
|
|
//-----------------------------------
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#define CFG_AHB_ROM_PATCH3_INDEX_ADDR 0x0134
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#define ROM_PATCH3_VLD_FLAG_OFFSET 20
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#define ROM_PATCH3_VLD_FLAG_MASK 0x00100000
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#define ROM_PATCH3_INDEX_OFFSET 0
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#define ROM_PATCH3_INDEX_MASK 0x000FFFFF
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|
|
|
//-----------------------------------
|
|
#define CFG_AHB_ROM_PATCH0_CONTENT_ADDR 0x0138
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|
#define ROM_PATCH0_CONTENT_OFFSET 0
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|
#define ROM_PATCH0_CONTENT_MASK 0xFFFFFFFF
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|
|
|
//-----------------------------------
|
|
#define CFG_AHB_ROM_PATCH1_CONTENT_ADDR 0x013C
|
|
#define ROM_PATCH1_CONTENT_OFFSET 0
|
|
#define ROM_PATCH1_CONTENT_MASK 0xFFFFFFFF
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|
|
|
//-----------------------------------
|
|
#define CFG_AHB_ROM_PATCH2_CONTENT_ADDR 0x0140
|
|
#define ROM_PATCH2_CONTENT_OFFSET 0
|
|
#define ROM_PATCH2_CONTENT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AHB_ROM_PATCH3_CONTENT_ADDR 0x0144
|
|
#define ROM_PATCH3_CONTENT_OFFSET 0
|
|
#define ROM_PATCH3_CONTENT_MASK 0xFFFFFFFF
|
|
|
|
//HW module read/write macro
|
|
#define AHB_REG_LITE0_READ_REG(addr) SOC_READ_REG(AHB_REG_LITE_BASEADDR + addr)
|
|
#define AHB_REG_LITE0_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_REG_LITE_BASEADDR + addr,value)
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|
|
|
#define AHB_REG_LITE1_READ_REG(addr) SOC_READ_REG(AHB_REG_LITE_SET_BASEADDR + addr)
|
|
#define AHB_REG_LITE1_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_REG_LITE_SET_BASEADDR + addr,value)
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|
|
|
#define AHB_REG_LITE2_READ_REG(addr) SOC_READ_REG(AHB_REG_LITE_CLR_BASEADDR + addr)
|
|
#define AHB_REG_LITE2_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_REG_LITE_CLR_BASEADDR + addr,value)
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