213 lines
6.9 KiB
C
213 lines
6.9 KiB
C
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//-----------------------------------
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#define CFG_ACC_EQ_VER_ADDR 0x0000
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#define SW_EQ_VERSION_OFFSET 0
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#define SW_EQ_VERSION_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_EQ_CMD_ADDR 0x0004
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#define SW_EQ_COEF_DONE_OFFSET 12
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#define SW_EQ_COEF_DONE_MASK 0x00001000
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#define SW_EQ_COEF_START_OFFSET 8
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#define SW_EQ_COEF_START_MASK 0x00000100
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#define SW_EQ_DONE_OFFSET 4
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#define SW_EQ_DONE_MASK 0x00000010
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#define SW_EQ_START_OFFSET 0
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#define SW_EQ_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_ENA_ADDR 0x0008
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#define SW_EQ_CLK_FORCE_ON_OFFSET 16
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#define SW_EQ_CLK_FORCE_ON_MASK 0x00010000
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#define RO_EQ_STATUS_OFFSET 12
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#define RO_EQ_STATUS_MASK 0x00007000
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#define SW_EQ_COEF_EN_OFFSET 8
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#define SW_EQ_COEF_EN_MASK 0x00000100
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#define SW_EQ_SRST_OFFSET 4
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#define SW_EQ_SRST_MASK 0x00000010
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#define SW_EQ_EN_OFFSET 0
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#define SW_EQ_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_SET_ADDR 0x000C
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#define SW_EQ_NOISE_MODE_OFFSET 30
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#define SW_EQ_NOISE_MODE_MASK 0x40000000
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#define SW_EQ_DATA_LEN_OFFSET 20
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#define SW_EQ_DATA_LEN_MASK 0x3FF00000
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#define SW_EQ_BIG_ENDIAN_OFFSET 19
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#define SW_EQ_BIG_ENDIAN_MASK 0x00080000
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#define SW_EQ_DATA_MODE_OFFSET 18
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#define SW_EQ_DATA_MODE_MASK 0x00040000
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#define SW_EQ_START_BAND_OFFSET 12
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#define SW_EQ_START_BAND_MASK 0x0003F000
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#define SW_EQ_DATA_LOAD_MEM_OFFSET 11
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#define SW_EQ_DATA_LOAD_MEM_MASK 0x00000800
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#define SW_EQ_FLT_MODE_OFFSET 10
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#define SW_EQ_FLT_MODE_MASK 0x00000400
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#define SW_EQ_NUM_OFFSET 4
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#define SW_EQ_NUM_MASK 0x000003F0
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#define SW_EQ_AHB_RW_OFFSET 3
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#define SW_EQ_AHB_RW_MASK 0x00000008
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#define SW_EQ_AHB_BYTES_OFFSET 0
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#define SW_EQ_AHB_BYTES_MASK 0x00000007
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//-----------------------------------
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#define CFG_EQ_DATA_RD_ADDR_ADDR 0x00010
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#define SW_EQ_DATA_RD_ADDR_OFFSET 0
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#define SW_EQ_DATA_RD_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_DATA_WR_ADDR_ADDR 0x0014
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#define SW_EQ_DATA_WR_ADDR_OFFSET 0
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#define SW_EQ_DATA_WR_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_SHIFT_ADDR 0x0018
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#define SW_EQ_OUT_RSH_BIT_SEL_OFFSET 4
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#define SW_EQ_OUT_RSH_BIT_SEL_MASK 0x000000F0
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#define SW_EQ_IN_LSH_BIT_SEL_OFFSET 0
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#define SW_EQ_IN_LSH_BIT_SEL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_EQ_FLT_SET_ADDR 0x001C
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#define SW_EQ_I2FLT_ST_OFFSET 24
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#define SW_EQ_I2FLT_ST_MASK 0xFF000000
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#define SW_EQ_FLT2I_ST_OFFSET 16
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#define SW_EQ_FLT2I_ST_MASK 0x00FF0000
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#define SW_EQ_FLT_ST_CLR_OFFSET 5
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#define SW_EQ_FLT_ST_CLR_MASK 0x00000020
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#define SW_EQ_IGNORE_FLT2I_ST_OFFSET 4
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#define SW_EQ_IGNORE_FLT2I_ST_MASK 0x00000010
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#define SW_EQ_FLT_RND_SEL_OFFSET 0
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#define SW_EQ_FLT_RND_SEL_MASK 0x00000007
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//-----------------------------------
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#define CFG_EQ_FLT_EXP_SET_ADDR 0x0020
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#define SW_EQ_FLTOUT_EXP_BIAS_OFFSET 18
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#define SW_EQ_FLTOUT_EXP_BIAS_MASK 0x03FC0000
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#define SW_EQ_EXP_BIAS_OVR_EN_OFFSET 17
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#define SW_EQ_EXP_BIAS_OVR_EN_MASK 0x00020000
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#define EQ_FLT_EXP_BIAS_OFFSET 8
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#define EQ_FLT_EXP_BIAS_MASK 0x0001FF00
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#define SW_EQ_EXP_THRE_OFFSET 0
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#define SW_EQ_EXP_THRE_MASK 0x000000FF
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//-----------------------------------
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#define CFG_EQ_FLT2I_REG0_ADDR 0x0024
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#define SW_EQ_FLT2I_REG0_OFFSET 0
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#define SW_EQ_FLT2I_REG0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_FLT2I_REG1_ADDR 0x0028
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#define SW_EQ_FLT2I_REG1_OFFSET 0
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#define SW_EQ_FLT2I_REG1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_FLT2I_REG2_ADDR 0x002C
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#define SW_EQ_FLT2I_REG2_OFFSET 0
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#define SW_EQ_FLT2I_REG2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_FLT2I_REG3_ADDR 0x0030
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#define SW_EQ_FLT2I_REG3_OFFSET 0
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#define SW_EQ_FLT2I_REG3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_INT_RAW_ADDR 0x0034
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#define EQ_COEF_DONE_INT_RAW_OFFSET 4
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#define EQ_COEF_DONE_INT_RAW_MASK 0x00000010
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#define EQ_DONE_INT_RAW_OFFSET 0
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#define EQ_DONE_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_INT_ST_ADDR 0x0038
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#define EQ_COEF_DONE_INT_ST_OFFSET 4
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#define EQ_COEF_DONE_INT_ST_MASK 0x00000010
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#define EQ_DONE_INT_ST_OFFSET 0
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#define EQ_DONE_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_INT_ENA_ADDR 0x003C
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#define EQ_COEF_DONE_INT_ENA_OFFSET 4
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#define EQ_COEF_DONE_INT_ENA_MASK 0x00000010
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#define EQ_DONE_INT_ENA_OFFSET 0
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#define EQ_DONE_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_INT_CLR_ADDR 0x0040
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#define EQ_COEF_DONE_INT_CLR_OFFSET 4
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#define EQ_COEF_DONE_INT_CLR_MASK 0x00000010
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#define EQ_DONE_INT_CLR_OFFSET 0
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#define EQ_DONE_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_COEF_RW_ADDR 0x0044
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#define SW_EQ_COEF_RW_OFFSET 0
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#define SW_EQ_COEF_RW_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_COEF_RD_ADDR_ADDR 0x0048
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#define SW_EQ_COEF_RD_ADDR_OFFSET 0
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#define SW_EQ_COEF_RD_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_COEF_WR_ADDR_ADDR 0x004C
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#define SW_EQ_COEF_WR_ADDR_OFFSET 0
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#define SW_EQ_COEF_WR_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_DATA_CLIP_RATE_ADDR 0x0050
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#define SW_EQ_OUT_CLIP_RATE_OFFSET 0
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#define SW_EQ_OUT_CLIP_RATE_MASK 0x0000000F
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//-----------------------------------
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#define CFG_EQ_OUT_CLIP_THRE_ADDR 0x0054
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#define SW_EQ_OUT_CLIP_THRES_OFFSET 0
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#define SW_EQ_OUT_CLIP_THRES_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_COEF_SWITCH_ADDR 0x0060
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#define SW_EQ_SWITCH_DONE_OFFSET 17
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#define SW_EQ_SWITCH_DONE_MASK 0x00020000
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#define RO_EQ_SWITCH_STATUS_OFFSET 16
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#define RO_EQ_SWITCH_STATUS_MASK 0x00010000
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#define SW_EQ_DST_NUM_OFFSET 10
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#define SW_EQ_DST_NUM_MASK 0x0000FC00
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#define SW_EQ_DST_START_BAND_OFFSET 4
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#define SW_EQ_DST_START_BAND_MASK 0x000003F0
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#define SW_EQ_DST_COEF_LOAD_EN_OFFSET 2
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#define SW_EQ_DST_COEF_LOAD_EN_MASK 0x00000004
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#define SW_EQ_SRC_COEF_OUT_EN_OFFSET 1
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#define SW_EQ_SRC_COEF_OUT_EN_MASK 0x00000002
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#define SW_EQ_COEF_SWITCH_EN_OFFSET 0
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#define SW_EQ_COEF_SWITCH_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_EQ_COEF_SWITCH_CFG_ADDR 0x0064
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#define SW_EQ_SWITCH_LEN_SEL_OFFSET 16
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#define SW_EQ_SWITCH_LEN_SEL_MASK 0x000F0000
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#define SW_EQ_SWITCH_DELAY_OFFSET 0
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#define SW_EQ_SWITCH_DELAY_MASK 0x00003FFF
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//-----------------------------------
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#define CFG_RO_EQ_COEF_SWITCH_ST_ADDR 0x0068
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#define RO_EQ_SWITCH_LEN_OFFSET 14
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#define RO_EQ_SWITCH_LEN_MASK 0xFFFFC000
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#define RO_EQ_SWITCH_DELAY_OFFSET 0
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#define RO_EQ_SWITCH_DELAY_MASK 0x00003FFF
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//-----------------------------------
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#define CFG_EQ_DST_COEF_RD_ADDR_ADDR 0x006C
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#define SW_EQ_DST_COEF_RD_ADDR_OFFSET 0
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#define SW_EQ_DST_COEF_RD_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EQ_DST_COEF_WR_ADDR_ADDR 0x0070
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#define SW_EQ_DST_COEF_WR_ADDR_OFFSET 0
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#define SW_EQ_DST_COEF_WR_ADDR_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define EQ_READ_REG(addr) SOC_READ_REG(EQ_REG_BASEADDR + addr)
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#define EQ_WRITE_REG(addr,value) SOC_WRITE_REG(EQ_REG_BASEADDR + addr,value)
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