3326 lines
106 KiB
C
3326 lines
106 KiB
C
|
|
//-----------------------------------
|
|
#define CFG_GPIO_INT0_ENA0_ADDR 0x0
|
|
#define GPIO_INT0_ENA0_OFFSET 0
|
|
#define GPIO_INT0_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO_INT1_ENA0_ADDR 0x4
|
|
#define GPIO_INT1_ENA0_OFFSET 0
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|
#define GPIO_INT1_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO_INT2_ENA0_ADDR 0x8
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|
#define GPIO_INT2_ENA0_OFFSET 0
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|
#define GPIO_INT2_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO_STS0_ENA0_ADDR 0xc
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#define GPIO_STS0_ENA0_OFFSET 0
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#define GPIO_STS0_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO_STS1_ENA0_ADDR 0x10
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#define GPIO_STS1_ENA0_OFFSET 0
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#define GPIO_STS1_ENA0_MASK 0xFFFFFFFF
|
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|
|
//-----------------------------------
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#define CFG_GPIO_STS2_ENA0_ADDR 0x14
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#define GPIO_STS2_ENA0_OFFSET 0
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#define GPIO_STS2_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
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#define CFG_GPIO_INT0_ENA1_ADDR 0x20
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#define GPIO_INT0_ENA1_OFFSET 0
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#define GPIO_INT0_ENA1_MASK 0xFFFFFFFF
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|
|
|
//-----------------------------------
|
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#define CFG_GPIO_INT1_ENA1_ADDR 0x24
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#define GPIO_INT1_ENA1_OFFSET 0
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#define GPIO_INT1_ENA1_MASK 0xFFFFFFFF
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|
|
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//-----------------------------------
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#define CFG_GPIO_INT2_ENA1_ADDR 0x28
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#define GPIO_INT2_ENA1_OFFSET 0
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#define GPIO_INT2_ENA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
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#define CFG_GPIO_STS0_ENA1_ADDR 0x2c
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#define GPIO_STS0_ENA1_OFFSET 0
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#define GPIO_STS0_ENA1_MASK 0xFFFFFFFF
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|
|
//-----------------------------------
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#define CFG_GPIO_STS1_ENA1_ADDR 0x30
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#define GPIO_STS1_ENA1_OFFSET 0
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#define GPIO_STS1_ENA1_MASK 0xFFFFFFFF
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|
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//-----------------------------------
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#define CFG_GPIO_STS2_ENA1_ADDR 0x34
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#define GPIO_STS2_ENA1_OFFSET 0
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#define GPIO_STS2_ENA1_MASK 0xFFFFFFFF
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|
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//-----------------------------------
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#define CFG_GPIO_INT0_ENA2_ADDR 0x40
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#define GPIO_INT0_ENA2_OFFSET 0
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#define GPIO_INT0_ENA2_MASK 0xFFFFFFFF
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|
|
|
//-----------------------------------
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#define CFG_GPIO_INT1_ENA2_ADDR 0x44
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#define GPIO_INT1_ENA2_OFFSET 0
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#define GPIO_INT1_ENA2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT2_ENA2_ADDR 0x48
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#define GPIO_INT2_ENA2_OFFSET 0
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#define GPIO_INT2_ENA2_MASK 0xFFFFFFFF
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|
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//-----------------------------------
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#define CFG_GPIO_STS0_ENA2_ADDR 0x4c
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#define GPIO_STS0_ENA2_OFFSET 0
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#define GPIO_STS0_ENA2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_STS1_ENA2_ADDR 0x50
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#define GPIO_STS1_ENA2_OFFSET 0
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#define GPIO_STS1_ENA2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_STS2_ENA2_ADDR 0x54
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#define GPIO_STS2_ENA2_OFFSET 0
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#define GPIO_STS2_ENA2_MASK 0xFFFFFFFF
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|
|
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//-----------------------------------
|
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#define CFG_GPIO_INT0_ENA3_ADDR 0x60
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#define GPIO_INT0_ENA3_OFFSET 0
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#define GPIO_INT0_ENA3_MASK 0xFFFFFFFF
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|
|
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//-----------------------------------
|
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#define CFG_GPIO_INT1_ENA3_ADDR 0x64
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#define GPIO_INT1_ENA3_OFFSET 0
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#define GPIO_INT1_ENA3_MASK 0xFFFFFFFF
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|
|
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//-----------------------------------
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#define CFG_GPIO_INT2_ENA3_ADDR 0x68
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#define GPIO_INT2_ENA3_OFFSET 0
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#define GPIO_INT2_ENA3_MASK 0xFFFFFFFF
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|
|
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//-----------------------------------
|
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#define CFG_GPIO_STS0_ENA3_ADDR 0x6c
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#define GPIO_STS0_ENA3_OFFSET 0
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#define GPIO_STS0_ENA3_MASK 0xFFFFFFFF
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|
|
|
//-----------------------------------
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#define CFG_GPIO_STS1_ENA3_ADDR 0x70
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#define GPIO_STS1_ENA3_OFFSET 0
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#define GPIO_STS1_ENA3_MASK 0xFFFFFFFF
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|
|
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//-----------------------------------
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#define CFG_GPIO_STS2_ENA3_ADDR 0x74
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#define GPIO_STS2_ENA3_OFFSET 0
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#define GPIO_STS2_ENA3_MASK 0xFFFFFFFF
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|
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//-----------------------------------
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#define CFG_GPIO0_CFG_ADDR 0x200
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#define GPIO0_OD_MODE_OFFSET 12
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#define GPIO0_OD_MODE_MASK 0x00003000
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#define GPIO0_OUT_OFFSET 11
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#define GPIO0_OUT_MASK 0x00000800
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#define GPIO0_OE_OFFSET 10
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|
#define GPIO0_OE_MASK 0x00000400
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|
#define GPIO0_IE_OFFSET 9
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#define GPIO0_IE_MASK 0x00000200
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#define GPIO0_IN_OFFSET 8
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#define GPIO0_IN_MASK 0x00000100
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#define GPIO0_WAKEUP_ENA_OFFSET 7
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#define GPIO0_WAKEUP_ENA_MASK 0x00000080
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#define GPIO0_INT_TYPE_OFFSET 4
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#define GPIO0_INT_TYPE_MASK 0x00000070
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#define GPIO0_INT_RAW_OFFSET 3
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#define GPIO0_INT_RAW_MASK 0x00000008
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#define GPIO0_INT_STS_OFFSET 2
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|
#define GPIO0_INT_STS_MASK 0x00000004
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#define GPIO0_INT_ENA_OFFSET 1
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#define GPIO0_INT_ENA_MASK 0x00000002
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#define GPIO0_CLR_OFFSET 0
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#define GPIO0_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO1_CFG_ADDR 0x204
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#define GPIO1_OD_MODE_OFFSET 12
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#define GPIO1_OD_MODE_MASK 0x00003000
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#define GPIO1_OUT_OFFSET 11
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|
#define GPIO1_OUT_MASK 0x00000800
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#define GPIO1_OE_OFFSET 10
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#define GPIO1_OE_MASK 0x00000400
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|
#define GPIO1_IE_OFFSET 9
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#define GPIO1_IE_MASK 0x00000200
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|
#define GPIO1_IN_OFFSET 8
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|
#define GPIO1_IN_MASK 0x00000100
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#define GPIO1_WAKEUP_ENA_OFFSET 7
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#define GPIO1_WAKEUP_ENA_MASK 0x00000080
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#define GPIO1_INT_TYPE_OFFSET 4
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#define GPIO1_INT_TYPE_MASK 0x00000070
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#define GPIO1_INT_RAW_OFFSET 3
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#define GPIO1_INT_RAW_MASK 0x00000008
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|
#define GPIO1_INT_STS_OFFSET 2
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|
#define GPIO1_INT_STS_MASK 0x00000004
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|
#define GPIO1_INT_ENA_OFFSET 1
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|
#define GPIO1_INT_ENA_MASK 0x00000002
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|
#define GPIO1_CLR_OFFSET 0
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|
#define GPIO1_CLR_MASK 0x00000001
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|
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|
//-----------------------------------
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#define CFG_GPIO2_CFG_ADDR 0x208
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|
#define GPIO2_OD_MODE_OFFSET 12
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|
#define GPIO2_OD_MODE_MASK 0x00003000
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|
#define GPIO2_OUT_OFFSET 11
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|
#define GPIO2_OUT_MASK 0x00000800
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#define GPIO2_OE_OFFSET 10
|
|
#define GPIO2_OE_MASK 0x00000400
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|
#define GPIO2_IE_OFFSET 9
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|
#define GPIO2_IE_MASK 0x00000200
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|
#define GPIO2_IN_OFFSET 8
|
|
#define GPIO2_IN_MASK 0x00000100
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|
#define GPIO2_WAKEUP_ENA_OFFSET 7
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|
#define GPIO2_WAKEUP_ENA_MASK 0x00000080
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|
#define GPIO2_INT_TYPE_OFFSET 4
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|
#define GPIO2_INT_TYPE_MASK 0x00000070
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|
#define GPIO2_INT_RAW_OFFSET 3
|
|
#define GPIO2_INT_RAW_MASK 0x00000008
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|
#define GPIO2_INT_STS_OFFSET 2
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|
#define GPIO2_INT_STS_MASK 0x00000004
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|
#define GPIO2_INT_ENA_OFFSET 1
|
|
#define GPIO2_INT_ENA_MASK 0x00000002
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|
#define GPIO2_CLR_OFFSET 0
|
|
#define GPIO2_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO3_CFG_ADDR 0x20c
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|
#define GPIO3_OD_MODE_OFFSET 12
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|
#define GPIO3_OD_MODE_MASK 0x00003000
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|
#define GPIO3_OUT_OFFSET 11
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|
#define GPIO3_OUT_MASK 0x00000800
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|
#define GPIO3_OE_OFFSET 10
|
|
#define GPIO3_OE_MASK 0x00000400
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|
#define GPIO3_IE_OFFSET 9
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|
#define GPIO3_IE_MASK 0x00000200
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|
#define GPIO3_IN_OFFSET 8
|
|
#define GPIO3_IN_MASK 0x00000100
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|
#define GPIO3_WAKEUP_ENA_OFFSET 7
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|
#define GPIO3_WAKEUP_ENA_MASK 0x00000080
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|
#define GPIO3_INT_TYPE_OFFSET 4
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|
#define GPIO3_INT_TYPE_MASK 0x00000070
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|
#define GPIO3_INT_RAW_OFFSET 3
|
|
#define GPIO3_INT_RAW_MASK 0x00000008
|
|
#define GPIO3_INT_STS_OFFSET 2
|
|
#define GPIO3_INT_STS_MASK 0x00000004
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|
#define GPIO3_INT_ENA_OFFSET 1
|
|
#define GPIO3_INT_ENA_MASK 0x00000002
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|
#define GPIO3_CLR_OFFSET 0
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|
#define GPIO3_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO4_CFG_ADDR 0x210
|
|
#define GPIO4_OD_MODE_OFFSET 12
|
|
#define GPIO4_OD_MODE_MASK 0x00003000
|
|
#define GPIO4_OUT_OFFSET 11
|
|
#define GPIO4_OUT_MASK 0x00000800
|
|
#define GPIO4_OE_OFFSET 10
|
|
#define GPIO4_OE_MASK 0x00000400
|
|
#define GPIO4_IE_OFFSET 9
|
|
#define GPIO4_IE_MASK 0x00000200
|
|
#define GPIO4_IN_OFFSET 8
|
|
#define GPIO4_IN_MASK 0x00000100
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|
#define GPIO4_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO4_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO4_INT_TYPE_OFFSET 4
|
|
#define GPIO4_INT_TYPE_MASK 0x00000070
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|
#define GPIO4_INT_RAW_OFFSET 3
|
|
#define GPIO4_INT_RAW_MASK 0x00000008
|
|
#define GPIO4_INT_STS_OFFSET 2
|
|
#define GPIO4_INT_STS_MASK 0x00000004
|
|
#define GPIO4_INT_ENA_OFFSET 1
|
|
#define GPIO4_INT_ENA_MASK 0x00000002
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|
#define GPIO4_CLR_OFFSET 0
|
|
#define GPIO4_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO5_CFG_ADDR 0x214
|
|
#define GPIO5_OD_MODE_OFFSET 12
|
|
#define GPIO5_OD_MODE_MASK 0x00003000
|
|
#define GPIO5_OUT_OFFSET 11
|
|
#define GPIO5_OUT_MASK 0x00000800
|
|
#define GPIO5_OE_OFFSET 10
|
|
#define GPIO5_OE_MASK 0x00000400
|
|
#define GPIO5_IE_OFFSET 9
|
|
#define GPIO5_IE_MASK 0x00000200
|
|
#define GPIO5_IN_OFFSET 8
|
|
#define GPIO5_IN_MASK 0x00000100
|
|
#define GPIO5_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO5_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO5_INT_TYPE_OFFSET 4
|
|
#define GPIO5_INT_TYPE_MASK 0x00000070
|
|
#define GPIO5_INT_RAW_OFFSET 3
|
|
#define GPIO5_INT_RAW_MASK 0x00000008
|
|
#define GPIO5_INT_STS_OFFSET 2
|
|
#define GPIO5_INT_STS_MASK 0x00000004
|
|
#define GPIO5_INT_ENA_OFFSET 1
|
|
#define GPIO5_INT_ENA_MASK 0x00000002
|
|
#define GPIO5_CLR_OFFSET 0
|
|
#define GPIO5_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO6_CFG_ADDR 0x218
|
|
#define GPIO6_OD_MODE_OFFSET 12
|
|
#define GPIO6_OD_MODE_MASK 0x00003000
|
|
#define GPIO6_OUT_OFFSET 11
|
|
#define GPIO6_OUT_MASK 0x00000800
|
|
#define GPIO6_OE_OFFSET 10
|
|
#define GPIO6_OE_MASK 0x00000400
|
|
#define GPIO6_IE_OFFSET 9
|
|
#define GPIO6_IE_MASK 0x00000200
|
|
#define GPIO6_IN_OFFSET 8
|
|
#define GPIO6_IN_MASK 0x00000100
|
|
#define GPIO6_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO6_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO6_INT_TYPE_OFFSET 4
|
|
#define GPIO6_INT_TYPE_MASK 0x00000070
|
|
#define GPIO6_INT_RAW_OFFSET 3
|
|
#define GPIO6_INT_RAW_MASK 0x00000008
|
|
#define GPIO6_INT_STS_OFFSET 2
|
|
#define GPIO6_INT_STS_MASK 0x00000004
|
|
#define GPIO6_INT_ENA_OFFSET 1
|
|
#define GPIO6_INT_ENA_MASK 0x00000002
|
|
#define GPIO6_CLR_OFFSET 0
|
|
#define GPIO6_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO7_CFG_ADDR 0x21c
|
|
#define GPIO7_OD_MODE_OFFSET 12
|
|
#define GPIO7_OD_MODE_MASK 0x00003000
|
|
#define GPIO7_OUT_OFFSET 11
|
|
#define GPIO7_OUT_MASK 0x00000800
|
|
#define GPIO7_OE_OFFSET 10
|
|
#define GPIO7_OE_MASK 0x00000400
|
|
#define GPIO7_IE_OFFSET 9
|
|
#define GPIO7_IE_MASK 0x00000200
|
|
#define GPIO7_IN_OFFSET 8
|
|
#define GPIO7_IN_MASK 0x00000100
|
|
#define GPIO7_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO7_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO7_INT_TYPE_OFFSET 4
|
|
#define GPIO7_INT_TYPE_MASK 0x00000070
|
|
#define GPIO7_INT_RAW_OFFSET 3
|
|
#define GPIO7_INT_RAW_MASK 0x00000008
|
|
#define GPIO7_INT_STS_OFFSET 2
|
|
#define GPIO7_INT_STS_MASK 0x00000004
|
|
#define GPIO7_INT_ENA_OFFSET 1
|
|
#define GPIO7_INT_ENA_MASK 0x00000002
|
|
#define GPIO7_CLR_OFFSET 0
|
|
#define GPIO7_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO8_CFG_ADDR 0x220
|
|
#define GPIO8_OD_MODE_OFFSET 12
|
|
#define GPIO8_OD_MODE_MASK 0x00003000
|
|
#define GPIO8_OUT_OFFSET 11
|
|
#define GPIO8_OUT_MASK 0x00000800
|
|
#define GPIO8_OE_OFFSET 10
|
|
#define GPIO8_OE_MASK 0x00000400
|
|
#define GPIO8_IE_OFFSET 9
|
|
#define GPIO8_IE_MASK 0x00000200
|
|
#define GPIO8_IN_OFFSET 8
|
|
#define GPIO8_IN_MASK 0x00000100
|
|
#define GPIO8_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO8_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO8_INT_TYPE_OFFSET 4
|
|
#define GPIO8_INT_TYPE_MASK 0x00000070
|
|
#define GPIO8_INT_RAW_OFFSET 3
|
|
#define GPIO8_INT_RAW_MASK 0x00000008
|
|
#define GPIO8_INT_STS_OFFSET 2
|
|
#define GPIO8_INT_STS_MASK 0x00000004
|
|
#define GPIO8_INT_ENA_OFFSET 1
|
|
#define GPIO8_INT_ENA_MASK 0x00000002
|
|
#define GPIO8_CLR_OFFSET 0
|
|
#define GPIO8_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO9_CFG_ADDR 0x224
|
|
#define GPIO9_OD_MODE_OFFSET 12
|
|
#define GPIO9_OD_MODE_MASK 0x00003000
|
|
#define GPIO9_OUT_OFFSET 11
|
|
#define GPIO9_OUT_MASK 0x00000800
|
|
#define GPIO9_OE_OFFSET 10
|
|
#define GPIO9_OE_MASK 0x00000400
|
|
#define GPIO9_IE_OFFSET 9
|
|
#define GPIO9_IE_MASK 0x00000200
|
|
#define GPIO9_IN_OFFSET 8
|
|
#define GPIO9_IN_MASK 0x00000100
|
|
#define GPIO9_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO9_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO9_INT_TYPE_OFFSET 4
|
|
#define GPIO9_INT_TYPE_MASK 0x00000070
|
|
#define GPIO9_INT_RAW_OFFSET 3
|
|
#define GPIO9_INT_RAW_MASK 0x00000008
|
|
#define GPIO9_INT_STS_OFFSET 2
|
|
#define GPIO9_INT_STS_MASK 0x00000004
|
|
#define GPIO9_INT_ENA_OFFSET 1
|
|
#define GPIO9_INT_ENA_MASK 0x00000002
|
|
#define GPIO9_CLR_OFFSET 0
|
|
#define GPIO9_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO10_CFG_ADDR 0x228
|
|
#define GPIO10_OD_MODE_OFFSET 12
|
|
#define GPIO10_OD_MODE_MASK 0x00003000
|
|
#define GPIO10_OUT_OFFSET 11
|
|
#define GPIO10_OUT_MASK 0x00000800
|
|
#define GPIO10_OE_OFFSET 10
|
|
#define GPIO10_OE_MASK 0x00000400
|
|
#define GPIO10_IE_OFFSET 9
|
|
#define GPIO10_IE_MASK 0x00000200
|
|
#define GPIO10_IN_OFFSET 8
|
|
#define GPIO10_IN_MASK 0x00000100
|
|
#define GPIO10_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO10_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO10_INT_TYPE_OFFSET 4
|
|
#define GPIO10_INT_TYPE_MASK 0x00000070
|
|
#define GPIO10_INT_RAW_OFFSET 3
|
|
#define GPIO10_INT_RAW_MASK 0x00000008
|
|
#define GPIO10_INT_STS_OFFSET 2
|
|
#define GPIO10_INT_STS_MASK 0x00000004
|
|
#define GPIO10_INT_ENA_OFFSET 1
|
|
#define GPIO10_INT_ENA_MASK 0x00000002
|
|
#define GPIO10_CLR_OFFSET 0
|
|
#define GPIO10_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO11_CFG_ADDR 0x22c
|
|
#define GPIO11_OD_MODE_OFFSET 12
|
|
#define GPIO11_OD_MODE_MASK 0x00003000
|
|
#define GPIO11_OUT_OFFSET 11
|
|
#define GPIO11_OUT_MASK 0x00000800
|
|
#define GPIO11_OE_OFFSET 10
|
|
#define GPIO11_OE_MASK 0x00000400
|
|
#define GPIO11_IE_OFFSET 9
|
|
#define GPIO11_IE_MASK 0x00000200
|
|
#define GPIO11_IN_OFFSET 8
|
|
#define GPIO11_IN_MASK 0x00000100
|
|
#define GPIO11_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO11_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO11_INT_TYPE_OFFSET 4
|
|
#define GPIO11_INT_TYPE_MASK 0x00000070
|
|
#define GPIO11_INT_RAW_OFFSET 3
|
|
#define GPIO11_INT_RAW_MASK 0x00000008
|
|
#define GPIO11_INT_STS_OFFSET 2
|
|
#define GPIO11_INT_STS_MASK 0x00000004
|
|
#define GPIO11_INT_ENA_OFFSET 1
|
|
#define GPIO11_INT_ENA_MASK 0x00000002
|
|
#define GPIO11_CLR_OFFSET 0
|
|
#define GPIO11_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO12_CFG_ADDR 0x230
|
|
#define GPIO12_OD_MODE_OFFSET 12
|
|
#define GPIO12_OD_MODE_MASK 0x00003000
|
|
#define GPIO12_OUT_OFFSET 11
|
|
#define GPIO12_OUT_MASK 0x00000800
|
|
#define GPIO12_OE_OFFSET 10
|
|
#define GPIO12_OE_MASK 0x00000400
|
|
#define GPIO12_IE_OFFSET 9
|
|
#define GPIO12_IE_MASK 0x00000200
|
|
#define GPIO12_IN_OFFSET 8
|
|
#define GPIO12_IN_MASK 0x00000100
|
|
#define GPIO12_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO12_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO12_INT_TYPE_OFFSET 4
|
|
#define GPIO12_INT_TYPE_MASK 0x00000070
|
|
#define GPIO12_INT_RAW_OFFSET 3
|
|
#define GPIO12_INT_RAW_MASK 0x00000008
|
|
#define GPIO12_INT_STS_OFFSET 2
|
|
#define GPIO12_INT_STS_MASK 0x00000004
|
|
#define GPIO12_INT_ENA_OFFSET 1
|
|
#define GPIO12_INT_ENA_MASK 0x00000002
|
|
#define GPIO12_CLR_OFFSET 0
|
|
#define GPIO12_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO13_CFG_ADDR 0x234
|
|
#define GPIO13_OD_MODE_OFFSET 12
|
|
#define GPIO13_OD_MODE_MASK 0x00003000
|
|
#define GPIO13_OUT_OFFSET 11
|
|
#define GPIO13_OUT_MASK 0x00000800
|
|
#define GPIO13_OE_OFFSET 10
|
|
#define GPIO13_OE_MASK 0x00000400
|
|
#define GPIO13_IE_OFFSET 9
|
|
#define GPIO13_IE_MASK 0x00000200
|
|
#define GPIO13_IN_OFFSET 8
|
|
#define GPIO13_IN_MASK 0x00000100
|
|
#define GPIO13_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO13_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO13_INT_TYPE_OFFSET 4
|
|
#define GPIO13_INT_TYPE_MASK 0x00000070
|
|
#define GPIO13_INT_RAW_OFFSET 3
|
|
#define GPIO13_INT_RAW_MASK 0x00000008
|
|
#define GPIO13_INT_STS_OFFSET 2
|
|
#define GPIO13_INT_STS_MASK 0x00000004
|
|
#define GPIO13_INT_ENA_OFFSET 1
|
|
#define GPIO13_INT_ENA_MASK 0x00000002
|
|
#define GPIO13_CLR_OFFSET 0
|
|
#define GPIO13_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO14_CFG_ADDR 0x238
|
|
#define GPIO14_OD_MODE_OFFSET 12
|
|
#define GPIO14_OD_MODE_MASK 0x00003000
|
|
#define GPIO14_OUT_OFFSET 11
|
|
#define GPIO14_OUT_MASK 0x00000800
|
|
#define GPIO14_OE_OFFSET 10
|
|
#define GPIO14_OE_MASK 0x00000400
|
|
#define GPIO14_IE_OFFSET 9
|
|
#define GPIO14_IE_MASK 0x00000200
|
|
#define GPIO14_IN_OFFSET 8
|
|
#define GPIO14_IN_MASK 0x00000100
|
|
#define GPIO14_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO14_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO14_INT_TYPE_OFFSET 4
|
|
#define GPIO14_INT_TYPE_MASK 0x00000070
|
|
#define GPIO14_INT_RAW_OFFSET 3
|
|
#define GPIO14_INT_RAW_MASK 0x00000008
|
|
#define GPIO14_INT_STS_OFFSET 2
|
|
#define GPIO14_INT_STS_MASK 0x00000004
|
|
#define GPIO14_INT_ENA_OFFSET 1
|
|
#define GPIO14_INT_ENA_MASK 0x00000002
|
|
#define GPIO14_CLR_OFFSET 0
|
|
#define GPIO14_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO15_CFG_ADDR 0x23c
|
|
#define GPIO15_OD_MODE_OFFSET 12
|
|
#define GPIO15_OD_MODE_MASK 0x00003000
|
|
#define GPIO15_OUT_OFFSET 11
|
|
#define GPIO15_OUT_MASK 0x00000800
|
|
#define GPIO15_OE_OFFSET 10
|
|
#define GPIO15_OE_MASK 0x00000400
|
|
#define GPIO15_IE_OFFSET 9
|
|
#define GPIO15_IE_MASK 0x00000200
|
|
#define GPIO15_IN_OFFSET 8
|
|
#define GPIO15_IN_MASK 0x00000100
|
|
#define GPIO15_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO15_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO15_INT_TYPE_OFFSET 4
|
|
#define GPIO15_INT_TYPE_MASK 0x00000070
|
|
#define GPIO15_INT_RAW_OFFSET 3
|
|
#define GPIO15_INT_RAW_MASK 0x00000008
|
|
#define GPIO15_INT_STS_OFFSET 2
|
|
#define GPIO15_INT_STS_MASK 0x00000004
|
|
#define GPIO15_INT_ENA_OFFSET 1
|
|
#define GPIO15_INT_ENA_MASK 0x00000002
|
|
#define GPIO15_CLR_OFFSET 0
|
|
#define GPIO15_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO16_CFG_ADDR 0x240
|
|
#define GPIO16_OD_MODE_OFFSET 12
|
|
#define GPIO16_OD_MODE_MASK 0x00003000
|
|
#define GPIO16_OUT_OFFSET 11
|
|
#define GPIO16_OUT_MASK 0x00000800
|
|
#define GPIO16_OE_OFFSET 10
|
|
#define GPIO16_OE_MASK 0x00000400
|
|
#define GPIO16_IE_OFFSET 9
|
|
#define GPIO16_IE_MASK 0x00000200
|
|
#define GPIO16_IN_OFFSET 8
|
|
#define GPIO16_IN_MASK 0x00000100
|
|
#define GPIO16_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO16_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO16_INT_TYPE_OFFSET 4
|
|
#define GPIO16_INT_TYPE_MASK 0x00000070
|
|
#define GPIO16_INT_RAW_OFFSET 3
|
|
#define GPIO16_INT_RAW_MASK 0x00000008
|
|
#define GPIO16_INT_STS_OFFSET 2
|
|
#define GPIO16_INT_STS_MASK 0x00000004
|
|
#define GPIO16_INT_ENA_OFFSET 1
|
|
#define GPIO16_INT_ENA_MASK 0x00000002
|
|
#define GPIO16_CLR_OFFSET 0
|
|
#define GPIO16_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO17_CFG_ADDR 0x244
|
|
#define GPIO17_OD_MODE_OFFSET 12
|
|
#define GPIO17_OD_MODE_MASK 0x00003000
|
|
#define GPIO17_OUT_OFFSET 11
|
|
#define GPIO17_OUT_MASK 0x00000800
|
|
#define GPIO17_OE_OFFSET 10
|
|
#define GPIO17_OE_MASK 0x00000400
|
|
#define GPIO17_IE_OFFSET 9
|
|
#define GPIO17_IE_MASK 0x00000200
|
|
#define GPIO17_IN_OFFSET 8
|
|
#define GPIO17_IN_MASK 0x00000100
|
|
#define GPIO17_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO17_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO17_INT_TYPE_OFFSET 4
|
|
#define GPIO17_INT_TYPE_MASK 0x00000070
|
|
#define GPIO17_INT_RAW_OFFSET 3
|
|
#define GPIO17_INT_RAW_MASK 0x00000008
|
|
#define GPIO17_INT_STS_OFFSET 2
|
|
#define GPIO17_INT_STS_MASK 0x00000004
|
|
#define GPIO17_INT_ENA_OFFSET 1
|
|
#define GPIO17_INT_ENA_MASK 0x00000002
|
|
#define GPIO17_CLR_OFFSET 0
|
|
#define GPIO17_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO18_CFG_ADDR 0x248
|
|
#define GPIO18_OD_MODE_OFFSET 12
|
|
#define GPIO18_OD_MODE_MASK 0x00003000
|
|
#define GPIO18_OUT_OFFSET 11
|
|
#define GPIO18_OUT_MASK 0x00000800
|
|
#define GPIO18_OE_OFFSET 10
|
|
#define GPIO18_OE_MASK 0x00000400
|
|
#define GPIO18_IE_OFFSET 9
|
|
#define GPIO18_IE_MASK 0x00000200
|
|
#define GPIO18_IN_OFFSET 8
|
|
#define GPIO18_IN_MASK 0x00000100
|
|
#define GPIO18_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO18_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO18_INT_TYPE_OFFSET 4
|
|
#define GPIO18_INT_TYPE_MASK 0x00000070
|
|
#define GPIO18_INT_RAW_OFFSET 3
|
|
#define GPIO18_INT_RAW_MASK 0x00000008
|
|
#define GPIO18_INT_STS_OFFSET 2
|
|
#define GPIO18_INT_STS_MASK 0x00000004
|
|
#define GPIO18_INT_ENA_OFFSET 1
|
|
#define GPIO18_INT_ENA_MASK 0x00000002
|
|
#define GPIO18_CLR_OFFSET 0
|
|
#define GPIO18_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO19_CFG_ADDR 0x24c
|
|
#define GPIO19_OD_MODE_OFFSET 12
|
|
#define GPIO19_OD_MODE_MASK 0x00003000
|
|
#define GPIO19_OUT_OFFSET 11
|
|
#define GPIO19_OUT_MASK 0x00000800
|
|
#define GPIO19_OE_OFFSET 10
|
|
#define GPIO19_OE_MASK 0x00000400
|
|
#define GPIO19_IE_OFFSET 9
|
|
#define GPIO19_IE_MASK 0x00000200
|
|
#define GPIO19_IN_OFFSET 8
|
|
#define GPIO19_IN_MASK 0x00000100
|
|
#define GPIO19_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO19_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO19_INT_TYPE_OFFSET 4
|
|
#define GPIO19_INT_TYPE_MASK 0x00000070
|
|
#define GPIO19_INT_RAW_OFFSET 3
|
|
#define GPIO19_INT_RAW_MASK 0x00000008
|
|
#define GPIO19_INT_STS_OFFSET 2
|
|
#define GPIO19_INT_STS_MASK 0x00000004
|
|
#define GPIO19_INT_ENA_OFFSET 1
|
|
#define GPIO19_INT_ENA_MASK 0x00000002
|
|
#define GPIO19_CLR_OFFSET 0
|
|
#define GPIO19_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO20_CFG_ADDR 0x250
|
|
#define GPIO20_OD_MODE_OFFSET 12
|
|
#define GPIO20_OD_MODE_MASK 0x00003000
|
|
#define GPIO20_OUT_OFFSET 11
|
|
#define GPIO20_OUT_MASK 0x00000800
|
|
#define GPIO20_OE_OFFSET 10
|
|
#define GPIO20_OE_MASK 0x00000400
|
|
#define GPIO20_IE_OFFSET 9
|
|
#define GPIO20_IE_MASK 0x00000200
|
|
#define GPIO20_IN_OFFSET 8
|
|
#define GPIO20_IN_MASK 0x00000100
|
|
#define GPIO20_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO20_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO20_INT_TYPE_OFFSET 4
|
|
#define GPIO20_INT_TYPE_MASK 0x00000070
|
|
#define GPIO20_INT_RAW_OFFSET 3
|
|
#define GPIO20_INT_RAW_MASK 0x00000008
|
|
#define GPIO20_INT_STS_OFFSET 2
|
|
#define GPIO20_INT_STS_MASK 0x00000004
|
|
#define GPIO20_INT_ENA_OFFSET 1
|
|
#define GPIO20_INT_ENA_MASK 0x00000002
|
|
#define GPIO20_CLR_OFFSET 0
|
|
#define GPIO20_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO21_CFG_ADDR 0x254
|
|
#define GPIO21_OD_MODE_OFFSET 12
|
|
#define GPIO21_OD_MODE_MASK 0x00003000
|
|
#define GPIO21_OUT_OFFSET 11
|
|
#define GPIO21_OUT_MASK 0x00000800
|
|
#define GPIO21_OE_OFFSET 10
|
|
#define GPIO21_OE_MASK 0x00000400
|
|
#define GPIO21_IE_OFFSET 9
|
|
#define GPIO21_IE_MASK 0x00000200
|
|
#define GPIO21_IN_OFFSET 8
|
|
#define GPIO21_IN_MASK 0x00000100
|
|
#define GPIO21_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO21_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO21_INT_TYPE_OFFSET 4
|
|
#define GPIO21_INT_TYPE_MASK 0x00000070
|
|
#define GPIO21_INT_RAW_OFFSET 3
|
|
#define GPIO21_INT_RAW_MASK 0x00000008
|
|
#define GPIO21_INT_STS_OFFSET 2
|
|
#define GPIO21_INT_STS_MASK 0x00000004
|
|
#define GPIO21_INT_ENA_OFFSET 1
|
|
#define GPIO21_INT_ENA_MASK 0x00000002
|
|
#define GPIO21_CLR_OFFSET 0
|
|
#define GPIO21_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO22_CFG_ADDR 0x258
|
|
#define GPIO22_OD_MODE_OFFSET 12
|
|
#define GPIO22_OD_MODE_MASK 0x00003000
|
|
#define GPIO22_OUT_OFFSET 11
|
|
#define GPIO22_OUT_MASK 0x00000800
|
|
#define GPIO22_OE_OFFSET 10
|
|
#define GPIO22_OE_MASK 0x00000400
|
|
#define GPIO22_IE_OFFSET 9
|
|
#define GPIO22_IE_MASK 0x00000200
|
|
#define GPIO22_IN_OFFSET 8
|
|
#define GPIO22_IN_MASK 0x00000100
|
|
#define GPIO22_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO22_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO22_INT_TYPE_OFFSET 4
|
|
#define GPIO22_INT_TYPE_MASK 0x00000070
|
|
#define GPIO22_INT_RAW_OFFSET 3
|
|
#define GPIO22_INT_RAW_MASK 0x00000008
|
|
#define GPIO22_INT_STS_OFFSET 2
|
|
#define GPIO22_INT_STS_MASK 0x00000004
|
|
#define GPIO22_INT_ENA_OFFSET 1
|
|
#define GPIO22_INT_ENA_MASK 0x00000002
|
|
#define GPIO22_CLR_OFFSET 0
|
|
#define GPIO22_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO23_CFG_ADDR 0x25c
|
|
#define GPIO23_OD_MODE_OFFSET 12
|
|
#define GPIO23_OD_MODE_MASK 0x00003000
|
|
#define GPIO23_OUT_OFFSET 11
|
|
#define GPIO23_OUT_MASK 0x00000800
|
|
#define GPIO23_OE_OFFSET 10
|
|
#define GPIO23_OE_MASK 0x00000400
|
|
#define GPIO23_IE_OFFSET 9
|
|
#define GPIO23_IE_MASK 0x00000200
|
|
#define GPIO23_IN_OFFSET 8
|
|
#define GPIO23_IN_MASK 0x00000100
|
|
#define GPIO23_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO23_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO23_INT_TYPE_OFFSET 4
|
|
#define GPIO23_INT_TYPE_MASK 0x00000070
|
|
#define GPIO23_INT_RAW_OFFSET 3
|
|
#define GPIO23_INT_RAW_MASK 0x00000008
|
|
#define GPIO23_INT_STS_OFFSET 2
|
|
#define GPIO23_INT_STS_MASK 0x00000004
|
|
#define GPIO23_INT_ENA_OFFSET 1
|
|
#define GPIO23_INT_ENA_MASK 0x00000002
|
|
#define GPIO23_CLR_OFFSET 0
|
|
#define GPIO23_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO24_CFG_ADDR 0x260
|
|
#define GPIO24_OD_MODE_OFFSET 12
|
|
#define GPIO24_OD_MODE_MASK 0x00003000
|
|
#define GPIO24_OUT_OFFSET 11
|
|
#define GPIO24_OUT_MASK 0x00000800
|
|
#define GPIO24_OE_OFFSET 10
|
|
#define GPIO24_OE_MASK 0x00000400
|
|
#define GPIO24_IE_OFFSET 9
|
|
#define GPIO24_IE_MASK 0x00000200
|
|
#define GPIO24_IN_OFFSET 8
|
|
#define GPIO24_IN_MASK 0x00000100
|
|
#define GPIO24_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO24_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO24_INT_TYPE_OFFSET 4
|
|
#define GPIO24_INT_TYPE_MASK 0x00000070
|
|
#define GPIO24_INT_RAW_OFFSET 3
|
|
#define GPIO24_INT_RAW_MASK 0x00000008
|
|
#define GPIO24_INT_STS_OFFSET 2
|
|
#define GPIO24_INT_STS_MASK 0x00000004
|
|
#define GPIO24_INT_ENA_OFFSET 1
|
|
#define GPIO24_INT_ENA_MASK 0x00000002
|
|
#define GPIO24_CLR_OFFSET 0
|
|
#define GPIO24_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO25_CFG_ADDR 0x264
|
|
#define GPIO25_OD_MODE_OFFSET 12
|
|
#define GPIO25_OD_MODE_MASK 0x00003000
|
|
#define GPIO25_OUT_OFFSET 11
|
|
#define GPIO25_OUT_MASK 0x00000800
|
|
#define GPIO25_OE_OFFSET 10
|
|
#define GPIO25_OE_MASK 0x00000400
|
|
#define GPIO25_IE_OFFSET 9
|
|
#define GPIO25_IE_MASK 0x00000200
|
|
#define GPIO25_IN_OFFSET 8
|
|
#define GPIO25_IN_MASK 0x00000100
|
|
#define GPIO25_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO25_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO25_INT_TYPE_OFFSET 4
|
|
#define GPIO25_INT_TYPE_MASK 0x00000070
|
|
#define GPIO25_INT_RAW_OFFSET 3
|
|
#define GPIO25_INT_RAW_MASK 0x00000008
|
|
#define GPIO25_INT_STS_OFFSET 2
|
|
#define GPIO25_INT_STS_MASK 0x00000004
|
|
#define GPIO25_INT_ENA_OFFSET 1
|
|
#define GPIO25_INT_ENA_MASK 0x00000002
|
|
#define GPIO25_CLR_OFFSET 0
|
|
#define GPIO25_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO26_CFG_ADDR 0x268
|
|
#define GPIO26_OD_MODE_OFFSET 12
|
|
#define GPIO26_OD_MODE_MASK 0x00003000
|
|
#define GPIO26_OUT_OFFSET 11
|
|
#define GPIO26_OUT_MASK 0x00000800
|
|
#define GPIO26_OE_OFFSET 10
|
|
#define GPIO26_OE_MASK 0x00000400
|
|
#define GPIO26_IE_OFFSET 9
|
|
#define GPIO26_IE_MASK 0x00000200
|
|
#define GPIO26_IN_OFFSET 8
|
|
#define GPIO26_IN_MASK 0x00000100
|
|
#define GPIO26_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO26_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO26_INT_TYPE_OFFSET 4
|
|
#define GPIO26_INT_TYPE_MASK 0x00000070
|
|
#define GPIO26_INT_RAW_OFFSET 3
|
|
#define GPIO26_INT_RAW_MASK 0x00000008
|
|
#define GPIO26_INT_STS_OFFSET 2
|
|
#define GPIO26_INT_STS_MASK 0x00000004
|
|
#define GPIO26_INT_ENA_OFFSET 1
|
|
#define GPIO26_INT_ENA_MASK 0x00000002
|
|
#define GPIO26_CLR_OFFSET 0
|
|
#define GPIO26_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO27_CFG_ADDR 0x26c
|
|
#define GPIO27_OD_MODE_OFFSET 12
|
|
#define GPIO27_OD_MODE_MASK 0x00003000
|
|
#define GPIO27_OUT_OFFSET 11
|
|
#define GPIO27_OUT_MASK 0x00000800
|
|
#define GPIO27_OE_OFFSET 10
|
|
#define GPIO27_OE_MASK 0x00000400
|
|
#define GPIO27_IE_OFFSET 9
|
|
#define GPIO27_IE_MASK 0x00000200
|
|
#define GPIO27_IN_OFFSET 8
|
|
#define GPIO27_IN_MASK 0x00000100
|
|
#define GPIO27_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO27_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO27_INT_TYPE_OFFSET 4
|
|
#define GPIO27_INT_TYPE_MASK 0x00000070
|
|
#define GPIO27_INT_RAW_OFFSET 3
|
|
#define GPIO27_INT_RAW_MASK 0x00000008
|
|
#define GPIO27_INT_STS_OFFSET 2
|
|
#define GPIO27_INT_STS_MASK 0x00000004
|
|
#define GPIO27_INT_ENA_OFFSET 1
|
|
#define GPIO27_INT_ENA_MASK 0x00000002
|
|
#define GPIO27_CLR_OFFSET 0
|
|
#define GPIO27_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO28_CFG_ADDR 0x270
|
|
#define GPIO28_OD_MODE_OFFSET 12
|
|
#define GPIO28_OD_MODE_MASK 0x00003000
|
|
#define GPIO28_OUT_OFFSET 11
|
|
#define GPIO28_OUT_MASK 0x00000800
|
|
#define GPIO28_OE_OFFSET 10
|
|
#define GPIO28_OE_MASK 0x00000400
|
|
#define GPIO28_IE_OFFSET 9
|
|
#define GPIO28_IE_MASK 0x00000200
|
|
#define GPIO28_IN_OFFSET 8
|
|
#define GPIO28_IN_MASK 0x00000100
|
|
#define GPIO28_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO28_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO28_INT_TYPE_OFFSET 4
|
|
#define GPIO28_INT_TYPE_MASK 0x00000070
|
|
#define GPIO28_INT_RAW_OFFSET 3
|
|
#define GPIO28_INT_RAW_MASK 0x00000008
|
|
#define GPIO28_INT_STS_OFFSET 2
|
|
#define GPIO28_INT_STS_MASK 0x00000004
|
|
#define GPIO28_INT_ENA_OFFSET 1
|
|
#define GPIO28_INT_ENA_MASK 0x00000002
|
|
#define GPIO28_CLR_OFFSET 0
|
|
#define GPIO28_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO29_CFG_ADDR 0x274
|
|
#define GPIO29_OD_MODE_OFFSET 12
|
|
#define GPIO29_OD_MODE_MASK 0x00003000
|
|
#define GPIO29_OUT_OFFSET 11
|
|
#define GPIO29_OUT_MASK 0x00000800
|
|
#define GPIO29_OE_OFFSET 10
|
|
#define GPIO29_OE_MASK 0x00000400
|
|
#define GPIO29_IE_OFFSET 9
|
|
#define GPIO29_IE_MASK 0x00000200
|
|
#define GPIO29_IN_OFFSET 8
|
|
#define GPIO29_IN_MASK 0x00000100
|
|
#define GPIO29_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO29_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO29_INT_TYPE_OFFSET 4
|
|
#define GPIO29_INT_TYPE_MASK 0x00000070
|
|
#define GPIO29_INT_RAW_OFFSET 3
|
|
#define GPIO29_INT_RAW_MASK 0x00000008
|
|
#define GPIO29_INT_STS_OFFSET 2
|
|
#define GPIO29_INT_STS_MASK 0x00000004
|
|
#define GPIO29_INT_ENA_OFFSET 1
|
|
#define GPIO29_INT_ENA_MASK 0x00000002
|
|
#define GPIO29_CLR_OFFSET 0
|
|
#define GPIO29_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO30_CFG_ADDR 0x278
|
|
#define GPIO30_OD_MODE_OFFSET 12
|
|
#define GPIO30_OD_MODE_MASK 0x00003000
|
|
#define GPIO30_OUT_OFFSET 11
|
|
#define GPIO30_OUT_MASK 0x00000800
|
|
#define GPIO30_OE_OFFSET 10
|
|
#define GPIO30_OE_MASK 0x00000400
|
|
#define GPIO30_IE_OFFSET 9
|
|
#define GPIO30_IE_MASK 0x00000200
|
|
#define GPIO30_IN_OFFSET 8
|
|
#define GPIO30_IN_MASK 0x00000100
|
|
#define GPIO30_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO30_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO30_INT_TYPE_OFFSET 4
|
|
#define GPIO30_INT_TYPE_MASK 0x00000070
|
|
#define GPIO30_INT_RAW_OFFSET 3
|
|
#define GPIO30_INT_RAW_MASK 0x00000008
|
|
#define GPIO30_INT_STS_OFFSET 2
|
|
#define GPIO30_INT_STS_MASK 0x00000004
|
|
#define GPIO30_INT_ENA_OFFSET 1
|
|
#define GPIO30_INT_ENA_MASK 0x00000002
|
|
#define GPIO30_CLR_OFFSET 0
|
|
#define GPIO30_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO31_CFG_ADDR 0x27c
|
|
#define GPIO31_OD_MODE_OFFSET 12
|
|
#define GPIO31_OD_MODE_MASK 0x00003000
|
|
#define GPIO31_OUT_OFFSET 11
|
|
#define GPIO31_OUT_MASK 0x00000800
|
|
#define GPIO31_OE_OFFSET 10
|
|
#define GPIO31_OE_MASK 0x00000400
|
|
#define GPIO31_IE_OFFSET 9
|
|
#define GPIO31_IE_MASK 0x00000200
|
|
#define GPIO31_IN_OFFSET 8
|
|
#define GPIO31_IN_MASK 0x00000100
|
|
#define GPIO31_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO31_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO31_INT_TYPE_OFFSET 4
|
|
#define GPIO31_INT_TYPE_MASK 0x00000070
|
|
#define GPIO31_INT_RAW_OFFSET 3
|
|
#define GPIO31_INT_RAW_MASK 0x00000008
|
|
#define GPIO31_INT_STS_OFFSET 2
|
|
#define GPIO31_INT_STS_MASK 0x00000004
|
|
#define GPIO31_INT_ENA_OFFSET 1
|
|
#define GPIO31_INT_ENA_MASK 0x00000002
|
|
#define GPIO31_CLR_OFFSET 0
|
|
#define GPIO31_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO32_CFG_ADDR 0x280
|
|
#define GPIO32_OD_MODE_OFFSET 12
|
|
#define GPIO32_OD_MODE_MASK 0x00003000
|
|
#define GPIO32_OUT_OFFSET 11
|
|
#define GPIO32_OUT_MASK 0x00000800
|
|
#define GPIO32_OE_OFFSET 10
|
|
#define GPIO32_OE_MASK 0x00000400
|
|
#define GPIO32_IE_OFFSET 9
|
|
#define GPIO32_IE_MASK 0x00000200
|
|
#define GPIO32_IN_OFFSET 8
|
|
#define GPIO32_IN_MASK 0x00000100
|
|
#define GPIO32_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO32_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO32_INT_TYPE_OFFSET 4
|
|
#define GPIO32_INT_TYPE_MASK 0x00000070
|
|
#define GPIO32_INT_RAW_OFFSET 3
|
|
#define GPIO32_INT_RAW_MASK 0x00000008
|
|
#define GPIO32_INT_STS_OFFSET 2
|
|
#define GPIO32_INT_STS_MASK 0x00000004
|
|
#define GPIO32_INT_ENA_OFFSET 1
|
|
#define GPIO32_INT_ENA_MASK 0x00000002
|
|
#define GPIO32_CLR_OFFSET 0
|
|
#define GPIO32_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO33_CFG_ADDR 0x284
|
|
#define GPIO33_OD_MODE_OFFSET 12
|
|
#define GPIO33_OD_MODE_MASK 0x00003000
|
|
#define GPIO33_OUT_OFFSET 11
|
|
#define GPIO33_OUT_MASK 0x00000800
|
|
#define GPIO33_OE_OFFSET 10
|
|
#define GPIO33_OE_MASK 0x00000400
|
|
#define GPIO33_IE_OFFSET 9
|
|
#define GPIO33_IE_MASK 0x00000200
|
|
#define GPIO33_IN_OFFSET 8
|
|
#define GPIO33_IN_MASK 0x00000100
|
|
#define GPIO33_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO33_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO33_INT_TYPE_OFFSET 4
|
|
#define GPIO33_INT_TYPE_MASK 0x00000070
|
|
#define GPIO33_INT_RAW_OFFSET 3
|
|
#define GPIO33_INT_RAW_MASK 0x00000008
|
|
#define GPIO33_INT_STS_OFFSET 2
|
|
#define GPIO33_INT_STS_MASK 0x00000004
|
|
#define GPIO33_INT_ENA_OFFSET 1
|
|
#define GPIO33_INT_ENA_MASK 0x00000002
|
|
#define GPIO33_CLR_OFFSET 0
|
|
#define GPIO33_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO34_CFG_ADDR 0x288
|
|
#define GPIO34_OD_MODE_OFFSET 12
|
|
#define GPIO34_OD_MODE_MASK 0x00003000
|
|
#define GPIO34_OUT_OFFSET 11
|
|
#define GPIO34_OUT_MASK 0x00000800
|
|
#define GPIO34_OE_OFFSET 10
|
|
#define GPIO34_OE_MASK 0x00000400
|
|
#define GPIO34_IE_OFFSET 9
|
|
#define GPIO34_IE_MASK 0x00000200
|
|
#define GPIO34_IN_OFFSET 8
|
|
#define GPIO34_IN_MASK 0x00000100
|
|
#define GPIO34_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO34_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO34_INT_TYPE_OFFSET 4
|
|
#define GPIO34_INT_TYPE_MASK 0x00000070
|
|
#define GPIO34_INT_RAW_OFFSET 3
|
|
#define GPIO34_INT_RAW_MASK 0x00000008
|
|
#define GPIO34_INT_STS_OFFSET 2
|
|
#define GPIO34_INT_STS_MASK 0x00000004
|
|
#define GPIO34_INT_ENA_OFFSET 1
|
|
#define GPIO34_INT_ENA_MASK 0x00000002
|
|
#define GPIO34_CLR_OFFSET 0
|
|
#define GPIO34_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO35_CFG_ADDR 0x28c
|
|
#define GPIO35_OD_MODE_OFFSET 12
|
|
#define GPIO35_OD_MODE_MASK 0x00003000
|
|
#define GPIO35_OUT_OFFSET 11
|
|
#define GPIO35_OUT_MASK 0x00000800
|
|
#define GPIO35_OE_OFFSET 10
|
|
#define GPIO35_OE_MASK 0x00000400
|
|
#define GPIO35_IE_OFFSET 9
|
|
#define GPIO35_IE_MASK 0x00000200
|
|
#define GPIO35_IN_OFFSET 8
|
|
#define GPIO35_IN_MASK 0x00000100
|
|
#define GPIO35_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO35_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO35_INT_TYPE_OFFSET 4
|
|
#define GPIO35_INT_TYPE_MASK 0x00000070
|
|
#define GPIO35_INT_RAW_OFFSET 3
|
|
#define GPIO35_INT_RAW_MASK 0x00000008
|
|
#define GPIO35_INT_STS_OFFSET 2
|
|
#define GPIO35_INT_STS_MASK 0x00000004
|
|
#define GPIO35_INT_ENA_OFFSET 1
|
|
#define GPIO35_INT_ENA_MASK 0x00000002
|
|
#define GPIO35_CLR_OFFSET 0
|
|
#define GPIO35_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO36_CFG_ADDR 0x290
|
|
#define GPIO36_OD_MODE_OFFSET 12
|
|
#define GPIO36_OD_MODE_MASK 0x00003000
|
|
#define GPIO36_OUT_OFFSET 11
|
|
#define GPIO36_OUT_MASK 0x00000800
|
|
#define GPIO36_OE_OFFSET 10
|
|
#define GPIO36_OE_MASK 0x00000400
|
|
#define GPIO36_IE_OFFSET 9
|
|
#define GPIO36_IE_MASK 0x00000200
|
|
#define GPIO36_IN_OFFSET 8
|
|
#define GPIO36_IN_MASK 0x00000100
|
|
#define GPIO36_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO36_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO36_INT_TYPE_OFFSET 4
|
|
#define GPIO36_INT_TYPE_MASK 0x00000070
|
|
#define GPIO36_INT_RAW_OFFSET 3
|
|
#define GPIO36_INT_RAW_MASK 0x00000008
|
|
#define GPIO36_INT_STS_OFFSET 2
|
|
#define GPIO36_INT_STS_MASK 0x00000004
|
|
#define GPIO36_INT_ENA_OFFSET 1
|
|
#define GPIO36_INT_ENA_MASK 0x00000002
|
|
#define GPIO36_CLR_OFFSET 0
|
|
#define GPIO36_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO37_CFG_ADDR 0x294
|
|
#define GPIO37_OD_MODE_OFFSET 12
|
|
#define GPIO37_OD_MODE_MASK 0x00003000
|
|
#define GPIO37_OUT_OFFSET 11
|
|
#define GPIO37_OUT_MASK 0x00000800
|
|
#define GPIO37_OE_OFFSET 10
|
|
#define GPIO37_OE_MASK 0x00000400
|
|
#define GPIO37_IE_OFFSET 9
|
|
#define GPIO37_IE_MASK 0x00000200
|
|
#define GPIO37_IN_OFFSET 8
|
|
#define GPIO37_IN_MASK 0x00000100
|
|
#define GPIO37_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO37_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO37_INT_TYPE_OFFSET 4
|
|
#define GPIO37_INT_TYPE_MASK 0x00000070
|
|
#define GPIO37_INT_RAW_OFFSET 3
|
|
#define GPIO37_INT_RAW_MASK 0x00000008
|
|
#define GPIO37_INT_STS_OFFSET 2
|
|
#define GPIO37_INT_STS_MASK 0x00000004
|
|
#define GPIO37_INT_ENA_OFFSET 1
|
|
#define GPIO37_INT_ENA_MASK 0x00000002
|
|
#define GPIO37_CLR_OFFSET 0
|
|
#define GPIO37_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO38_CFG_ADDR 0x298
|
|
#define GPIO38_OD_MODE_OFFSET 12
|
|
#define GPIO38_OD_MODE_MASK 0x00003000
|
|
#define GPIO38_OUT_OFFSET 11
|
|
#define GPIO38_OUT_MASK 0x00000800
|
|
#define GPIO38_OE_OFFSET 10
|
|
#define GPIO38_OE_MASK 0x00000400
|
|
#define GPIO38_IE_OFFSET 9
|
|
#define GPIO38_IE_MASK 0x00000200
|
|
#define GPIO38_IN_OFFSET 8
|
|
#define GPIO38_IN_MASK 0x00000100
|
|
#define GPIO38_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO38_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO38_INT_TYPE_OFFSET 4
|
|
#define GPIO38_INT_TYPE_MASK 0x00000070
|
|
#define GPIO38_INT_RAW_OFFSET 3
|
|
#define GPIO38_INT_RAW_MASK 0x00000008
|
|
#define GPIO38_INT_STS_OFFSET 2
|
|
#define GPIO38_INT_STS_MASK 0x00000004
|
|
#define GPIO38_INT_ENA_OFFSET 1
|
|
#define GPIO38_INT_ENA_MASK 0x00000002
|
|
#define GPIO38_CLR_OFFSET 0
|
|
#define GPIO38_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO39_CFG_ADDR 0x29c
|
|
#define GPIO39_OD_MODE_OFFSET 12
|
|
#define GPIO39_OD_MODE_MASK 0x00003000
|
|
#define GPIO39_OUT_OFFSET 11
|
|
#define GPIO39_OUT_MASK 0x00000800
|
|
#define GPIO39_OE_OFFSET 10
|
|
#define GPIO39_OE_MASK 0x00000400
|
|
#define GPIO39_IE_OFFSET 9
|
|
#define GPIO39_IE_MASK 0x00000200
|
|
#define GPIO39_IN_OFFSET 8
|
|
#define GPIO39_IN_MASK 0x00000100
|
|
#define GPIO39_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO39_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO39_INT_TYPE_OFFSET 4
|
|
#define GPIO39_INT_TYPE_MASK 0x00000070
|
|
#define GPIO39_INT_RAW_OFFSET 3
|
|
#define GPIO39_INT_RAW_MASK 0x00000008
|
|
#define GPIO39_INT_STS_OFFSET 2
|
|
#define GPIO39_INT_STS_MASK 0x00000004
|
|
#define GPIO39_INT_ENA_OFFSET 1
|
|
#define GPIO39_INT_ENA_MASK 0x00000002
|
|
#define GPIO39_CLR_OFFSET 0
|
|
#define GPIO39_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO40_CFG_ADDR 0x2a0
|
|
#define GPIO40_OD_MODE_OFFSET 12
|
|
#define GPIO40_OD_MODE_MASK 0x00003000
|
|
#define GPIO40_OUT_OFFSET 11
|
|
#define GPIO40_OUT_MASK 0x00000800
|
|
#define GPIO40_OE_OFFSET 10
|
|
#define GPIO40_OE_MASK 0x00000400
|
|
#define GPIO40_IE_OFFSET 9
|
|
#define GPIO40_IE_MASK 0x00000200
|
|
#define GPIO40_IN_OFFSET 8
|
|
#define GPIO40_IN_MASK 0x00000100
|
|
#define GPIO40_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO40_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO40_INT_TYPE_OFFSET 4
|
|
#define GPIO40_INT_TYPE_MASK 0x00000070
|
|
#define GPIO40_INT_RAW_OFFSET 3
|
|
#define GPIO40_INT_RAW_MASK 0x00000008
|
|
#define GPIO40_INT_STS_OFFSET 2
|
|
#define GPIO40_INT_STS_MASK 0x00000004
|
|
#define GPIO40_INT_ENA_OFFSET 1
|
|
#define GPIO40_INT_ENA_MASK 0x00000002
|
|
#define GPIO40_CLR_OFFSET 0
|
|
#define GPIO40_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO41_CFG_ADDR 0x2a4
|
|
#define GPIO41_OD_MODE_OFFSET 12
|
|
#define GPIO41_OD_MODE_MASK 0x00003000
|
|
#define GPIO41_OUT_OFFSET 11
|
|
#define GPIO41_OUT_MASK 0x00000800
|
|
#define GPIO41_OE_OFFSET 10
|
|
#define GPIO41_OE_MASK 0x00000400
|
|
#define GPIO41_IE_OFFSET 9
|
|
#define GPIO41_IE_MASK 0x00000200
|
|
#define GPIO41_IN_OFFSET 8
|
|
#define GPIO41_IN_MASK 0x00000100
|
|
#define GPIO41_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO41_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO41_INT_TYPE_OFFSET 4
|
|
#define GPIO41_INT_TYPE_MASK 0x00000070
|
|
#define GPIO41_INT_RAW_OFFSET 3
|
|
#define GPIO41_INT_RAW_MASK 0x00000008
|
|
#define GPIO41_INT_STS_OFFSET 2
|
|
#define GPIO41_INT_STS_MASK 0x00000004
|
|
#define GPIO41_INT_ENA_OFFSET 1
|
|
#define GPIO41_INT_ENA_MASK 0x00000002
|
|
#define GPIO41_CLR_OFFSET 0
|
|
#define GPIO41_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO42_CFG_ADDR 0x2a8
|
|
#define GPIO42_OD_MODE_OFFSET 12
|
|
#define GPIO42_OD_MODE_MASK 0x00003000
|
|
#define GPIO42_OUT_OFFSET 11
|
|
#define GPIO42_OUT_MASK 0x00000800
|
|
#define GPIO42_OE_OFFSET 10
|
|
#define GPIO42_OE_MASK 0x00000400
|
|
#define GPIO42_IE_OFFSET 9
|
|
#define GPIO42_IE_MASK 0x00000200
|
|
#define GPIO42_IN_OFFSET 8
|
|
#define GPIO42_IN_MASK 0x00000100
|
|
#define GPIO42_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO42_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO42_INT_TYPE_OFFSET 4
|
|
#define GPIO42_INT_TYPE_MASK 0x00000070
|
|
#define GPIO42_INT_RAW_OFFSET 3
|
|
#define GPIO42_INT_RAW_MASK 0x00000008
|
|
#define GPIO42_INT_STS_OFFSET 2
|
|
#define GPIO42_INT_STS_MASK 0x00000004
|
|
#define GPIO42_INT_ENA_OFFSET 1
|
|
#define GPIO42_INT_ENA_MASK 0x00000002
|
|
#define GPIO42_CLR_OFFSET 0
|
|
#define GPIO42_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO43_CFG_ADDR 0x2ac
|
|
#define GPIO43_OD_MODE_OFFSET 12
|
|
#define GPIO43_OD_MODE_MASK 0x00003000
|
|
#define GPIO43_OUT_OFFSET 11
|
|
#define GPIO43_OUT_MASK 0x00000800
|
|
#define GPIO43_OE_OFFSET 10
|
|
#define GPIO43_OE_MASK 0x00000400
|
|
#define GPIO43_IE_OFFSET 9
|
|
#define GPIO43_IE_MASK 0x00000200
|
|
#define GPIO43_IN_OFFSET 8
|
|
#define GPIO43_IN_MASK 0x00000100
|
|
#define GPIO43_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO43_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO43_INT_TYPE_OFFSET 4
|
|
#define GPIO43_INT_TYPE_MASK 0x00000070
|
|
#define GPIO43_INT_RAW_OFFSET 3
|
|
#define GPIO43_INT_RAW_MASK 0x00000008
|
|
#define GPIO43_INT_STS_OFFSET 2
|
|
#define GPIO43_INT_STS_MASK 0x00000004
|
|
#define GPIO43_INT_ENA_OFFSET 1
|
|
#define GPIO43_INT_ENA_MASK 0x00000002
|
|
#define GPIO43_CLR_OFFSET 0
|
|
#define GPIO43_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO44_CFG_ADDR 0x2b0
|
|
#define GPIO44_OD_MODE_OFFSET 12
|
|
#define GPIO44_OD_MODE_MASK 0x00003000
|
|
#define GPIO44_OUT_OFFSET 11
|
|
#define GPIO44_OUT_MASK 0x00000800
|
|
#define GPIO44_OE_OFFSET 10
|
|
#define GPIO44_OE_MASK 0x00000400
|
|
#define GPIO44_IE_OFFSET 9
|
|
#define GPIO44_IE_MASK 0x00000200
|
|
#define GPIO44_IN_OFFSET 8
|
|
#define GPIO44_IN_MASK 0x00000100
|
|
#define GPIO44_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO44_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO44_INT_TYPE_OFFSET 4
|
|
#define GPIO44_INT_TYPE_MASK 0x00000070
|
|
#define GPIO44_INT_RAW_OFFSET 3
|
|
#define GPIO44_INT_RAW_MASK 0x00000008
|
|
#define GPIO44_INT_STS_OFFSET 2
|
|
#define GPIO44_INT_STS_MASK 0x00000004
|
|
#define GPIO44_INT_ENA_OFFSET 1
|
|
#define GPIO44_INT_ENA_MASK 0x00000002
|
|
#define GPIO44_CLR_OFFSET 0
|
|
#define GPIO44_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO45_CFG_ADDR 0x2b4
|
|
#define GPIO45_OD_MODE_OFFSET 12
|
|
#define GPIO45_OD_MODE_MASK 0x00003000
|
|
#define GPIO45_OUT_OFFSET 11
|
|
#define GPIO45_OUT_MASK 0x00000800
|
|
#define GPIO45_OE_OFFSET 10
|
|
#define GPIO45_OE_MASK 0x00000400
|
|
#define GPIO45_IE_OFFSET 9
|
|
#define GPIO45_IE_MASK 0x00000200
|
|
#define GPIO45_IN_OFFSET 8
|
|
#define GPIO45_IN_MASK 0x00000100
|
|
#define GPIO45_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO45_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO45_INT_TYPE_OFFSET 4
|
|
#define GPIO45_INT_TYPE_MASK 0x00000070
|
|
#define GPIO45_INT_RAW_OFFSET 3
|
|
#define GPIO45_INT_RAW_MASK 0x00000008
|
|
#define GPIO45_INT_STS_OFFSET 2
|
|
#define GPIO45_INT_STS_MASK 0x00000004
|
|
#define GPIO45_INT_ENA_OFFSET 1
|
|
#define GPIO45_INT_ENA_MASK 0x00000002
|
|
#define GPIO45_CLR_OFFSET 0
|
|
#define GPIO45_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO46_CFG_ADDR 0x2b8
|
|
#define GPIO46_OD_MODE_OFFSET 12
|
|
#define GPIO46_OD_MODE_MASK 0x00003000
|
|
#define GPIO46_OUT_OFFSET 11
|
|
#define GPIO46_OUT_MASK 0x00000800
|
|
#define GPIO46_OE_OFFSET 10
|
|
#define GPIO46_OE_MASK 0x00000400
|
|
#define GPIO46_IE_OFFSET 9
|
|
#define GPIO46_IE_MASK 0x00000200
|
|
#define GPIO46_IN_OFFSET 8
|
|
#define GPIO46_IN_MASK 0x00000100
|
|
#define GPIO46_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO46_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO46_INT_TYPE_OFFSET 4
|
|
#define GPIO46_INT_TYPE_MASK 0x00000070
|
|
#define GPIO46_INT_RAW_OFFSET 3
|
|
#define GPIO46_INT_RAW_MASK 0x00000008
|
|
#define GPIO46_INT_STS_OFFSET 2
|
|
#define GPIO46_INT_STS_MASK 0x00000004
|
|
#define GPIO46_INT_ENA_OFFSET 1
|
|
#define GPIO46_INT_ENA_MASK 0x00000002
|
|
#define GPIO46_CLR_OFFSET 0
|
|
#define GPIO46_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO47_CFG_ADDR 0x2bc
|
|
#define GPIO47_OD_MODE_OFFSET 12
|
|
#define GPIO47_OD_MODE_MASK 0x00003000
|
|
#define GPIO47_OUT_OFFSET 11
|
|
#define GPIO47_OUT_MASK 0x00000800
|
|
#define GPIO47_OE_OFFSET 10
|
|
#define GPIO47_OE_MASK 0x00000400
|
|
#define GPIO47_IE_OFFSET 9
|
|
#define GPIO47_IE_MASK 0x00000200
|
|
#define GPIO47_IN_OFFSET 8
|
|
#define GPIO47_IN_MASK 0x00000100
|
|
#define GPIO47_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO47_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO47_INT_TYPE_OFFSET 4
|
|
#define GPIO47_INT_TYPE_MASK 0x00000070
|
|
#define GPIO47_INT_RAW_OFFSET 3
|
|
#define GPIO47_INT_RAW_MASK 0x00000008
|
|
#define GPIO47_INT_STS_OFFSET 2
|
|
#define GPIO47_INT_STS_MASK 0x00000004
|
|
#define GPIO47_INT_ENA_OFFSET 1
|
|
#define GPIO47_INT_ENA_MASK 0x00000002
|
|
#define GPIO47_CLR_OFFSET 0
|
|
#define GPIO47_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO48_CFG_ADDR 0x2c0
|
|
#define GPIO48_OD_MODE_OFFSET 12
|
|
#define GPIO48_OD_MODE_MASK 0x00003000
|
|
#define GPIO48_OUT_OFFSET 11
|
|
#define GPIO48_OUT_MASK 0x00000800
|
|
#define GPIO48_OE_OFFSET 10
|
|
#define GPIO48_OE_MASK 0x00000400
|
|
#define GPIO48_IE_OFFSET 9
|
|
#define GPIO48_IE_MASK 0x00000200
|
|
#define GPIO48_IN_OFFSET 8
|
|
#define GPIO48_IN_MASK 0x00000100
|
|
#define GPIO48_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO48_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO48_INT_TYPE_OFFSET 4
|
|
#define GPIO48_INT_TYPE_MASK 0x00000070
|
|
#define GPIO48_INT_RAW_OFFSET 3
|
|
#define GPIO48_INT_RAW_MASK 0x00000008
|
|
#define GPIO48_INT_STS_OFFSET 2
|
|
#define GPIO48_INT_STS_MASK 0x00000004
|
|
#define GPIO48_INT_ENA_OFFSET 1
|
|
#define GPIO48_INT_ENA_MASK 0x00000002
|
|
#define GPIO48_CLR_OFFSET 0
|
|
#define GPIO48_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO49_CFG_ADDR 0x2c4
|
|
#define GPIO49_OD_MODE_OFFSET 12
|
|
#define GPIO49_OD_MODE_MASK 0x00003000
|
|
#define GPIO49_OUT_OFFSET 11
|
|
#define GPIO49_OUT_MASK 0x00000800
|
|
#define GPIO49_OE_OFFSET 10
|
|
#define GPIO49_OE_MASK 0x00000400
|
|
#define GPIO49_IE_OFFSET 9
|
|
#define GPIO49_IE_MASK 0x00000200
|
|
#define GPIO49_IN_OFFSET 8
|
|
#define GPIO49_IN_MASK 0x00000100
|
|
#define GPIO49_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO49_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO49_INT_TYPE_OFFSET 4
|
|
#define GPIO49_INT_TYPE_MASK 0x00000070
|
|
#define GPIO49_INT_RAW_OFFSET 3
|
|
#define GPIO49_INT_RAW_MASK 0x00000008
|
|
#define GPIO49_INT_STS_OFFSET 2
|
|
#define GPIO49_INT_STS_MASK 0x00000004
|
|
#define GPIO49_INT_ENA_OFFSET 1
|
|
#define GPIO49_INT_ENA_MASK 0x00000002
|
|
#define GPIO49_CLR_OFFSET 0
|
|
#define GPIO49_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO50_CFG_ADDR 0x2c8
|
|
#define GPIO50_OD_MODE_OFFSET 12
|
|
#define GPIO50_OD_MODE_MASK 0x00003000
|
|
#define GPIO50_OUT_OFFSET 11
|
|
#define GPIO50_OUT_MASK 0x00000800
|
|
#define GPIO50_OE_OFFSET 10
|
|
#define GPIO50_OE_MASK 0x00000400
|
|
#define GPIO50_IE_OFFSET 9
|
|
#define GPIO50_IE_MASK 0x00000200
|
|
#define GPIO50_IN_OFFSET 8
|
|
#define GPIO50_IN_MASK 0x00000100
|
|
#define GPIO50_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO50_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO50_INT_TYPE_OFFSET 4
|
|
#define GPIO50_INT_TYPE_MASK 0x00000070
|
|
#define GPIO50_INT_RAW_OFFSET 3
|
|
#define GPIO50_INT_RAW_MASK 0x00000008
|
|
#define GPIO50_INT_STS_OFFSET 2
|
|
#define GPIO50_INT_STS_MASK 0x00000004
|
|
#define GPIO50_INT_ENA_OFFSET 1
|
|
#define GPIO50_INT_ENA_MASK 0x00000002
|
|
#define GPIO50_CLR_OFFSET 0
|
|
#define GPIO50_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO51_CFG_ADDR 0x2cc
|
|
#define GPIO51_OD_MODE_OFFSET 12
|
|
#define GPIO51_OD_MODE_MASK 0x00003000
|
|
#define GPIO51_OUT_OFFSET 11
|
|
#define GPIO51_OUT_MASK 0x00000800
|
|
#define GPIO51_OE_OFFSET 10
|
|
#define GPIO51_OE_MASK 0x00000400
|
|
#define GPIO51_IE_OFFSET 9
|
|
#define GPIO51_IE_MASK 0x00000200
|
|
#define GPIO51_IN_OFFSET 8
|
|
#define GPIO51_IN_MASK 0x00000100
|
|
#define GPIO51_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO51_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO51_INT_TYPE_OFFSET 4
|
|
#define GPIO51_INT_TYPE_MASK 0x00000070
|
|
#define GPIO51_INT_RAW_OFFSET 3
|
|
#define GPIO51_INT_RAW_MASK 0x00000008
|
|
#define GPIO51_INT_STS_OFFSET 2
|
|
#define GPIO51_INT_STS_MASK 0x00000004
|
|
#define GPIO51_INT_ENA_OFFSET 1
|
|
#define GPIO51_INT_ENA_MASK 0x00000002
|
|
#define GPIO51_CLR_OFFSET 0
|
|
#define GPIO51_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO52_CFG_ADDR 0x2d0
|
|
#define GPIO52_OD_MODE_OFFSET 12
|
|
#define GPIO52_OD_MODE_MASK 0x00003000
|
|
#define GPIO52_OUT_OFFSET 11
|
|
#define GPIO52_OUT_MASK 0x00000800
|
|
#define GPIO52_OE_OFFSET 10
|
|
#define GPIO52_OE_MASK 0x00000400
|
|
#define GPIO52_IE_OFFSET 9
|
|
#define GPIO52_IE_MASK 0x00000200
|
|
#define GPIO52_IN_OFFSET 8
|
|
#define GPIO52_IN_MASK 0x00000100
|
|
#define GPIO52_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO52_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO52_INT_TYPE_OFFSET 4
|
|
#define GPIO52_INT_TYPE_MASK 0x00000070
|
|
#define GPIO52_INT_RAW_OFFSET 3
|
|
#define GPIO52_INT_RAW_MASK 0x00000008
|
|
#define GPIO52_INT_STS_OFFSET 2
|
|
#define GPIO52_INT_STS_MASK 0x00000004
|
|
#define GPIO52_INT_ENA_OFFSET 1
|
|
#define GPIO52_INT_ENA_MASK 0x00000002
|
|
#define GPIO52_CLR_OFFSET 0
|
|
#define GPIO52_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO53_CFG_ADDR 0x2d4
|
|
#define GPIO53_OD_MODE_OFFSET 12
|
|
#define GPIO53_OD_MODE_MASK 0x00003000
|
|
#define GPIO53_OUT_OFFSET 11
|
|
#define GPIO53_OUT_MASK 0x00000800
|
|
#define GPIO53_OE_OFFSET 10
|
|
#define GPIO53_OE_MASK 0x00000400
|
|
#define GPIO53_IE_OFFSET 9
|
|
#define GPIO53_IE_MASK 0x00000200
|
|
#define GPIO53_IN_OFFSET 8
|
|
#define GPIO53_IN_MASK 0x00000100
|
|
#define GPIO53_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO53_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO53_INT_TYPE_OFFSET 4
|
|
#define GPIO53_INT_TYPE_MASK 0x00000070
|
|
#define GPIO53_INT_RAW_OFFSET 3
|
|
#define GPIO53_INT_RAW_MASK 0x00000008
|
|
#define GPIO53_INT_STS_OFFSET 2
|
|
#define GPIO53_INT_STS_MASK 0x00000004
|
|
#define GPIO53_INT_ENA_OFFSET 1
|
|
#define GPIO53_INT_ENA_MASK 0x00000002
|
|
#define GPIO53_CLR_OFFSET 0
|
|
#define GPIO53_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO54_CFG_ADDR 0x2d8
|
|
#define GPIO54_OD_MODE_OFFSET 12
|
|
#define GPIO54_OD_MODE_MASK 0x00003000
|
|
#define GPIO54_OUT_OFFSET 11
|
|
#define GPIO54_OUT_MASK 0x00000800
|
|
#define GPIO54_OE_OFFSET 10
|
|
#define GPIO54_OE_MASK 0x00000400
|
|
#define GPIO54_IE_OFFSET 9
|
|
#define GPIO54_IE_MASK 0x00000200
|
|
#define GPIO54_IN_OFFSET 8
|
|
#define GPIO54_IN_MASK 0x00000100
|
|
#define GPIO54_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO54_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO54_INT_TYPE_OFFSET 4
|
|
#define GPIO54_INT_TYPE_MASK 0x00000070
|
|
#define GPIO54_INT_RAW_OFFSET 3
|
|
#define GPIO54_INT_RAW_MASK 0x00000008
|
|
#define GPIO54_INT_STS_OFFSET 2
|
|
#define GPIO54_INT_STS_MASK 0x00000004
|
|
#define GPIO54_INT_ENA_OFFSET 1
|
|
#define GPIO54_INT_ENA_MASK 0x00000002
|
|
#define GPIO54_CLR_OFFSET 0
|
|
#define GPIO54_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO55_CFG_ADDR 0x2dc
|
|
#define GPIO55_OD_MODE_OFFSET 12
|
|
#define GPIO55_OD_MODE_MASK 0x00003000
|
|
#define GPIO55_OUT_OFFSET 11
|
|
#define GPIO55_OUT_MASK 0x00000800
|
|
#define GPIO55_OE_OFFSET 10
|
|
#define GPIO55_OE_MASK 0x00000400
|
|
#define GPIO55_IE_OFFSET 9
|
|
#define GPIO55_IE_MASK 0x00000200
|
|
#define GPIO55_IN_OFFSET 8
|
|
#define GPIO55_IN_MASK 0x00000100
|
|
#define GPIO55_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO55_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO55_INT_TYPE_OFFSET 4
|
|
#define GPIO55_INT_TYPE_MASK 0x00000070
|
|
#define GPIO55_INT_RAW_OFFSET 3
|
|
#define GPIO55_INT_RAW_MASK 0x00000008
|
|
#define GPIO55_INT_STS_OFFSET 2
|
|
#define GPIO55_INT_STS_MASK 0x00000004
|
|
#define GPIO55_INT_ENA_OFFSET 1
|
|
#define GPIO55_INT_ENA_MASK 0x00000002
|
|
#define GPIO55_CLR_OFFSET 0
|
|
#define GPIO55_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO56_CFG_ADDR 0x2e0
|
|
#define GPIO56_OD_MODE_OFFSET 12
|
|
#define GPIO56_OD_MODE_MASK 0x00003000
|
|
#define GPIO56_OUT_OFFSET 11
|
|
#define GPIO56_OUT_MASK 0x00000800
|
|
#define GPIO56_OE_OFFSET 10
|
|
#define GPIO56_OE_MASK 0x00000400
|
|
#define GPIO56_IE_OFFSET 9
|
|
#define GPIO56_IE_MASK 0x00000200
|
|
#define GPIO56_IN_OFFSET 8
|
|
#define GPIO56_IN_MASK 0x00000100
|
|
#define GPIO56_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO56_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO56_INT_TYPE_OFFSET 4
|
|
#define GPIO56_INT_TYPE_MASK 0x00000070
|
|
#define GPIO56_INT_RAW_OFFSET 3
|
|
#define GPIO56_INT_RAW_MASK 0x00000008
|
|
#define GPIO56_INT_STS_OFFSET 2
|
|
#define GPIO56_INT_STS_MASK 0x00000004
|
|
#define GPIO56_INT_ENA_OFFSET 1
|
|
#define GPIO56_INT_ENA_MASK 0x00000002
|
|
#define GPIO56_CLR_OFFSET 0
|
|
#define GPIO56_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO57_CFG_ADDR 0x2e4
|
|
#define GPIO57_OD_MODE_OFFSET 12
|
|
#define GPIO57_OD_MODE_MASK 0x00003000
|
|
#define GPIO57_OUT_OFFSET 11
|
|
#define GPIO57_OUT_MASK 0x00000800
|
|
#define GPIO57_OE_OFFSET 10
|
|
#define GPIO57_OE_MASK 0x00000400
|
|
#define GPIO57_IE_OFFSET 9
|
|
#define GPIO57_IE_MASK 0x00000200
|
|
#define GPIO57_IN_OFFSET 8
|
|
#define GPIO57_IN_MASK 0x00000100
|
|
#define GPIO57_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO57_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO57_INT_TYPE_OFFSET 4
|
|
#define GPIO57_INT_TYPE_MASK 0x00000070
|
|
#define GPIO57_INT_RAW_OFFSET 3
|
|
#define GPIO57_INT_RAW_MASK 0x00000008
|
|
#define GPIO57_INT_STS_OFFSET 2
|
|
#define GPIO57_INT_STS_MASK 0x00000004
|
|
#define GPIO57_INT_ENA_OFFSET 1
|
|
#define GPIO57_INT_ENA_MASK 0x00000002
|
|
#define GPIO57_CLR_OFFSET 0
|
|
#define GPIO57_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO58_CFG_ADDR 0x2e8
|
|
#define GPIO58_OD_MODE_OFFSET 12
|
|
#define GPIO58_OD_MODE_MASK 0x00003000
|
|
#define GPIO58_OUT_OFFSET 11
|
|
#define GPIO58_OUT_MASK 0x00000800
|
|
#define GPIO58_OE_OFFSET 10
|
|
#define GPIO58_OE_MASK 0x00000400
|
|
#define GPIO58_IE_OFFSET 9
|
|
#define GPIO58_IE_MASK 0x00000200
|
|
#define GPIO58_IN_OFFSET 8
|
|
#define GPIO58_IN_MASK 0x00000100
|
|
#define GPIO58_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO58_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO58_INT_TYPE_OFFSET 4
|
|
#define GPIO58_INT_TYPE_MASK 0x00000070
|
|
#define GPIO58_INT_RAW_OFFSET 3
|
|
#define GPIO58_INT_RAW_MASK 0x00000008
|
|
#define GPIO58_INT_STS_OFFSET 2
|
|
#define GPIO58_INT_STS_MASK 0x00000004
|
|
#define GPIO58_INT_ENA_OFFSET 1
|
|
#define GPIO58_INT_ENA_MASK 0x00000002
|
|
#define GPIO58_CLR_OFFSET 0
|
|
#define GPIO58_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO59_CFG_ADDR 0x2ec
|
|
#define GPIO59_OD_MODE_OFFSET 12
|
|
#define GPIO59_OD_MODE_MASK 0x00003000
|
|
#define GPIO59_OUT_OFFSET 11
|
|
#define GPIO59_OUT_MASK 0x00000800
|
|
#define GPIO59_OE_OFFSET 10
|
|
#define GPIO59_OE_MASK 0x00000400
|
|
#define GPIO59_IE_OFFSET 9
|
|
#define GPIO59_IE_MASK 0x00000200
|
|
#define GPIO59_IN_OFFSET 8
|
|
#define GPIO59_IN_MASK 0x00000100
|
|
#define GPIO59_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO59_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO59_INT_TYPE_OFFSET 4
|
|
#define GPIO59_INT_TYPE_MASK 0x00000070
|
|
#define GPIO59_INT_RAW_OFFSET 3
|
|
#define GPIO59_INT_RAW_MASK 0x00000008
|
|
#define GPIO59_INT_STS_OFFSET 2
|
|
#define GPIO59_INT_STS_MASK 0x00000004
|
|
#define GPIO59_INT_ENA_OFFSET 1
|
|
#define GPIO59_INT_ENA_MASK 0x00000002
|
|
#define GPIO59_CLR_OFFSET 0
|
|
#define GPIO59_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO60_CFG_ADDR 0x2f0
|
|
#define GPIO60_OD_MODE_OFFSET 12
|
|
#define GPIO60_OD_MODE_MASK 0x00003000
|
|
#define GPIO60_OUT_OFFSET 11
|
|
#define GPIO60_OUT_MASK 0x00000800
|
|
#define GPIO60_OE_OFFSET 10
|
|
#define GPIO60_OE_MASK 0x00000400
|
|
#define GPIO60_IE_OFFSET 9
|
|
#define GPIO60_IE_MASK 0x00000200
|
|
#define GPIO60_IN_OFFSET 8
|
|
#define GPIO60_IN_MASK 0x00000100
|
|
#define GPIO60_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO60_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO60_INT_TYPE_OFFSET 4
|
|
#define GPIO60_INT_TYPE_MASK 0x00000070
|
|
#define GPIO60_INT_RAW_OFFSET 3
|
|
#define GPIO60_INT_RAW_MASK 0x00000008
|
|
#define GPIO60_INT_STS_OFFSET 2
|
|
#define GPIO60_INT_STS_MASK 0x00000004
|
|
#define GPIO60_INT_ENA_OFFSET 1
|
|
#define GPIO60_INT_ENA_MASK 0x00000002
|
|
#define GPIO60_CLR_OFFSET 0
|
|
#define GPIO60_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO61_CFG_ADDR 0x2f4
|
|
#define GPIO61_OD_MODE_OFFSET 12
|
|
#define GPIO61_OD_MODE_MASK 0x00003000
|
|
#define GPIO61_OUT_OFFSET 11
|
|
#define GPIO61_OUT_MASK 0x00000800
|
|
#define GPIO61_OE_OFFSET 10
|
|
#define GPIO61_OE_MASK 0x00000400
|
|
#define GPIO61_IE_OFFSET 9
|
|
#define GPIO61_IE_MASK 0x00000200
|
|
#define GPIO61_IN_OFFSET 8
|
|
#define GPIO61_IN_MASK 0x00000100
|
|
#define GPIO61_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO61_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO61_INT_TYPE_OFFSET 4
|
|
#define GPIO61_INT_TYPE_MASK 0x00000070
|
|
#define GPIO61_INT_RAW_OFFSET 3
|
|
#define GPIO61_INT_RAW_MASK 0x00000008
|
|
#define GPIO61_INT_STS_OFFSET 2
|
|
#define GPIO61_INT_STS_MASK 0x00000004
|
|
#define GPIO61_INT_ENA_OFFSET 1
|
|
#define GPIO61_INT_ENA_MASK 0x00000002
|
|
#define GPIO61_CLR_OFFSET 0
|
|
#define GPIO61_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO62_CFG_ADDR 0x2f8
|
|
#define GPIO62_OD_MODE_OFFSET 12
|
|
#define GPIO62_OD_MODE_MASK 0x00003000
|
|
#define GPIO62_OUT_OFFSET 11
|
|
#define GPIO62_OUT_MASK 0x00000800
|
|
#define GPIO62_OE_OFFSET 10
|
|
#define GPIO62_OE_MASK 0x00000400
|
|
#define GPIO62_IE_OFFSET 9
|
|
#define GPIO62_IE_MASK 0x00000200
|
|
#define GPIO62_IN_OFFSET 8
|
|
#define GPIO62_IN_MASK 0x00000100
|
|
#define GPIO62_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO62_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO62_INT_TYPE_OFFSET 4
|
|
#define GPIO62_INT_TYPE_MASK 0x00000070
|
|
#define GPIO62_INT_RAW_OFFSET 3
|
|
#define GPIO62_INT_RAW_MASK 0x00000008
|
|
#define GPIO62_INT_STS_OFFSET 2
|
|
#define GPIO62_INT_STS_MASK 0x00000004
|
|
#define GPIO62_INT_ENA_OFFSET 1
|
|
#define GPIO62_INT_ENA_MASK 0x00000002
|
|
#define GPIO62_CLR_OFFSET 0
|
|
#define GPIO62_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO63_CFG_ADDR 0x2fc
|
|
#define GPIO63_OD_MODE_OFFSET 12
|
|
#define GPIO63_OD_MODE_MASK 0x00003000
|
|
#define GPIO63_OUT_OFFSET 11
|
|
#define GPIO63_OUT_MASK 0x00000800
|
|
#define GPIO63_OE_OFFSET 10
|
|
#define GPIO63_OE_MASK 0x00000400
|
|
#define GPIO63_IE_OFFSET 9
|
|
#define GPIO63_IE_MASK 0x00000200
|
|
#define GPIO63_IN_OFFSET 8
|
|
#define GPIO63_IN_MASK 0x00000100
|
|
#define GPIO63_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO63_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO63_INT_TYPE_OFFSET 4
|
|
#define GPIO63_INT_TYPE_MASK 0x00000070
|
|
#define GPIO63_INT_RAW_OFFSET 3
|
|
#define GPIO63_INT_RAW_MASK 0x00000008
|
|
#define GPIO63_INT_STS_OFFSET 2
|
|
#define GPIO63_INT_STS_MASK 0x00000004
|
|
#define GPIO63_INT_ENA_OFFSET 1
|
|
#define GPIO63_INT_ENA_MASK 0x00000002
|
|
#define GPIO63_CLR_OFFSET 0
|
|
#define GPIO63_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO64_CFG_ADDR 0x300
|
|
#define GPIO64_OD_MODE_OFFSET 12
|
|
#define GPIO64_OD_MODE_MASK 0x00003000
|
|
#define GPIO64_OUT_OFFSET 11
|
|
#define GPIO64_OUT_MASK 0x00000800
|
|
#define GPIO64_OE_OFFSET 10
|
|
#define GPIO64_OE_MASK 0x00000400
|
|
#define GPIO64_IE_OFFSET 9
|
|
#define GPIO64_IE_MASK 0x00000200
|
|
#define GPIO64_IN_OFFSET 8
|
|
#define GPIO64_IN_MASK 0x00000100
|
|
#define GPIO64_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO64_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO64_INT_TYPE_OFFSET 4
|
|
#define GPIO64_INT_TYPE_MASK 0x00000070
|
|
#define GPIO64_INT_RAW_OFFSET 3
|
|
#define GPIO64_INT_RAW_MASK 0x00000008
|
|
#define GPIO64_INT_STS_OFFSET 2
|
|
#define GPIO64_INT_STS_MASK 0x00000004
|
|
#define GPIO64_INT_ENA_OFFSET 1
|
|
#define GPIO64_INT_ENA_MASK 0x00000002
|
|
#define GPIO64_CLR_OFFSET 0
|
|
#define GPIO64_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO65_CFG_ADDR 0x304
|
|
#define GPIO65_OD_MODE_OFFSET 12
|
|
#define GPIO65_OD_MODE_MASK 0x00003000
|
|
#define GPIO65_OUT_OFFSET 11
|
|
#define GPIO65_OUT_MASK 0x00000800
|
|
#define GPIO65_OE_OFFSET 10
|
|
#define GPIO65_OE_MASK 0x00000400
|
|
#define GPIO65_IE_OFFSET 9
|
|
#define GPIO65_IE_MASK 0x00000200
|
|
#define GPIO65_IN_OFFSET 8
|
|
#define GPIO65_IN_MASK 0x00000100
|
|
#define GPIO65_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO65_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO65_INT_TYPE_OFFSET 4
|
|
#define GPIO65_INT_TYPE_MASK 0x00000070
|
|
#define GPIO65_INT_RAW_OFFSET 3
|
|
#define GPIO65_INT_RAW_MASK 0x00000008
|
|
#define GPIO65_INT_STS_OFFSET 2
|
|
#define GPIO65_INT_STS_MASK 0x00000004
|
|
#define GPIO65_INT_ENA_OFFSET 1
|
|
#define GPIO65_INT_ENA_MASK 0x00000002
|
|
#define GPIO65_CLR_OFFSET 0
|
|
#define GPIO65_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO66_CFG_ADDR 0x308
|
|
#define GPIO66_OD_MODE_OFFSET 12
|
|
#define GPIO66_OD_MODE_MASK 0x00003000
|
|
#define GPIO66_OUT_OFFSET 11
|
|
#define GPIO66_OUT_MASK 0x00000800
|
|
#define GPIO66_OE_OFFSET 10
|
|
#define GPIO66_OE_MASK 0x00000400
|
|
#define GPIO66_IE_OFFSET 9
|
|
#define GPIO66_IE_MASK 0x00000200
|
|
#define GPIO66_IN_OFFSET 8
|
|
#define GPIO66_IN_MASK 0x00000100
|
|
#define GPIO66_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO66_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO66_INT_TYPE_OFFSET 4
|
|
#define GPIO66_INT_TYPE_MASK 0x00000070
|
|
#define GPIO66_INT_RAW_OFFSET 3
|
|
#define GPIO66_INT_RAW_MASK 0x00000008
|
|
#define GPIO66_INT_STS_OFFSET 2
|
|
#define GPIO66_INT_STS_MASK 0x00000004
|
|
#define GPIO66_INT_ENA_OFFSET 1
|
|
#define GPIO66_INT_ENA_MASK 0x00000002
|
|
#define GPIO66_CLR_OFFSET 0
|
|
#define GPIO66_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO67_CFG_ADDR 0x30c
|
|
#define GPIO67_OD_MODE_OFFSET 12
|
|
#define GPIO67_OD_MODE_MASK 0x00003000
|
|
#define GPIO67_OUT_OFFSET 11
|
|
#define GPIO67_OUT_MASK 0x00000800
|
|
#define GPIO67_OE_OFFSET 10
|
|
#define GPIO67_OE_MASK 0x00000400
|
|
#define GPIO67_IE_OFFSET 9
|
|
#define GPIO67_IE_MASK 0x00000200
|
|
#define GPIO67_IN_OFFSET 8
|
|
#define GPIO67_IN_MASK 0x00000100
|
|
#define GPIO67_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO67_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO67_INT_TYPE_OFFSET 4
|
|
#define GPIO67_INT_TYPE_MASK 0x00000070
|
|
#define GPIO67_INT_RAW_OFFSET 3
|
|
#define GPIO67_INT_RAW_MASK 0x00000008
|
|
#define GPIO67_INT_STS_OFFSET 2
|
|
#define GPIO67_INT_STS_MASK 0x00000004
|
|
#define GPIO67_INT_ENA_OFFSET 1
|
|
#define GPIO67_INT_ENA_MASK 0x00000002
|
|
#define GPIO67_CLR_OFFSET 0
|
|
#define GPIO67_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO68_CFG_ADDR 0x310
|
|
#define GPIO68_OD_MODE_OFFSET 12
|
|
#define GPIO68_OD_MODE_MASK 0x00003000
|
|
#define GPIO68_OUT_OFFSET 11
|
|
#define GPIO68_OUT_MASK 0x00000800
|
|
#define GPIO68_OE_OFFSET 10
|
|
#define GPIO68_OE_MASK 0x00000400
|
|
#define GPIO68_IE_OFFSET 9
|
|
#define GPIO68_IE_MASK 0x00000200
|
|
#define GPIO68_IN_OFFSET 8
|
|
#define GPIO68_IN_MASK 0x00000100
|
|
#define GPIO68_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO68_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO68_INT_TYPE_OFFSET 4
|
|
#define GPIO68_INT_TYPE_MASK 0x00000070
|
|
#define GPIO68_INT_RAW_OFFSET 3
|
|
#define GPIO68_INT_RAW_MASK 0x00000008
|
|
#define GPIO68_INT_STS_OFFSET 2
|
|
#define GPIO68_INT_STS_MASK 0x00000004
|
|
#define GPIO68_INT_ENA_OFFSET 1
|
|
#define GPIO68_INT_ENA_MASK 0x00000002
|
|
#define GPIO68_CLR_OFFSET 0
|
|
#define GPIO68_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO69_CFG_ADDR 0x314
|
|
#define GPIO69_OD_MODE_OFFSET 12
|
|
#define GPIO69_OD_MODE_MASK 0x00003000
|
|
#define GPIO69_OUT_OFFSET 11
|
|
#define GPIO69_OUT_MASK 0x00000800
|
|
#define GPIO69_OE_OFFSET 10
|
|
#define GPIO69_OE_MASK 0x00000400
|
|
#define GPIO69_IE_OFFSET 9
|
|
#define GPIO69_IE_MASK 0x00000200
|
|
#define GPIO69_IN_OFFSET 8
|
|
#define GPIO69_IN_MASK 0x00000100
|
|
#define GPIO69_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO69_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO69_INT_TYPE_OFFSET 4
|
|
#define GPIO69_INT_TYPE_MASK 0x00000070
|
|
#define GPIO69_INT_RAW_OFFSET 3
|
|
#define GPIO69_INT_RAW_MASK 0x00000008
|
|
#define GPIO69_INT_STS_OFFSET 2
|
|
#define GPIO69_INT_STS_MASK 0x00000004
|
|
#define GPIO69_INT_ENA_OFFSET 1
|
|
#define GPIO69_INT_ENA_MASK 0x00000002
|
|
#define GPIO69_CLR_OFFSET 0
|
|
#define GPIO69_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO70_CFG_ADDR 0x318
|
|
#define GPIO70_OD_MODE_OFFSET 12
|
|
#define GPIO70_OD_MODE_MASK 0x00003000
|
|
#define GPIO70_OUT_OFFSET 11
|
|
#define GPIO70_OUT_MASK 0x00000800
|
|
#define GPIO70_OE_OFFSET 10
|
|
#define GPIO70_OE_MASK 0x00000400
|
|
#define GPIO70_IE_OFFSET 9
|
|
#define GPIO70_IE_MASK 0x00000200
|
|
#define GPIO70_IN_OFFSET 8
|
|
#define GPIO70_IN_MASK 0x00000100
|
|
#define GPIO70_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO70_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO70_INT_TYPE_OFFSET 4
|
|
#define GPIO70_INT_TYPE_MASK 0x00000070
|
|
#define GPIO70_INT_RAW_OFFSET 3
|
|
#define GPIO70_INT_RAW_MASK 0x00000008
|
|
#define GPIO70_INT_STS_OFFSET 2
|
|
#define GPIO70_INT_STS_MASK 0x00000004
|
|
#define GPIO70_INT_ENA_OFFSET 1
|
|
#define GPIO70_INT_ENA_MASK 0x00000002
|
|
#define GPIO70_CLR_OFFSET 0
|
|
#define GPIO70_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO71_CFG_ADDR 0x31c
|
|
#define GPIO71_OD_MODE_OFFSET 12
|
|
#define GPIO71_OD_MODE_MASK 0x00003000
|
|
#define GPIO71_OUT_OFFSET 11
|
|
#define GPIO71_OUT_MASK 0x00000800
|
|
#define GPIO71_OE_OFFSET 10
|
|
#define GPIO71_OE_MASK 0x00000400
|
|
#define GPIO71_IE_OFFSET 9
|
|
#define GPIO71_IE_MASK 0x00000200
|
|
#define GPIO71_IN_OFFSET 8
|
|
#define GPIO71_IN_MASK 0x00000100
|
|
#define GPIO71_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO71_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO71_INT_TYPE_OFFSET 4
|
|
#define GPIO71_INT_TYPE_MASK 0x00000070
|
|
#define GPIO71_INT_RAW_OFFSET 3
|
|
#define GPIO71_INT_RAW_MASK 0x00000008
|
|
#define GPIO71_INT_STS_OFFSET 2
|
|
#define GPIO71_INT_STS_MASK 0x00000004
|
|
#define GPIO71_INT_ENA_OFFSET 1
|
|
#define GPIO71_INT_ENA_MASK 0x00000002
|
|
#define GPIO71_CLR_OFFSET 0
|
|
#define GPIO71_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO72_CFG_ADDR 0x320
|
|
#define GPIO72_OD_MODE_OFFSET 12
|
|
#define GPIO72_OD_MODE_MASK 0x00003000
|
|
#define GPIO72_OUT_OFFSET 11
|
|
#define GPIO72_OUT_MASK 0x00000800
|
|
#define GPIO72_OE_OFFSET 10
|
|
#define GPIO72_OE_MASK 0x00000400
|
|
#define GPIO72_IE_OFFSET 9
|
|
#define GPIO72_IE_MASK 0x00000200
|
|
#define GPIO72_IN_OFFSET 8
|
|
#define GPIO72_IN_MASK 0x00000100
|
|
#define GPIO72_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO72_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO72_INT_TYPE_OFFSET 4
|
|
#define GPIO72_INT_TYPE_MASK 0x00000070
|
|
#define GPIO72_INT_RAW_OFFSET 3
|
|
#define GPIO72_INT_RAW_MASK 0x00000008
|
|
#define GPIO72_INT_STS_OFFSET 2
|
|
#define GPIO72_INT_STS_MASK 0x00000004
|
|
#define GPIO72_INT_ENA_OFFSET 1
|
|
#define GPIO72_INT_ENA_MASK 0x00000002
|
|
#define GPIO72_CLR_OFFSET 0
|
|
#define GPIO72_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO73_CFG_ADDR 0x324
|
|
#define GPIO73_OD_MODE_OFFSET 12
|
|
#define GPIO73_OD_MODE_MASK 0x00003000
|
|
#define GPIO73_OUT_OFFSET 11
|
|
#define GPIO73_OUT_MASK 0x00000800
|
|
#define GPIO73_OE_OFFSET 10
|
|
#define GPIO73_OE_MASK 0x00000400
|
|
#define GPIO73_IE_OFFSET 9
|
|
#define GPIO73_IE_MASK 0x00000200
|
|
#define GPIO73_IN_OFFSET 8
|
|
#define GPIO73_IN_MASK 0x00000100
|
|
#define GPIO73_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO73_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO73_INT_TYPE_OFFSET 4
|
|
#define GPIO73_INT_TYPE_MASK 0x00000070
|
|
#define GPIO73_INT_RAW_OFFSET 3
|
|
#define GPIO73_INT_RAW_MASK 0x00000008
|
|
#define GPIO73_INT_STS_OFFSET 2
|
|
#define GPIO73_INT_STS_MASK 0x00000004
|
|
#define GPIO73_INT_ENA_OFFSET 1
|
|
#define GPIO73_INT_ENA_MASK 0x00000002
|
|
#define GPIO73_CLR_OFFSET 0
|
|
#define GPIO73_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO74_CFG_ADDR 0x328
|
|
#define GPIO74_OD_MODE_OFFSET 12
|
|
#define GPIO74_OD_MODE_MASK 0x00003000
|
|
#define GPIO74_OUT_OFFSET 11
|
|
#define GPIO74_OUT_MASK 0x00000800
|
|
#define GPIO74_OE_OFFSET 10
|
|
#define GPIO74_OE_MASK 0x00000400
|
|
#define GPIO74_IE_OFFSET 9
|
|
#define GPIO74_IE_MASK 0x00000200
|
|
#define GPIO74_IN_OFFSET 8
|
|
#define GPIO74_IN_MASK 0x00000100
|
|
#define GPIO74_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO74_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO74_INT_TYPE_OFFSET 4
|
|
#define GPIO74_INT_TYPE_MASK 0x00000070
|
|
#define GPIO74_INT_RAW_OFFSET 3
|
|
#define GPIO74_INT_RAW_MASK 0x00000008
|
|
#define GPIO74_INT_STS_OFFSET 2
|
|
#define GPIO74_INT_STS_MASK 0x00000004
|
|
#define GPIO74_INT_ENA_OFFSET 1
|
|
#define GPIO74_INT_ENA_MASK 0x00000002
|
|
#define GPIO74_CLR_OFFSET 0
|
|
#define GPIO74_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO75_CFG_ADDR 0x32c
|
|
#define GPIO75_OD_MODE_OFFSET 12
|
|
#define GPIO75_OD_MODE_MASK 0x00003000
|
|
#define GPIO75_OUT_OFFSET 11
|
|
#define GPIO75_OUT_MASK 0x00000800
|
|
#define GPIO75_OE_OFFSET 10
|
|
#define GPIO75_OE_MASK 0x00000400
|
|
#define GPIO75_IE_OFFSET 9
|
|
#define GPIO75_IE_MASK 0x00000200
|
|
#define GPIO75_IN_OFFSET 8
|
|
#define GPIO75_IN_MASK 0x00000100
|
|
#define GPIO75_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO75_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO75_INT_TYPE_OFFSET 4
|
|
#define GPIO75_INT_TYPE_MASK 0x00000070
|
|
#define GPIO75_INT_RAW_OFFSET 3
|
|
#define GPIO75_INT_RAW_MASK 0x00000008
|
|
#define GPIO75_INT_STS_OFFSET 2
|
|
#define GPIO75_INT_STS_MASK 0x00000004
|
|
#define GPIO75_INT_ENA_OFFSET 1
|
|
#define GPIO75_INT_ENA_MASK 0x00000002
|
|
#define GPIO75_CLR_OFFSET 0
|
|
#define GPIO75_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO76_CFG_ADDR 0x330
|
|
#define GPIO76_OD_MODE_OFFSET 12
|
|
#define GPIO76_OD_MODE_MASK 0x00003000
|
|
#define GPIO76_OUT_OFFSET 11
|
|
#define GPIO76_OUT_MASK 0x00000800
|
|
#define GPIO76_OE_OFFSET 10
|
|
#define GPIO76_OE_MASK 0x00000400
|
|
#define GPIO76_IE_OFFSET 9
|
|
#define GPIO76_IE_MASK 0x00000200
|
|
#define GPIO76_IN_OFFSET 8
|
|
#define GPIO76_IN_MASK 0x00000100
|
|
#define GPIO76_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO76_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO76_INT_TYPE_OFFSET 4
|
|
#define GPIO76_INT_TYPE_MASK 0x00000070
|
|
#define GPIO76_INT_RAW_OFFSET 3
|
|
#define GPIO76_INT_RAW_MASK 0x00000008
|
|
#define GPIO76_INT_STS_OFFSET 2
|
|
#define GPIO76_INT_STS_MASK 0x00000004
|
|
#define GPIO76_INT_ENA_OFFSET 1
|
|
#define GPIO76_INT_ENA_MASK 0x00000002
|
|
#define GPIO76_CLR_OFFSET 0
|
|
#define GPIO76_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO77_CFG_ADDR 0x334
|
|
#define GPIO77_OD_MODE_OFFSET 12
|
|
#define GPIO77_OD_MODE_MASK 0x00003000
|
|
#define GPIO77_OUT_OFFSET 11
|
|
#define GPIO77_OUT_MASK 0x00000800
|
|
#define GPIO77_OE_OFFSET 10
|
|
#define GPIO77_OE_MASK 0x00000400
|
|
#define GPIO77_IE_OFFSET 9
|
|
#define GPIO77_IE_MASK 0x00000200
|
|
#define GPIO77_IN_OFFSET 8
|
|
#define GPIO77_IN_MASK 0x00000100
|
|
#define GPIO77_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO77_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO77_INT_TYPE_OFFSET 4
|
|
#define GPIO77_INT_TYPE_MASK 0x00000070
|
|
#define GPIO77_INT_RAW_OFFSET 3
|
|
#define GPIO77_INT_RAW_MASK 0x00000008
|
|
#define GPIO77_INT_STS_OFFSET 2
|
|
#define GPIO77_INT_STS_MASK 0x00000004
|
|
#define GPIO77_INT_ENA_OFFSET 1
|
|
#define GPIO77_INT_ENA_MASK 0x00000002
|
|
#define GPIO77_CLR_OFFSET 0
|
|
#define GPIO77_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO78_CFG_ADDR 0x338
|
|
#define GPIO78_OD_MODE_OFFSET 12
|
|
#define GPIO78_OD_MODE_MASK 0x00003000
|
|
#define GPIO78_OUT_OFFSET 11
|
|
#define GPIO78_OUT_MASK 0x00000800
|
|
#define GPIO78_OE_OFFSET 10
|
|
#define GPIO78_OE_MASK 0x00000400
|
|
#define GPIO78_IE_OFFSET 9
|
|
#define GPIO78_IE_MASK 0x00000200
|
|
#define GPIO78_IN_OFFSET 8
|
|
#define GPIO78_IN_MASK 0x00000100
|
|
#define GPIO78_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO78_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO78_INT_TYPE_OFFSET 4
|
|
#define GPIO78_INT_TYPE_MASK 0x00000070
|
|
#define GPIO78_INT_RAW_OFFSET 3
|
|
#define GPIO78_INT_RAW_MASK 0x00000008
|
|
#define GPIO78_INT_STS_OFFSET 2
|
|
#define GPIO78_INT_STS_MASK 0x00000004
|
|
#define GPIO78_INT_ENA_OFFSET 1
|
|
#define GPIO78_INT_ENA_MASK 0x00000002
|
|
#define GPIO78_CLR_OFFSET 0
|
|
#define GPIO78_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO79_CFG_ADDR 0x33c
|
|
#define GPIO79_OD_MODE_OFFSET 12
|
|
#define GPIO79_OD_MODE_MASK 0x00003000
|
|
#define GPIO79_OUT_OFFSET 11
|
|
#define GPIO79_OUT_MASK 0x00000800
|
|
#define GPIO79_OE_OFFSET 10
|
|
#define GPIO79_OE_MASK 0x00000400
|
|
#define GPIO79_IE_OFFSET 9
|
|
#define GPIO79_IE_MASK 0x00000200
|
|
#define GPIO79_IN_OFFSET 8
|
|
#define GPIO79_IN_MASK 0x00000100
|
|
#define GPIO79_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO79_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO79_INT_TYPE_OFFSET 4
|
|
#define GPIO79_INT_TYPE_MASK 0x00000070
|
|
#define GPIO79_INT_RAW_OFFSET 3
|
|
#define GPIO79_INT_RAW_MASK 0x00000008
|
|
#define GPIO79_INT_STS_OFFSET 2
|
|
#define GPIO79_INT_STS_MASK 0x00000004
|
|
#define GPIO79_INT_ENA_OFFSET 1
|
|
#define GPIO79_INT_ENA_MASK 0x00000002
|
|
#define GPIO79_CLR_OFFSET 0
|
|
#define GPIO79_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO80_CFG_ADDR 0x340
|
|
#define GPIO80_OD_MODE_OFFSET 12
|
|
#define GPIO80_OD_MODE_MASK 0x00003000
|
|
#define GPIO80_OUT_OFFSET 11
|
|
#define GPIO80_OUT_MASK 0x00000800
|
|
#define GPIO80_OE_OFFSET 10
|
|
#define GPIO80_OE_MASK 0x00000400
|
|
#define GPIO80_IE_OFFSET 9
|
|
#define GPIO80_IE_MASK 0x00000200
|
|
#define GPIO80_IN_OFFSET 8
|
|
#define GPIO80_IN_MASK 0x00000100
|
|
#define GPIO80_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO80_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO80_INT_TYPE_OFFSET 4
|
|
#define GPIO80_INT_TYPE_MASK 0x00000070
|
|
#define GPIO80_INT_RAW_OFFSET 3
|
|
#define GPIO80_INT_RAW_MASK 0x00000008
|
|
#define GPIO80_INT_STS_OFFSET 2
|
|
#define GPIO80_INT_STS_MASK 0x00000004
|
|
#define GPIO80_INT_ENA_OFFSET 1
|
|
#define GPIO80_INT_ENA_MASK 0x00000002
|
|
#define GPIO80_CLR_OFFSET 0
|
|
#define GPIO80_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO81_CFG_ADDR 0x344
|
|
#define GPIO81_OD_MODE_OFFSET 12
|
|
#define GPIO81_OD_MODE_MASK 0x00003000
|
|
#define GPIO81_OUT_OFFSET 11
|
|
#define GPIO81_OUT_MASK 0x00000800
|
|
#define GPIO81_OE_OFFSET 10
|
|
#define GPIO81_OE_MASK 0x00000400
|
|
#define GPIO81_IE_OFFSET 9
|
|
#define GPIO81_IE_MASK 0x00000200
|
|
#define GPIO81_IN_OFFSET 8
|
|
#define GPIO81_IN_MASK 0x00000100
|
|
#define GPIO81_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO81_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO81_INT_TYPE_OFFSET 4
|
|
#define GPIO81_INT_TYPE_MASK 0x00000070
|
|
#define GPIO81_INT_RAW_OFFSET 3
|
|
#define GPIO81_INT_RAW_MASK 0x00000008
|
|
#define GPIO81_INT_STS_OFFSET 2
|
|
#define GPIO81_INT_STS_MASK 0x00000004
|
|
#define GPIO81_INT_ENA_OFFSET 1
|
|
#define GPIO81_INT_ENA_MASK 0x00000002
|
|
#define GPIO81_CLR_OFFSET 0
|
|
#define GPIO81_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO82_CFG_ADDR 0x348
|
|
#define GPIO82_OD_MODE_OFFSET 12
|
|
#define GPIO82_OD_MODE_MASK 0x00003000
|
|
#define GPIO82_OUT_OFFSET 11
|
|
#define GPIO82_OUT_MASK 0x00000800
|
|
#define GPIO82_OE_OFFSET 10
|
|
#define GPIO82_OE_MASK 0x00000400
|
|
#define GPIO82_IE_OFFSET 9
|
|
#define GPIO82_IE_MASK 0x00000200
|
|
#define GPIO82_IN_OFFSET 8
|
|
#define GPIO82_IN_MASK 0x00000100
|
|
#define GPIO82_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO82_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO82_INT_TYPE_OFFSET 4
|
|
#define GPIO82_INT_TYPE_MASK 0x00000070
|
|
#define GPIO82_INT_RAW_OFFSET 3
|
|
#define GPIO82_INT_RAW_MASK 0x00000008
|
|
#define GPIO82_INT_STS_OFFSET 2
|
|
#define GPIO82_INT_STS_MASK 0x00000004
|
|
#define GPIO82_INT_ENA_OFFSET 1
|
|
#define GPIO82_INT_ENA_MASK 0x00000002
|
|
#define GPIO82_CLR_OFFSET 0
|
|
#define GPIO82_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO83_CFG_ADDR 0x34c
|
|
#define GPIO83_OD_MODE_OFFSET 12
|
|
#define GPIO83_OD_MODE_MASK 0x00003000
|
|
#define GPIO83_OUT_OFFSET 11
|
|
#define GPIO83_OUT_MASK 0x00000800
|
|
#define GPIO83_OE_OFFSET 10
|
|
#define GPIO83_OE_MASK 0x00000400
|
|
#define GPIO83_IE_OFFSET 9
|
|
#define GPIO83_IE_MASK 0x00000200
|
|
#define GPIO83_IN_OFFSET 8
|
|
#define GPIO83_IN_MASK 0x00000100
|
|
#define GPIO83_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO83_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO83_INT_TYPE_OFFSET 4
|
|
#define GPIO83_INT_TYPE_MASK 0x00000070
|
|
#define GPIO83_INT_RAW_OFFSET 3
|
|
#define GPIO83_INT_RAW_MASK 0x00000008
|
|
#define GPIO83_INT_STS_OFFSET 2
|
|
#define GPIO83_INT_STS_MASK 0x00000004
|
|
#define GPIO83_INT_ENA_OFFSET 1
|
|
#define GPIO83_INT_ENA_MASK 0x00000002
|
|
#define GPIO83_CLR_OFFSET 0
|
|
#define GPIO83_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO84_CFG_ADDR 0x350
|
|
#define GPIO84_OD_MODE_OFFSET 12
|
|
#define GPIO84_OD_MODE_MASK 0x00003000
|
|
#define GPIO84_OUT_OFFSET 11
|
|
#define GPIO84_OUT_MASK 0x00000800
|
|
#define GPIO84_OE_OFFSET 10
|
|
#define GPIO84_OE_MASK 0x00000400
|
|
#define GPIO84_IE_OFFSET 9
|
|
#define GPIO84_IE_MASK 0x00000200
|
|
#define GPIO84_IN_OFFSET 8
|
|
#define GPIO84_IN_MASK 0x00000100
|
|
#define GPIO84_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO84_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO84_INT_TYPE_OFFSET 4
|
|
#define GPIO84_INT_TYPE_MASK 0x00000070
|
|
#define GPIO84_INT_RAW_OFFSET 3
|
|
#define GPIO84_INT_RAW_MASK 0x00000008
|
|
#define GPIO84_INT_STS_OFFSET 2
|
|
#define GPIO84_INT_STS_MASK 0x00000004
|
|
#define GPIO84_INT_ENA_OFFSET 1
|
|
#define GPIO84_INT_ENA_MASK 0x00000002
|
|
#define GPIO84_CLR_OFFSET 0
|
|
#define GPIO84_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO85_CFG_ADDR 0x354
|
|
#define GPIO85_OD_MODE_OFFSET 12
|
|
#define GPIO85_OD_MODE_MASK 0x00003000
|
|
#define GPIO85_OUT_OFFSET 11
|
|
#define GPIO85_OUT_MASK 0x00000800
|
|
#define GPIO85_OE_OFFSET 10
|
|
#define GPIO85_OE_MASK 0x00000400
|
|
#define GPIO85_IE_OFFSET 9
|
|
#define GPIO85_IE_MASK 0x00000200
|
|
#define GPIO85_IN_OFFSET 8
|
|
#define GPIO85_IN_MASK 0x00000100
|
|
#define GPIO85_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO85_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO85_INT_TYPE_OFFSET 4
|
|
#define GPIO85_INT_TYPE_MASK 0x00000070
|
|
#define GPIO85_INT_RAW_OFFSET 3
|
|
#define GPIO85_INT_RAW_MASK 0x00000008
|
|
#define GPIO85_INT_STS_OFFSET 2
|
|
#define GPIO85_INT_STS_MASK 0x00000004
|
|
#define GPIO85_INT_ENA_OFFSET 1
|
|
#define GPIO85_INT_ENA_MASK 0x00000002
|
|
#define GPIO85_CLR_OFFSET 0
|
|
#define GPIO85_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO86_CFG_ADDR 0x358
|
|
#define GPIO86_OD_MODE_OFFSET 12
|
|
#define GPIO86_OD_MODE_MASK 0x00003000
|
|
#define GPIO86_OUT_OFFSET 11
|
|
#define GPIO86_OUT_MASK 0x00000800
|
|
#define GPIO86_OE_OFFSET 10
|
|
#define GPIO86_OE_MASK 0x00000400
|
|
#define GPIO86_IE_OFFSET 9
|
|
#define GPIO86_IE_MASK 0x00000200
|
|
#define GPIO86_IN_OFFSET 8
|
|
#define GPIO86_IN_MASK 0x00000100
|
|
#define GPIO86_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO86_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO86_INT_TYPE_OFFSET 4
|
|
#define GPIO86_INT_TYPE_MASK 0x00000070
|
|
#define GPIO86_INT_RAW_OFFSET 3
|
|
#define GPIO86_INT_RAW_MASK 0x00000008
|
|
#define GPIO86_INT_STS_OFFSET 2
|
|
#define GPIO86_INT_STS_MASK 0x00000004
|
|
#define GPIO86_INT_ENA_OFFSET 1
|
|
#define GPIO86_INT_ENA_MASK 0x00000002
|
|
#define GPIO86_CLR_OFFSET 0
|
|
#define GPIO86_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO87_CFG_ADDR 0x35c
|
|
#define GPIO87_OD_MODE_OFFSET 12
|
|
#define GPIO87_OD_MODE_MASK 0x00003000
|
|
#define GPIO87_OUT_OFFSET 11
|
|
#define GPIO87_OUT_MASK 0x00000800
|
|
#define GPIO87_OE_OFFSET 10
|
|
#define GPIO87_OE_MASK 0x00000400
|
|
#define GPIO87_IE_OFFSET 9
|
|
#define GPIO87_IE_MASK 0x00000200
|
|
#define GPIO87_IN_OFFSET 8
|
|
#define GPIO87_IN_MASK 0x00000100
|
|
#define GPIO87_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO87_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO87_INT_TYPE_OFFSET 4
|
|
#define GPIO87_INT_TYPE_MASK 0x00000070
|
|
#define GPIO87_INT_RAW_OFFSET 3
|
|
#define GPIO87_INT_RAW_MASK 0x00000008
|
|
#define GPIO87_INT_STS_OFFSET 2
|
|
#define GPIO87_INT_STS_MASK 0x00000004
|
|
#define GPIO87_INT_ENA_OFFSET 1
|
|
#define GPIO87_INT_ENA_MASK 0x00000002
|
|
#define GPIO87_CLR_OFFSET 0
|
|
#define GPIO87_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO88_CFG_ADDR 0x360
|
|
#define GPIO88_OD_MODE_OFFSET 12
|
|
#define GPIO88_OD_MODE_MASK 0x00003000
|
|
#define GPIO88_OUT_OFFSET 11
|
|
#define GPIO88_OUT_MASK 0x00000800
|
|
#define GPIO88_OE_OFFSET 10
|
|
#define GPIO88_OE_MASK 0x00000400
|
|
#define GPIO88_IE_OFFSET 9
|
|
#define GPIO88_IE_MASK 0x00000200
|
|
#define GPIO88_IN_OFFSET 8
|
|
#define GPIO88_IN_MASK 0x00000100
|
|
#define GPIO88_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO88_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO88_INT_TYPE_OFFSET 4
|
|
#define GPIO88_INT_TYPE_MASK 0x00000070
|
|
#define GPIO88_INT_RAW_OFFSET 3
|
|
#define GPIO88_INT_RAW_MASK 0x00000008
|
|
#define GPIO88_INT_STS_OFFSET 2
|
|
#define GPIO88_INT_STS_MASK 0x00000004
|
|
#define GPIO88_INT_ENA_OFFSET 1
|
|
#define GPIO88_INT_ENA_MASK 0x00000002
|
|
#define GPIO88_CLR_OFFSET 0
|
|
#define GPIO88_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO89_CFG_ADDR 0x364
|
|
#define GPIO89_OD_MODE_OFFSET 12
|
|
#define GPIO89_OD_MODE_MASK 0x00003000
|
|
#define GPIO89_OUT_OFFSET 11
|
|
#define GPIO89_OUT_MASK 0x00000800
|
|
#define GPIO89_OE_OFFSET 10
|
|
#define GPIO89_OE_MASK 0x00000400
|
|
#define GPIO89_IE_OFFSET 9
|
|
#define GPIO89_IE_MASK 0x00000200
|
|
#define GPIO89_IN_OFFSET 8
|
|
#define GPIO89_IN_MASK 0x00000100
|
|
#define GPIO89_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO89_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO89_INT_TYPE_OFFSET 4
|
|
#define GPIO89_INT_TYPE_MASK 0x00000070
|
|
#define GPIO89_INT_RAW_OFFSET 3
|
|
#define GPIO89_INT_RAW_MASK 0x00000008
|
|
#define GPIO89_INT_STS_OFFSET 2
|
|
#define GPIO89_INT_STS_MASK 0x00000004
|
|
#define GPIO89_INT_ENA_OFFSET 1
|
|
#define GPIO89_INT_ENA_MASK 0x00000002
|
|
#define GPIO89_CLR_OFFSET 0
|
|
#define GPIO89_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO90_CFG_ADDR 0x368
|
|
#define GPIO90_OD_MODE_OFFSET 12
|
|
#define GPIO90_OD_MODE_MASK 0x00003000
|
|
#define GPIO90_OUT_OFFSET 11
|
|
#define GPIO90_OUT_MASK 0x00000800
|
|
#define GPIO90_OE_OFFSET 10
|
|
#define GPIO90_OE_MASK 0x00000400
|
|
#define GPIO90_IE_OFFSET 9
|
|
#define GPIO90_IE_MASK 0x00000200
|
|
#define GPIO90_IN_OFFSET 8
|
|
#define GPIO90_IN_MASK 0x00000100
|
|
#define GPIO90_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO90_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO90_INT_TYPE_OFFSET 4
|
|
#define GPIO90_INT_TYPE_MASK 0x00000070
|
|
#define GPIO90_INT_RAW_OFFSET 3
|
|
#define GPIO90_INT_RAW_MASK 0x00000008
|
|
#define GPIO90_INT_STS_OFFSET 2
|
|
#define GPIO90_INT_STS_MASK 0x00000004
|
|
#define GPIO90_INT_ENA_OFFSET 1
|
|
#define GPIO90_INT_ENA_MASK 0x00000002
|
|
#define GPIO90_CLR_OFFSET 0
|
|
#define GPIO90_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO91_CFG_ADDR 0x36c
|
|
#define GPIO91_OD_MODE_OFFSET 12
|
|
#define GPIO91_OD_MODE_MASK 0x00003000
|
|
#define GPIO91_OUT_OFFSET 11
|
|
#define GPIO91_OUT_MASK 0x00000800
|
|
#define GPIO91_OE_OFFSET 10
|
|
#define GPIO91_OE_MASK 0x00000400
|
|
#define GPIO91_IE_OFFSET 9
|
|
#define GPIO91_IE_MASK 0x00000200
|
|
#define GPIO91_IN_OFFSET 8
|
|
#define GPIO91_IN_MASK 0x00000100
|
|
#define GPIO91_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO91_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO91_INT_TYPE_OFFSET 4
|
|
#define GPIO91_INT_TYPE_MASK 0x00000070
|
|
#define GPIO91_INT_RAW_OFFSET 3
|
|
#define GPIO91_INT_RAW_MASK 0x00000008
|
|
#define GPIO91_INT_STS_OFFSET 2
|
|
#define GPIO91_INT_STS_MASK 0x00000004
|
|
#define GPIO91_INT_ENA_OFFSET 1
|
|
#define GPIO91_INT_ENA_MASK 0x00000002
|
|
#define GPIO91_CLR_OFFSET 0
|
|
#define GPIO91_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO92_CFG_ADDR 0x370
|
|
#define GPIO92_OD_MODE_OFFSET 12
|
|
#define GPIO92_OD_MODE_MASK 0x00003000
|
|
#define GPIO92_OUT_OFFSET 11
|
|
#define GPIO92_OUT_MASK 0x00000800
|
|
#define GPIO92_OE_OFFSET 10
|
|
#define GPIO92_OE_MASK 0x00000400
|
|
#define GPIO92_IE_OFFSET 9
|
|
#define GPIO92_IE_MASK 0x00000200
|
|
#define GPIO92_IN_OFFSET 8
|
|
#define GPIO92_IN_MASK 0x00000100
|
|
#define GPIO92_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO92_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO92_INT_TYPE_OFFSET 4
|
|
#define GPIO92_INT_TYPE_MASK 0x00000070
|
|
#define GPIO92_INT_RAW_OFFSET 3
|
|
#define GPIO92_INT_RAW_MASK 0x00000008
|
|
#define GPIO92_INT_STS_OFFSET 2
|
|
#define GPIO92_INT_STS_MASK 0x00000004
|
|
#define GPIO92_INT_ENA_OFFSET 1
|
|
#define GPIO92_INT_ENA_MASK 0x00000002
|
|
#define GPIO92_CLR_OFFSET 0
|
|
#define GPIO92_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO93_CFG_ADDR 0x374
|
|
#define GPIO93_OD_MODE_OFFSET 12
|
|
#define GPIO93_OD_MODE_MASK 0x00003000
|
|
#define GPIO93_OUT_OFFSET 11
|
|
#define GPIO93_OUT_MASK 0x00000800
|
|
#define GPIO93_OE_OFFSET 10
|
|
#define GPIO93_OE_MASK 0x00000400
|
|
#define GPIO93_IE_OFFSET 9
|
|
#define GPIO93_IE_MASK 0x00000200
|
|
#define GPIO93_IN_OFFSET 8
|
|
#define GPIO93_IN_MASK 0x00000100
|
|
#define GPIO93_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO93_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO93_INT_TYPE_OFFSET 4
|
|
#define GPIO93_INT_TYPE_MASK 0x00000070
|
|
#define GPIO93_INT_RAW_OFFSET 3
|
|
#define GPIO93_INT_RAW_MASK 0x00000008
|
|
#define GPIO93_INT_STS_OFFSET 2
|
|
#define GPIO93_INT_STS_MASK 0x00000004
|
|
#define GPIO93_INT_ENA_OFFSET 1
|
|
#define GPIO93_INT_ENA_MASK 0x00000002
|
|
#define GPIO93_CLR_OFFSET 0
|
|
#define GPIO93_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO94_CFG_ADDR 0x378
|
|
#define GPIO94_OD_MODE_OFFSET 12
|
|
#define GPIO94_OD_MODE_MASK 0x00003000
|
|
#define GPIO94_OUT_OFFSET 11
|
|
#define GPIO94_OUT_MASK 0x00000800
|
|
#define GPIO94_OE_OFFSET 10
|
|
#define GPIO94_OE_MASK 0x00000400
|
|
#define GPIO94_IE_OFFSET 9
|
|
#define GPIO94_IE_MASK 0x00000200
|
|
#define GPIO94_IN_OFFSET 8
|
|
#define GPIO94_IN_MASK 0x00000100
|
|
#define GPIO94_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO94_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO94_INT_TYPE_OFFSET 4
|
|
#define GPIO94_INT_TYPE_MASK 0x00000070
|
|
#define GPIO94_INT_RAW_OFFSET 3
|
|
#define GPIO94_INT_RAW_MASK 0x00000008
|
|
#define GPIO94_INT_STS_OFFSET 2
|
|
#define GPIO94_INT_STS_MASK 0x00000004
|
|
#define GPIO94_INT_ENA_OFFSET 1
|
|
#define GPIO94_INT_ENA_MASK 0x00000002
|
|
#define GPIO94_CLR_OFFSET 0
|
|
#define GPIO94_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO95_CFG_ADDR 0x37c
|
|
#define GPIO95_OD_MODE_OFFSET 12
|
|
#define GPIO95_OD_MODE_MASK 0x00003000
|
|
#define GPIO95_OUT_OFFSET 11
|
|
#define GPIO95_OUT_MASK 0x00000800
|
|
#define GPIO95_OE_OFFSET 10
|
|
#define GPIO95_OE_MASK 0x00000400
|
|
#define GPIO95_IE_OFFSET 9
|
|
#define GPIO95_IE_MASK 0x00000200
|
|
#define GPIO95_IN_OFFSET 8
|
|
#define GPIO95_IN_MASK 0x00000100
|
|
#define GPIO95_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO95_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO95_INT_TYPE_OFFSET 4
|
|
#define GPIO95_INT_TYPE_MASK 0x00000070
|
|
#define GPIO95_INT_RAW_OFFSET 3
|
|
#define GPIO95_INT_RAW_MASK 0x00000008
|
|
#define GPIO95_INT_STS_OFFSET 2
|
|
#define GPIO95_INT_STS_MASK 0x00000004
|
|
#define GPIO95_INT_ENA_OFFSET 1
|
|
#define GPIO95_INT_ENA_MASK 0x00000002
|
|
#define GPIO95_CLR_OFFSET 0
|
|
#define GPIO95_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO96_CFG_ADDR 0x380
|
|
#define GPIO96_OD_MODE_OFFSET 12
|
|
#define GPIO96_OD_MODE_MASK 0x00003000
|
|
#define GPIO96_OUT_OFFSET 11
|
|
#define GPIO96_OUT_MASK 0x00000800
|
|
#define GPIO96_OE_OFFSET 10
|
|
#define GPIO96_OE_MASK 0x00000400
|
|
#define GPIO96_IE_OFFSET 9
|
|
#define GPIO96_IE_MASK 0x00000200
|
|
#define GPIO96_IN_OFFSET 8
|
|
#define GPIO96_IN_MASK 0x00000100
|
|
#define GPIO96_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO96_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO96_INT_TYPE_OFFSET 4
|
|
#define GPIO96_INT_TYPE_MASK 0x00000070
|
|
#define GPIO96_INT_RAW_OFFSET 3
|
|
#define GPIO96_INT_RAW_MASK 0x00000008
|
|
#define GPIO96_INT_STS_OFFSET 2
|
|
#define GPIO96_INT_STS_MASK 0x00000004
|
|
#define GPIO96_INT_ENA_OFFSET 1
|
|
#define GPIO96_INT_ENA_MASK 0x00000002
|
|
#define GPIO96_CLR_OFFSET 0
|
|
#define GPIO96_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO97_CFG_ADDR 0x384
|
|
#define GPIO97_OD_MODE_OFFSET 12
|
|
#define GPIO97_OD_MODE_MASK 0x00003000
|
|
#define GPIO97_OUT_OFFSET 11
|
|
#define GPIO97_OUT_MASK 0x00000800
|
|
#define GPIO97_OE_OFFSET 10
|
|
#define GPIO97_OE_MASK 0x00000400
|
|
#define GPIO97_IE_OFFSET 9
|
|
#define GPIO97_IE_MASK 0x00000200
|
|
#define GPIO97_IN_OFFSET 8
|
|
#define GPIO97_IN_MASK 0x00000100
|
|
#define GPIO97_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO97_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO97_INT_TYPE_OFFSET 4
|
|
#define GPIO97_INT_TYPE_MASK 0x00000070
|
|
#define GPIO97_INT_RAW_OFFSET 3
|
|
#define GPIO97_INT_RAW_MASK 0x00000008
|
|
#define GPIO97_INT_STS_OFFSET 2
|
|
#define GPIO97_INT_STS_MASK 0x00000004
|
|
#define GPIO97_INT_ENA_OFFSET 1
|
|
#define GPIO97_INT_ENA_MASK 0x00000002
|
|
#define GPIO97_CLR_OFFSET 0
|
|
#define GPIO97_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO98_CFG_ADDR 0x388
|
|
#define GPIO98_OD_MODE_OFFSET 12
|
|
#define GPIO98_OD_MODE_MASK 0x00003000
|
|
#define GPIO98_OUT_OFFSET 11
|
|
#define GPIO98_OUT_MASK 0x00000800
|
|
#define GPIO98_OE_OFFSET 10
|
|
#define GPIO98_OE_MASK 0x00000400
|
|
#define GPIO98_IE_OFFSET 9
|
|
#define GPIO98_IE_MASK 0x00000200
|
|
#define GPIO98_IN_OFFSET 8
|
|
#define GPIO98_IN_MASK 0x00000100
|
|
#define GPIO98_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO98_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO98_INT_TYPE_OFFSET 4
|
|
#define GPIO98_INT_TYPE_MASK 0x00000070
|
|
#define GPIO98_INT_RAW_OFFSET 3
|
|
#define GPIO98_INT_RAW_MASK 0x00000008
|
|
#define GPIO98_INT_STS_OFFSET 2
|
|
#define GPIO98_INT_STS_MASK 0x00000004
|
|
#define GPIO98_INT_ENA_OFFSET 1
|
|
#define GPIO98_INT_ENA_MASK 0x00000002
|
|
#define GPIO98_CLR_OFFSET 0
|
|
#define GPIO98_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO99_CFG_ADDR 0x38c
|
|
#define GPIO99_OD_MODE_OFFSET 12
|
|
#define GPIO99_OD_MODE_MASK 0x00003000
|
|
#define GPIO99_OUT_OFFSET 11
|
|
#define GPIO99_OUT_MASK 0x00000800
|
|
#define GPIO99_OE_OFFSET 10
|
|
#define GPIO99_OE_MASK 0x00000400
|
|
#define GPIO99_IE_OFFSET 9
|
|
#define GPIO99_IE_MASK 0x00000200
|
|
#define GPIO99_IN_OFFSET 8
|
|
#define GPIO99_IN_MASK 0x00000100
|
|
#define GPIO99_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO99_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO99_INT_TYPE_OFFSET 4
|
|
#define GPIO99_INT_TYPE_MASK 0x00000070
|
|
#define GPIO99_INT_RAW_OFFSET 3
|
|
#define GPIO99_INT_RAW_MASK 0x00000008
|
|
#define GPIO99_INT_STS_OFFSET 2
|
|
#define GPIO99_INT_STS_MASK 0x00000004
|
|
#define GPIO99_INT_ENA_OFFSET 1
|
|
#define GPIO99_INT_ENA_MASK 0x00000002
|
|
#define GPIO99_CLR_OFFSET 0
|
|
#define GPIO99_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO100_CFG_ADDR 0x390
|
|
#define GPIO100_OD_MODE_OFFSET 12
|
|
#define GPIO100_OD_MODE_MASK 0x00003000
|
|
#define GPIO100_OUT_OFFSET 11
|
|
#define GPIO100_OUT_MASK 0x00000800
|
|
#define GPIO100_OE_OFFSET 10
|
|
#define GPIO100_OE_MASK 0x00000400
|
|
#define GPIO100_IE_OFFSET 9
|
|
#define GPIO100_IE_MASK 0x00000200
|
|
#define GPIO100_IN_OFFSET 8
|
|
#define GPIO100_IN_MASK 0x00000100
|
|
#define GPIO100_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO100_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO100_INT_TYPE_OFFSET 4
|
|
#define GPIO100_INT_TYPE_MASK 0x00000070
|
|
#define GPIO100_INT_RAW_OFFSET 3
|
|
#define GPIO100_INT_RAW_MASK 0x00000008
|
|
#define GPIO100_INT_STS_OFFSET 2
|
|
#define GPIO100_INT_STS_MASK 0x00000004
|
|
#define GPIO100_INT_ENA_OFFSET 1
|
|
#define GPIO100_INT_ENA_MASK 0x00000002
|
|
#define GPIO100_CLR_OFFSET 0
|
|
#define GPIO100_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO101_CFG_ADDR 0x394
|
|
#define GPIO101_OD_MODE_OFFSET 12
|
|
#define GPIO101_OD_MODE_MASK 0x00003000
|
|
#define GPIO101_OUT_OFFSET 11
|
|
#define GPIO101_OUT_MASK 0x00000800
|
|
#define GPIO101_OE_OFFSET 10
|
|
#define GPIO101_OE_MASK 0x00000400
|
|
#define GPIO101_IE_OFFSET 9
|
|
#define GPIO101_IE_MASK 0x00000200
|
|
#define GPIO101_IN_OFFSET 8
|
|
#define GPIO101_IN_MASK 0x00000100
|
|
#define GPIO101_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO101_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO101_INT_TYPE_OFFSET 4
|
|
#define GPIO101_INT_TYPE_MASK 0x00000070
|
|
#define GPIO101_INT_RAW_OFFSET 3
|
|
#define GPIO101_INT_RAW_MASK 0x00000008
|
|
#define GPIO101_INT_STS_OFFSET 2
|
|
#define GPIO101_INT_STS_MASK 0x00000004
|
|
#define GPIO101_INT_ENA_OFFSET 1
|
|
#define GPIO101_INT_ENA_MASK 0x00000002
|
|
#define GPIO101_CLR_OFFSET 0
|
|
#define GPIO101_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO102_CFG_ADDR 0x398
|
|
#define GPIO102_OD_MODE_OFFSET 12
|
|
#define GPIO102_OD_MODE_MASK 0x00003000
|
|
#define GPIO102_OUT_OFFSET 11
|
|
#define GPIO102_OUT_MASK 0x00000800
|
|
#define GPIO102_OE_OFFSET 10
|
|
#define GPIO102_OE_MASK 0x00000400
|
|
#define GPIO102_IE_OFFSET 9
|
|
#define GPIO102_IE_MASK 0x00000200
|
|
#define GPIO102_IN_OFFSET 8
|
|
#define GPIO102_IN_MASK 0x00000100
|
|
#define GPIO102_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO102_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO102_INT_TYPE_OFFSET 4
|
|
#define GPIO102_INT_TYPE_MASK 0x00000070
|
|
#define GPIO102_INT_RAW_OFFSET 3
|
|
#define GPIO102_INT_RAW_MASK 0x00000008
|
|
#define GPIO102_INT_STS_OFFSET 2
|
|
#define GPIO102_INT_STS_MASK 0x00000004
|
|
#define GPIO102_INT_ENA_OFFSET 1
|
|
#define GPIO102_INT_ENA_MASK 0x00000002
|
|
#define GPIO102_CLR_OFFSET 0
|
|
#define GPIO102_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO103_CFG_ADDR 0x39c
|
|
#define GPIO103_OD_MODE_OFFSET 12
|
|
#define GPIO103_OD_MODE_MASK 0x00003000
|
|
#define GPIO103_OUT_OFFSET 11
|
|
#define GPIO103_OUT_MASK 0x00000800
|
|
#define GPIO103_OE_OFFSET 10
|
|
#define GPIO103_OE_MASK 0x00000400
|
|
#define GPIO103_IE_OFFSET 9
|
|
#define GPIO103_IE_MASK 0x00000200
|
|
#define GPIO103_IN_OFFSET 8
|
|
#define GPIO103_IN_MASK 0x00000100
|
|
#define GPIO103_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO103_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO103_INT_TYPE_OFFSET 4
|
|
#define GPIO103_INT_TYPE_MASK 0x00000070
|
|
#define GPIO103_INT_RAW_OFFSET 3
|
|
#define GPIO103_INT_RAW_MASK 0x00000008
|
|
#define GPIO103_INT_STS_OFFSET 2
|
|
#define GPIO103_INT_STS_MASK 0x00000004
|
|
#define GPIO103_INT_ENA_OFFSET 1
|
|
#define GPIO103_INT_ENA_MASK 0x00000002
|
|
#define GPIO103_CLR_OFFSET 0
|
|
#define GPIO103_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO104_CFG_ADDR 0x3a0
|
|
#define GPIO104_OD_MODE_OFFSET 12
|
|
#define GPIO104_OD_MODE_MASK 0x00003000
|
|
#define GPIO104_OUT_OFFSET 11
|
|
#define GPIO104_OUT_MASK 0x00000800
|
|
#define GPIO104_OE_OFFSET 10
|
|
#define GPIO104_OE_MASK 0x00000400
|
|
#define GPIO104_IE_OFFSET 9
|
|
#define GPIO104_IE_MASK 0x00000200
|
|
#define GPIO104_IN_OFFSET 8
|
|
#define GPIO104_IN_MASK 0x00000100
|
|
#define GPIO104_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO104_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO104_INT_TYPE_OFFSET 4
|
|
#define GPIO104_INT_TYPE_MASK 0x00000070
|
|
#define GPIO104_INT_RAW_OFFSET 3
|
|
#define GPIO104_INT_RAW_MASK 0x00000008
|
|
#define GPIO104_INT_STS_OFFSET 2
|
|
#define GPIO104_INT_STS_MASK 0x00000004
|
|
#define GPIO104_INT_ENA_OFFSET 1
|
|
#define GPIO104_INT_ENA_MASK 0x00000002
|
|
#define GPIO104_CLR_OFFSET 0
|
|
#define GPIO104_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO105_CFG_ADDR 0x3a4
|
|
#define GPIO105_OD_MODE_OFFSET 12
|
|
#define GPIO105_OD_MODE_MASK 0x00003000
|
|
#define GPIO105_OUT_OFFSET 11
|
|
#define GPIO105_OUT_MASK 0x00000800
|
|
#define GPIO105_OE_OFFSET 10
|
|
#define GPIO105_OE_MASK 0x00000400
|
|
#define GPIO105_IE_OFFSET 9
|
|
#define GPIO105_IE_MASK 0x00000200
|
|
#define GPIO105_IN_OFFSET 8
|
|
#define GPIO105_IN_MASK 0x00000100
|
|
#define GPIO105_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO105_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO105_INT_TYPE_OFFSET 4
|
|
#define GPIO105_INT_TYPE_MASK 0x00000070
|
|
#define GPIO105_INT_RAW_OFFSET 3
|
|
#define GPIO105_INT_RAW_MASK 0x00000008
|
|
#define GPIO105_INT_STS_OFFSET 2
|
|
#define GPIO105_INT_STS_MASK 0x00000004
|
|
#define GPIO105_INT_ENA_OFFSET 1
|
|
#define GPIO105_INT_ENA_MASK 0x00000002
|
|
#define GPIO105_CLR_OFFSET 0
|
|
#define GPIO105_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO106_CFG_ADDR 0x3a8
|
|
#define GPIO106_OD_MODE_OFFSET 12
|
|
#define GPIO106_OD_MODE_MASK 0x00003000
|
|
#define GPIO106_OUT_OFFSET 11
|
|
#define GPIO106_OUT_MASK 0x00000800
|
|
#define GPIO106_OE_OFFSET 10
|
|
#define GPIO106_OE_MASK 0x00000400
|
|
#define GPIO106_IE_OFFSET 9
|
|
#define GPIO106_IE_MASK 0x00000200
|
|
#define GPIO106_IN_OFFSET 8
|
|
#define GPIO106_IN_MASK 0x00000100
|
|
#define GPIO106_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO106_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO106_INT_TYPE_OFFSET 4
|
|
#define GPIO106_INT_TYPE_MASK 0x00000070
|
|
#define GPIO106_INT_RAW_OFFSET 3
|
|
#define GPIO106_INT_RAW_MASK 0x00000008
|
|
#define GPIO106_INT_STS_OFFSET 2
|
|
#define GPIO106_INT_STS_MASK 0x00000004
|
|
#define GPIO106_INT_ENA_OFFSET 1
|
|
#define GPIO106_INT_ENA_MASK 0x00000002
|
|
#define GPIO106_CLR_OFFSET 0
|
|
#define GPIO106_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO107_CFG_ADDR 0x3ac
|
|
#define GPIO107_OD_MODE_OFFSET 12
|
|
#define GPIO107_OD_MODE_MASK 0x00003000
|
|
#define GPIO107_OUT_OFFSET 11
|
|
#define GPIO107_OUT_MASK 0x00000800
|
|
#define GPIO107_OE_OFFSET 10
|
|
#define GPIO107_OE_MASK 0x00000400
|
|
#define GPIO107_IE_OFFSET 9
|
|
#define GPIO107_IE_MASK 0x00000200
|
|
#define GPIO107_IN_OFFSET 8
|
|
#define GPIO107_IN_MASK 0x00000100
|
|
#define GPIO107_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO107_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO107_INT_TYPE_OFFSET 4
|
|
#define GPIO107_INT_TYPE_MASK 0x00000070
|
|
#define GPIO107_INT_RAW_OFFSET 3
|
|
#define GPIO107_INT_RAW_MASK 0x00000008
|
|
#define GPIO107_INT_STS_OFFSET 2
|
|
#define GPIO107_INT_STS_MASK 0x00000004
|
|
#define GPIO107_INT_ENA_OFFSET 1
|
|
#define GPIO107_INT_ENA_MASK 0x00000002
|
|
#define GPIO107_CLR_OFFSET 0
|
|
#define GPIO107_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO108_CFG_ADDR 0x3b0
|
|
#define GPIO108_OD_MODE_OFFSET 12
|
|
#define GPIO108_OD_MODE_MASK 0x00003000
|
|
#define GPIO108_OUT_OFFSET 11
|
|
#define GPIO108_OUT_MASK 0x00000800
|
|
#define GPIO108_OE_OFFSET 10
|
|
#define GPIO108_OE_MASK 0x00000400
|
|
#define GPIO108_IE_OFFSET 9
|
|
#define GPIO108_IE_MASK 0x00000200
|
|
#define GPIO108_IN_OFFSET 8
|
|
#define GPIO108_IN_MASK 0x00000100
|
|
#define GPIO108_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO108_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO108_INT_TYPE_OFFSET 4
|
|
#define GPIO108_INT_TYPE_MASK 0x00000070
|
|
#define GPIO108_INT_RAW_OFFSET 3
|
|
#define GPIO108_INT_RAW_MASK 0x00000008
|
|
#define GPIO108_INT_STS_OFFSET 2
|
|
#define GPIO108_INT_STS_MASK 0x00000004
|
|
#define GPIO108_INT_ENA_OFFSET 1
|
|
#define GPIO108_INT_ENA_MASK 0x00000002
|
|
#define GPIO108_CLR_OFFSET 0
|
|
#define GPIO108_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO109_CFG_ADDR 0x3b4
|
|
#define GPIO109_OD_MODE_OFFSET 12
|
|
#define GPIO109_OD_MODE_MASK 0x00003000
|
|
#define GPIO109_OUT_OFFSET 11
|
|
#define GPIO109_OUT_MASK 0x00000800
|
|
#define GPIO109_OE_OFFSET 10
|
|
#define GPIO109_OE_MASK 0x00000400
|
|
#define GPIO109_IE_OFFSET 9
|
|
#define GPIO109_IE_MASK 0x00000200
|
|
#define GPIO109_IN_OFFSET 8
|
|
#define GPIO109_IN_MASK 0x00000100
|
|
#define GPIO109_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO109_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO109_INT_TYPE_OFFSET 4
|
|
#define GPIO109_INT_TYPE_MASK 0x00000070
|
|
#define GPIO109_INT_RAW_OFFSET 3
|
|
#define GPIO109_INT_RAW_MASK 0x00000008
|
|
#define GPIO109_INT_STS_OFFSET 2
|
|
#define GPIO109_INT_STS_MASK 0x00000004
|
|
#define GPIO109_INT_ENA_OFFSET 1
|
|
#define GPIO109_INT_ENA_MASK 0x00000002
|
|
#define GPIO109_CLR_OFFSET 0
|
|
#define GPIO109_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO110_CFG_ADDR 0x3b8
|
|
#define GPIO110_OD_MODE_OFFSET 12
|
|
#define GPIO110_OD_MODE_MASK 0x00003000
|
|
#define GPIO110_OUT_OFFSET 11
|
|
#define GPIO110_OUT_MASK 0x00000800
|
|
#define GPIO110_OE_OFFSET 10
|
|
#define GPIO110_OE_MASK 0x00000400
|
|
#define GPIO110_IE_OFFSET 9
|
|
#define GPIO110_IE_MASK 0x00000200
|
|
#define GPIO110_IN_OFFSET 8
|
|
#define GPIO110_IN_MASK 0x00000100
|
|
#define GPIO110_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO110_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO110_INT_TYPE_OFFSET 4
|
|
#define GPIO110_INT_TYPE_MASK 0x00000070
|
|
#define GPIO110_INT_RAW_OFFSET 3
|
|
#define GPIO110_INT_RAW_MASK 0x00000008
|
|
#define GPIO110_INT_STS_OFFSET 2
|
|
#define GPIO110_INT_STS_MASK 0x00000004
|
|
#define GPIO110_INT_ENA_OFFSET 1
|
|
#define GPIO110_INT_ENA_MASK 0x00000002
|
|
#define GPIO110_CLR_OFFSET 0
|
|
#define GPIO110_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO111_CFG_ADDR 0x3bc
|
|
#define GPIO111_OD_MODE_OFFSET 12
|
|
#define GPIO111_OD_MODE_MASK 0x00003000
|
|
#define GPIO111_OUT_OFFSET 11
|
|
#define GPIO111_OUT_MASK 0x00000800
|
|
#define GPIO111_OE_OFFSET 10
|
|
#define GPIO111_OE_MASK 0x00000400
|
|
#define GPIO111_IE_OFFSET 9
|
|
#define GPIO111_IE_MASK 0x00000200
|
|
#define GPIO111_IN_OFFSET 8
|
|
#define GPIO111_IN_MASK 0x00000100
|
|
#define GPIO111_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO111_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO111_INT_TYPE_OFFSET 4
|
|
#define GPIO111_INT_TYPE_MASK 0x00000070
|
|
#define GPIO111_INT_RAW_OFFSET 3
|
|
#define GPIO111_INT_RAW_MASK 0x00000008
|
|
#define GPIO111_INT_STS_OFFSET 2
|
|
#define GPIO111_INT_STS_MASK 0x00000004
|
|
#define GPIO111_INT_ENA_OFFSET 1
|
|
#define GPIO111_INT_ENA_MASK 0x00000002
|
|
#define GPIO111_CLR_OFFSET 0
|
|
#define GPIO111_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO112_CFG_ADDR 0x3c0
|
|
#define GPIO112_OD_MODE_OFFSET 12
|
|
#define GPIO112_OD_MODE_MASK 0x00003000
|
|
#define GPIO112_OUT_OFFSET 11
|
|
#define GPIO112_OUT_MASK 0x00000800
|
|
#define GPIO112_OE_OFFSET 10
|
|
#define GPIO112_OE_MASK 0x00000400
|
|
#define GPIO112_IE_OFFSET 9
|
|
#define GPIO112_IE_MASK 0x00000200
|
|
#define GPIO112_IN_OFFSET 8
|
|
#define GPIO112_IN_MASK 0x00000100
|
|
#define GPIO112_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO112_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO112_INT_TYPE_OFFSET 4
|
|
#define GPIO112_INT_TYPE_MASK 0x00000070
|
|
#define GPIO112_INT_RAW_OFFSET 3
|
|
#define GPIO112_INT_RAW_MASK 0x00000008
|
|
#define GPIO112_INT_STS_OFFSET 2
|
|
#define GPIO112_INT_STS_MASK 0x00000004
|
|
#define GPIO112_INT_ENA_OFFSET 1
|
|
#define GPIO112_INT_ENA_MASK 0x00000002
|
|
#define GPIO112_CLR_OFFSET 0
|
|
#define GPIO112_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO113_CFG_ADDR 0x3c4
|
|
#define GPIO113_OD_MODE_OFFSET 12
|
|
#define GPIO113_OD_MODE_MASK 0x00003000
|
|
#define GPIO113_OUT_OFFSET 11
|
|
#define GPIO113_OUT_MASK 0x00000800
|
|
#define GPIO113_OE_OFFSET 10
|
|
#define GPIO113_OE_MASK 0x00000400
|
|
#define GPIO113_IE_OFFSET 9
|
|
#define GPIO113_IE_MASK 0x00000200
|
|
#define GPIO113_IN_OFFSET 8
|
|
#define GPIO113_IN_MASK 0x00000100
|
|
#define GPIO113_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO113_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO113_INT_TYPE_OFFSET 4
|
|
#define GPIO113_INT_TYPE_MASK 0x00000070
|
|
#define GPIO113_INT_RAW_OFFSET 3
|
|
#define GPIO113_INT_RAW_MASK 0x00000008
|
|
#define GPIO113_INT_STS_OFFSET 2
|
|
#define GPIO113_INT_STS_MASK 0x00000004
|
|
#define GPIO113_INT_ENA_OFFSET 1
|
|
#define GPIO113_INT_ENA_MASK 0x00000002
|
|
#define GPIO113_CLR_OFFSET 0
|
|
#define GPIO113_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO114_CFG_ADDR 0x3c8
|
|
#define GPIO114_OD_MODE_OFFSET 12
|
|
#define GPIO114_OD_MODE_MASK 0x00003000
|
|
#define GPIO114_OUT_OFFSET 11
|
|
#define GPIO114_OUT_MASK 0x00000800
|
|
#define GPIO114_OE_OFFSET 10
|
|
#define GPIO114_OE_MASK 0x00000400
|
|
#define GPIO114_IE_OFFSET 9
|
|
#define GPIO114_IE_MASK 0x00000200
|
|
#define GPIO114_IN_OFFSET 8
|
|
#define GPIO114_IN_MASK 0x00000100
|
|
#define GPIO114_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO114_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO114_INT_TYPE_OFFSET 4
|
|
#define GPIO114_INT_TYPE_MASK 0x00000070
|
|
#define GPIO114_INT_RAW_OFFSET 3
|
|
#define GPIO114_INT_RAW_MASK 0x00000008
|
|
#define GPIO114_INT_STS_OFFSET 2
|
|
#define GPIO114_INT_STS_MASK 0x00000004
|
|
#define GPIO114_INT_ENA_OFFSET 1
|
|
#define GPIO114_INT_ENA_MASK 0x00000002
|
|
#define GPIO114_CLR_OFFSET 0
|
|
#define GPIO114_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO115_CFG_ADDR 0x3cc
|
|
#define GPIO115_OD_MODE_OFFSET 12
|
|
#define GPIO115_OD_MODE_MASK 0x00003000
|
|
#define GPIO115_OUT_OFFSET 11
|
|
#define GPIO115_OUT_MASK 0x00000800
|
|
#define GPIO115_OE_OFFSET 10
|
|
#define GPIO115_OE_MASK 0x00000400
|
|
#define GPIO115_IE_OFFSET 9
|
|
#define GPIO115_IE_MASK 0x00000200
|
|
#define GPIO115_IN_OFFSET 8
|
|
#define GPIO115_IN_MASK 0x00000100
|
|
#define GPIO115_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO115_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO115_INT_TYPE_OFFSET 4
|
|
#define GPIO115_INT_TYPE_MASK 0x00000070
|
|
#define GPIO115_INT_RAW_OFFSET 3
|
|
#define GPIO115_INT_RAW_MASK 0x00000008
|
|
#define GPIO115_INT_STS_OFFSET 2
|
|
#define GPIO115_INT_STS_MASK 0x00000004
|
|
#define GPIO115_INT_ENA_OFFSET 1
|
|
#define GPIO115_INT_ENA_MASK 0x00000002
|
|
#define GPIO115_CLR_OFFSET 0
|
|
#define GPIO115_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO116_CFG_ADDR 0x3d0
|
|
#define GPIO116_OD_MODE_OFFSET 12
|
|
#define GPIO116_OD_MODE_MASK 0x00003000
|
|
#define GPIO116_OUT_OFFSET 11
|
|
#define GPIO116_OUT_MASK 0x00000800
|
|
#define GPIO116_OE_OFFSET 10
|
|
#define GPIO116_OE_MASK 0x00000400
|
|
#define GPIO116_IE_OFFSET 9
|
|
#define GPIO116_IE_MASK 0x00000200
|
|
#define GPIO116_IN_OFFSET 8
|
|
#define GPIO116_IN_MASK 0x00000100
|
|
#define GPIO116_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO116_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO116_INT_TYPE_OFFSET 4
|
|
#define GPIO116_INT_TYPE_MASK 0x00000070
|
|
#define GPIO116_INT_RAW_OFFSET 3
|
|
#define GPIO116_INT_RAW_MASK 0x00000008
|
|
#define GPIO116_INT_STS_OFFSET 2
|
|
#define GPIO116_INT_STS_MASK 0x00000004
|
|
#define GPIO116_INT_ENA_OFFSET 1
|
|
#define GPIO116_INT_ENA_MASK 0x00000002
|
|
#define GPIO116_CLR_OFFSET 0
|
|
#define GPIO116_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO117_CFG_ADDR 0x3d4
|
|
#define GPIO117_OD_MODE_OFFSET 12
|
|
#define GPIO117_OD_MODE_MASK 0x00003000
|
|
#define GPIO117_OUT_OFFSET 11
|
|
#define GPIO117_OUT_MASK 0x00000800
|
|
#define GPIO117_OE_OFFSET 10
|
|
#define GPIO117_OE_MASK 0x00000400
|
|
#define GPIO117_IE_OFFSET 9
|
|
#define GPIO117_IE_MASK 0x00000200
|
|
#define GPIO117_IN_OFFSET 8
|
|
#define GPIO117_IN_MASK 0x00000100
|
|
#define GPIO117_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO117_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO117_INT_TYPE_OFFSET 4
|
|
#define GPIO117_INT_TYPE_MASK 0x00000070
|
|
#define GPIO117_INT_RAW_OFFSET 3
|
|
#define GPIO117_INT_RAW_MASK 0x00000008
|
|
#define GPIO117_INT_STS_OFFSET 2
|
|
#define GPIO117_INT_STS_MASK 0x00000004
|
|
#define GPIO117_INT_ENA_OFFSET 1
|
|
#define GPIO117_INT_ENA_MASK 0x00000002
|
|
#define GPIO117_CLR_OFFSET 0
|
|
#define GPIO117_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO118_CFG_ADDR 0x3d8
|
|
#define GPIO118_OD_MODE_OFFSET 12
|
|
#define GPIO118_OD_MODE_MASK 0x00003000
|
|
#define GPIO118_OUT_OFFSET 11
|
|
#define GPIO118_OUT_MASK 0x00000800
|
|
#define GPIO118_OE_OFFSET 10
|
|
#define GPIO118_OE_MASK 0x00000400
|
|
#define GPIO118_IE_OFFSET 9
|
|
#define GPIO118_IE_MASK 0x00000200
|
|
#define GPIO118_IN_OFFSET 8
|
|
#define GPIO118_IN_MASK 0x00000100
|
|
#define GPIO118_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO118_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO118_INT_TYPE_OFFSET 4
|
|
#define GPIO118_INT_TYPE_MASK 0x00000070
|
|
#define GPIO118_INT_RAW_OFFSET 3
|
|
#define GPIO118_INT_RAW_MASK 0x00000008
|
|
#define GPIO118_INT_STS_OFFSET 2
|
|
#define GPIO118_INT_STS_MASK 0x00000004
|
|
#define GPIO118_INT_ENA_OFFSET 1
|
|
#define GPIO118_INT_ENA_MASK 0x00000002
|
|
#define GPIO118_CLR_OFFSET 0
|
|
#define GPIO118_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO119_CFG_ADDR 0x3dc
|
|
#define GPIO119_OD_MODE_OFFSET 12
|
|
#define GPIO119_OD_MODE_MASK 0x00003000
|
|
#define GPIO119_OUT_OFFSET 11
|
|
#define GPIO119_OUT_MASK 0x00000800
|
|
#define GPIO119_OE_OFFSET 10
|
|
#define GPIO119_OE_MASK 0x00000400
|
|
#define GPIO119_IE_OFFSET 9
|
|
#define GPIO119_IE_MASK 0x00000200
|
|
#define GPIO119_IN_OFFSET 8
|
|
#define GPIO119_IN_MASK 0x00000100
|
|
#define GPIO119_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO119_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO119_INT_TYPE_OFFSET 4
|
|
#define GPIO119_INT_TYPE_MASK 0x00000070
|
|
#define GPIO119_INT_RAW_OFFSET 3
|
|
#define GPIO119_INT_RAW_MASK 0x00000008
|
|
#define GPIO119_INT_STS_OFFSET 2
|
|
#define GPIO119_INT_STS_MASK 0x00000004
|
|
#define GPIO119_INT_ENA_OFFSET 1
|
|
#define GPIO119_INT_ENA_MASK 0x00000002
|
|
#define GPIO119_CLR_OFFSET 0
|
|
#define GPIO119_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO120_CFG_ADDR 0x3e0
|
|
#define GPIO120_OD_MODE_OFFSET 12
|
|
#define GPIO120_OD_MODE_MASK 0x00003000
|
|
#define GPIO120_OUT_OFFSET 11
|
|
#define GPIO120_OUT_MASK 0x00000800
|
|
#define GPIO120_OE_OFFSET 10
|
|
#define GPIO120_OE_MASK 0x00000400
|
|
#define GPIO120_IE_OFFSET 9
|
|
#define GPIO120_IE_MASK 0x00000200
|
|
#define GPIO120_IN_OFFSET 8
|
|
#define GPIO120_IN_MASK 0x00000100
|
|
#define GPIO120_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO120_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO120_INT_TYPE_OFFSET 4
|
|
#define GPIO120_INT_TYPE_MASK 0x00000070
|
|
#define GPIO120_INT_RAW_OFFSET 3
|
|
#define GPIO120_INT_RAW_MASK 0x00000008
|
|
#define GPIO120_INT_STS_OFFSET 2
|
|
#define GPIO120_INT_STS_MASK 0x00000004
|
|
#define GPIO120_INT_ENA_OFFSET 1
|
|
#define GPIO120_INT_ENA_MASK 0x00000002
|
|
#define GPIO120_CLR_OFFSET 0
|
|
#define GPIO120_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO121_CFG_ADDR 0x3e4
|
|
#define GPIO121_OD_MODE_OFFSET 12
|
|
#define GPIO121_OD_MODE_MASK 0x00003000
|
|
#define GPIO121_OUT_OFFSET 11
|
|
#define GPIO121_OUT_MASK 0x00000800
|
|
#define GPIO121_OE_OFFSET 10
|
|
#define GPIO121_OE_MASK 0x00000400
|
|
#define GPIO121_IE_OFFSET 9
|
|
#define GPIO121_IE_MASK 0x00000200
|
|
#define GPIO121_IN_OFFSET 8
|
|
#define GPIO121_IN_MASK 0x00000100
|
|
#define GPIO121_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO121_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO121_INT_TYPE_OFFSET 4
|
|
#define GPIO121_INT_TYPE_MASK 0x00000070
|
|
#define GPIO121_INT_RAW_OFFSET 3
|
|
#define GPIO121_INT_RAW_MASK 0x00000008
|
|
#define GPIO121_INT_STS_OFFSET 2
|
|
#define GPIO121_INT_STS_MASK 0x00000004
|
|
#define GPIO121_INT_ENA_OFFSET 1
|
|
#define GPIO121_INT_ENA_MASK 0x00000002
|
|
#define GPIO121_CLR_OFFSET 0
|
|
#define GPIO121_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO122_CFG_ADDR 0x3e8
|
|
#define GPIO122_OD_MODE_OFFSET 12
|
|
#define GPIO122_OD_MODE_MASK 0x00003000
|
|
#define GPIO122_OUT_OFFSET 11
|
|
#define GPIO122_OUT_MASK 0x00000800
|
|
#define GPIO122_OE_OFFSET 10
|
|
#define GPIO122_OE_MASK 0x00000400
|
|
#define GPIO122_IE_OFFSET 9
|
|
#define GPIO122_IE_MASK 0x00000200
|
|
#define GPIO122_IN_OFFSET 8
|
|
#define GPIO122_IN_MASK 0x00000100
|
|
#define GPIO122_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO122_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO122_INT_TYPE_OFFSET 4
|
|
#define GPIO122_INT_TYPE_MASK 0x00000070
|
|
#define GPIO122_INT_RAW_OFFSET 3
|
|
#define GPIO122_INT_RAW_MASK 0x00000008
|
|
#define GPIO122_INT_STS_OFFSET 2
|
|
#define GPIO122_INT_STS_MASK 0x00000004
|
|
#define GPIO122_INT_ENA_OFFSET 1
|
|
#define GPIO122_INT_ENA_MASK 0x00000002
|
|
#define GPIO122_CLR_OFFSET 0
|
|
#define GPIO122_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO123_CFG_ADDR 0x3ec
|
|
#define GPIO123_OD_MODE_OFFSET 12
|
|
#define GPIO123_OD_MODE_MASK 0x00003000
|
|
#define GPIO123_OUT_OFFSET 11
|
|
#define GPIO123_OUT_MASK 0x00000800
|
|
#define GPIO123_OE_OFFSET 10
|
|
#define GPIO123_OE_MASK 0x00000400
|
|
#define GPIO123_IE_OFFSET 9
|
|
#define GPIO123_IE_MASK 0x00000200
|
|
#define GPIO123_IN_OFFSET 8
|
|
#define GPIO123_IN_MASK 0x00000100
|
|
#define GPIO123_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO123_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO123_INT_TYPE_OFFSET 4
|
|
#define GPIO123_INT_TYPE_MASK 0x00000070
|
|
#define GPIO123_INT_RAW_OFFSET 3
|
|
#define GPIO123_INT_RAW_MASK 0x00000008
|
|
#define GPIO123_INT_STS_OFFSET 2
|
|
#define GPIO123_INT_STS_MASK 0x00000004
|
|
#define GPIO123_INT_ENA_OFFSET 1
|
|
#define GPIO123_INT_ENA_MASK 0x00000002
|
|
#define GPIO123_CLR_OFFSET 0
|
|
#define GPIO123_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO124_CFG_ADDR 0x3f0
|
|
#define GPIO124_OD_MODE_OFFSET 12
|
|
#define GPIO124_OD_MODE_MASK 0x00003000
|
|
#define GPIO124_OUT_OFFSET 11
|
|
#define GPIO124_OUT_MASK 0x00000800
|
|
#define GPIO124_OE_OFFSET 10
|
|
#define GPIO124_OE_MASK 0x00000400
|
|
#define GPIO124_IE_OFFSET 9
|
|
#define GPIO124_IE_MASK 0x00000200
|
|
#define GPIO124_IN_OFFSET 8
|
|
#define GPIO124_IN_MASK 0x00000100
|
|
#define GPIO124_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO124_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO124_INT_TYPE_OFFSET 4
|
|
#define GPIO124_INT_TYPE_MASK 0x00000070
|
|
#define GPIO124_INT_RAW_OFFSET 3
|
|
#define GPIO124_INT_RAW_MASK 0x00000008
|
|
#define GPIO124_INT_STS_OFFSET 2
|
|
#define GPIO124_INT_STS_MASK 0x00000004
|
|
#define GPIO124_INT_ENA_OFFSET 1
|
|
#define GPIO124_INT_ENA_MASK 0x00000002
|
|
#define GPIO124_CLR_OFFSET 0
|
|
#define GPIO124_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO125_CFG_ADDR 0x3f4
|
|
#define GPIO125_OD_MODE_OFFSET 12
|
|
#define GPIO125_OD_MODE_MASK 0x00003000
|
|
#define GPIO125_OUT_OFFSET 11
|
|
#define GPIO125_OUT_MASK 0x00000800
|
|
#define GPIO125_OE_OFFSET 10
|
|
#define GPIO125_OE_MASK 0x00000400
|
|
#define GPIO125_IE_OFFSET 9
|
|
#define GPIO125_IE_MASK 0x00000200
|
|
#define GPIO125_IN_OFFSET 8
|
|
#define GPIO125_IN_MASK 0x00000100
|
|
#define GPIO125_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO125_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO125_INT_TYPE_OFFSET 4
|
|
#define GPIO125_INT_TYPE_MASK 0x00000070
|
|
#define GPIO125_INT_RAW_OFFSET 3
|
|
#define GPIO125_INT_RAW_MASK 0x00000008
|
|
#define GPIO125_INT_STS_OFFSET 2
|
|
#define GPIO125_INT_STS_MASK 0x00000004
|
|
#define GPIO125_INT_ENA_OFFSET 1
|
|
#define GPIO125_INT_ENA_MASK 0x00000002
|
|
#define GPIO125_CLR_OFFSET 0
|
|
#define GPIO125_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO126_CFG_ADDR 0x3f8
|
|
#define GPIO126_OD_MODE_OFFSET 12
|
|
#define GPIO126_OD_MODE_MASK 0x00003000
|
|
#define GPIO126_OUT_OFFSET 11
|
|
#define GPIO126_OUT_MASK 0x00000800
|
|
#define GPIO126_OE_OFFSET 10
|
|
#define GPIO126_OE_MASK 0x00000400
|
|
#define GPIO126_IE_OFFSET 9
|
|
#define GPIO126_IE_MASK 0x00000200
|
|
#define GPIO126_IN_OFFSET 8
|
|
#define GPIO126_IN_MASK 0x00000100
|
|
#define GPIO126_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO126_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO126_INT_TYPE_OFFSET 4
|
|
#define GPIO126_INT_TYPE_MASK 0x00000070
|
|
#define GPIO126_INT_RAW_OFFSET 3
|
|
#define GPIO126_INT_RAW_MASK 0x00000008
|
|
#define GPIO126_INT_STS_OFFSET 2
|
|
#define GPIO126_INT_STS_MASK 0x00000004
|
|
#define GPIO126_INT_ENA_OFFSET 1
|
|
#define GPIO126_INT_ENA_MASK 0x00000002
|
|
#define GPIO126_CLR_OFFSET 0
|
|
#define GPIO126_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO127_CFG_ADDR 0x3fc
|
|
#define GPIO127_OD_MODE_OFFSET 12
|
|
#define GPIO127_OD_MODE_MASK 0x00003000
|
|
#define GPIO127_OUT_OFFSET 11
|
|
#define GPIO127_OUT_MASK 0x00000800
|
|
#define GPIO127_OE_OFFSET 10
|
|
#define GPIO127_OE_MASK 0x00000400
|
|
#define GPIO127_IE_OFFSET 9
|
|
#define GPIO127_IE_MASK 0x00000200
|
|
#define GPIO127_IN_OFFSET 8
|
|
#define GPIO127_IN_MASK 0x00000100
|
|
#define GPIO127_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO127_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO127_INT_TYPE_OFFSET 4
|
|
#define GPIO127_INT_TYPE_MASK 0x00000070
|
|
#define GPIO127_INT_RAW_OFFSET 3
|
|
#define GPIO127_INT_RAW_MASK 0x00000008
|
|
#define GPIO127_INT_STS_OFFSET 2
|
|
#define GPIO127_INT_STS_MASK 0x00000004
|
|
#define GPIO127_INT_ENA_OFFSET 1
|
|
#define GPIO127_INT_ENA_MASK 0x00000002
|
|
#define GPIO127_CLR_OFFSET 0
|
|
#define GPIO127_CLR_MASK 0x00000001
|
|
|
|
//HW module read/write macro
|
|
#define GPIO_READ_REG(addr) SOC_READ_REG(GPIO_BASEADDR + addr)
|
|
#define GPIO_WRITE_REG(addr,value) SOC_WRITE_REG(GPIO_BASEADDR + addr,value)
|
|
|