386 lines
12 KiB
C
386 lines
12 KiB
C
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//-----------------------------------
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#define CFG_BB_CLOCK_CTRL_ADDR 0x0000
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#define SW_MEM_FORCE_ON_OFFSET 7
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#define SW_MEM_FORCE_ON_MASK 0x00000080
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#define SW_CLK_EN_TD_RX_OFFSET 6
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#define SW_CLK_EN_TD_RX_MASK 0x00000040
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#define SW_CLK_EN_TD_TX_OFFSET 5
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#define SW_CLK_EN_TD_TX_MASK 0x00000020
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#define SW_CLK_EN_FFT_OFFSET 4
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#define SW_CLK_EN_FFT_MASK 0x00000010
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#define SW_CLK_EN_RX_FEC_OFFSET 3
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#define SW_CLK_EN_RX_FEC_MASK 0x00000008
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#define SW_CLK_EN_TX_FEC_OFFSET 2
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#define SW_CLK_EN_TX_FEC_MASK 0x00000004
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#define SW_CLK_EN_TURBO_DEC_OFFSET 1
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#define SW_CLK_EN_TURBO_DEC_MASK 0x00000002
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#define SW_CLK_EN_TURBO_ENC_OFFSET 0
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#define SW_CLK_EN_TURBO_ENC_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RESET_CTRL_ADDR 0x0004
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#define SW_ARST_TD_RX_OFFSET 6
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#define SW_ARST_TD_RX_MASK 0x00000040
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#define SW_ARST_TD_TX_OFFSET 5
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#define SW_ARST_TD_TX_MASK 0x00000020
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#define SW_ARST_FFT_OFFSET 4
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#define SW_ARST_FFT_MASK 0x00000010
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#define SW_ARST_RX_FEC_OFFSET 3
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#define SW_ARST_RX_FEC_MASK 0x00000008
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#define SW_ARST_TX_FEC_OFFSET 2
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#define SW_ARST_TX_FEC_MASK 0x00000004
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#define SW_ARST_TURBO_DEC_OFFSET 1
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#define SW_ARST_TURBO_DEC_MASK 0x00000002
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#define SW_ARST_TURBO_ENC_OFFSET 0
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#define SW_ARST_TURBO_ENC_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RTL_VERSION_ADDR 0x0008
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#define BB_RTL_VERSION_OFFSET 0
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#define BB_RTL_VERSION_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_VERSION_ADDR 0x0010
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#define SW_BB_VERSION_OFFSET 0
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#define SW_BB_VERSION_MASK 0x00000007
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//-----------------------------------
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#define CFG_BB_PRE_CFG_ADDR 0x0014
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#define SW_TX_PRE_AMP_OFFSET 9
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#define SW_TX_PRE_AMP_MASK 0x00001E00
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#define SW_TX_PRE_NUM_OFFSET 5
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#define SW_TX_PRE_NUM_MASK 0x000001E0
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#define SW_PRE_REF_PHASE_OFFSET 2
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#define SW_PRE_REF_PHASE_MASK 0x0000001C
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#define SW_TX_PRE_MODE_OFFSET 0
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#define SW_TX_PRE_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_BB_PLD_CFG_ADDR 0x0018
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#define SW_RX_TURBO_SOFT_BIT_WIDTH_OFFSET 18
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#define SW_RX_TURBO_SOFT_BIT_WIDTH_MASK 0x000C0000
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#define SW_RX_TURBO_DEC_LOOP_OFFSET 16
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#define SW_RX_TURBO_DEC_LOOP_MASK 0x00030000
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#define SW_CI_HBS_DIR_OFFSET 8
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#define SW_CI_HBS_DIR_MASK 0x00000100
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#define SW_PLD_REF_PHASE_OFFSET 3
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#define SW_PLD_REF_PHASE_MASK 0x00000038
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#define SW_TX_PLD_MODE_OFFSET 1
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#define SW_TX_PLD_MODE_MASK 0x00000006
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#define SW_PLD_COPY_MODE_OFFSET 0
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#define SW_PLD_COPY_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_SW_ACCESS_BUF_ADDR 0x0020
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#define SW_ACCESS_CSI_BUF_EN_OFFSET 2
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#define SW_ACCESS_CSI_BUF_EN_MASK 0x00000004
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#define SW_ACCESS_AGC_GAIN_BUF_EN_OFFSET 1
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#define SW_ACCESS_AGC_GAIN_BUF_EN_MASK 0x00000002
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#define SW_ACCESS_TMI_BUF_EN_OFFSET 0
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#define SW_ACCESS_TMI_BUF_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RX_PAUSE_CLR_ADDR 0x0024
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#define SW_RX_PAUSE_CLR_OFFSET 0
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#define SW_RX_PAUSE_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_INT_EN_ADDR 0x0080
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#define BB_INT_EN_OFFSET 0
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#define BB_INT_EN_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_CLR_ADDR 0x0084
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#define BB_INT_CLR_OFFSET 0
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#define BB_INT_CLR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_MASK_ADDR 0x0088
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#define BB_INT_MASK_OFFSET 0
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#define BB_INT_MASK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_RAW_ADDR 0x008c
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#define BB_INT_RAW_OFFSET 0
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#define BB_INT_RAW_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_FC_OFFSET0_ADDR 0x0100
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#define SW_FC_SYMB5_OFFSET_OFFSET 24
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#define SW_FC_SYMB5_OFFSET_MASK 0xFF000000
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#define SW_FC_SYMB4_OFFSET_OFFSET 16
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#define SW_FC_SYMB4_OFFSET_MASK 0x00FF0000
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#define SW_FC_SYMB3_OFFSET_OFFSET 8
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#define SW_FC_SYMB3_OFFSET_MASK 0x0000FF00
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#define SW_FC_SYMB2_OFFSET_OFFSET 0
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#define SW_FC_SYMB2_OFFSET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_FC_OFFSET1_ADDR 0x0104
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#define SW_FC_SYMB9_OFFSET_OFFSET 24
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#define SW_FC_SYMB9_OFFSET_MASK 0xFF000000
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#define SW_FC_SYMB8_OFFSET_OFFSET 16
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#define SW_FC_SYMB8_OFFSET_MASK 0x00FF0000
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#define SW_FC_SYMB7_OFFSET_OFFSET 8
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#define SW_FC_SYMB7_OFFSET_MASK 0x0000FF00
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#define SW_FC_SYMB6_OFFSET_OFFSET 0
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#define SW_FC_SYMB6_OFFSET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_FC_OFFSET2_ADDR 0x0108
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#define SW_FC_SYMB12_OFFSET_OFFSET 16
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#define SW_FC_SYMB12_OFFSET_MASK 0x00FF0000
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#define SW_FC_SYMB11_OFFSET_OFFSET 8
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#define SW_FC_SYMB11_OFFSET_MASK 0x0000FF00
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#define SW_FC_SYMB10_OFFSET_OFFSET 0
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#define SW_FC_SYMB10_OFFSET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_FC_GI_ADDR 0x010C
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#define SW_FC_GI1_OFFSET 16
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#define SW_FC_GI1_MASK 0x07FF0000
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#define SW_FC_GI0_RANGE_OFFSET 11
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#define SW_FC_GI0_RANGE_MASK 0x00007800
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#define SW_FC_GI0_OFFSET 0
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#define SW_FC_GI0_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_PLD_GI0_ADDR 0x0110
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#define SW_PLD_GI1_RANGE_OFFSET 27
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#define SW_PLD_GI1_RANGE_MASK 0x78000000
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#define SW_PLD_GI1_OFFSET 16
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#define SW_PLD_GI1_MASK 0x07FF0000
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#define SW_PLD_GI0_RANGE_OFFSET 11
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#define SW_PLD_GI0_RANGE_MASK 0x00007800
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#define SW_PLD_GI0_OFFSET 0
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#define SW_PLD_GI0_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_PLD_GI1_ADDR 0x0114
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#define SW_PLD_GI2_OFFSET 0
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#define SW_PLD_GI2_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_CRC_CFG_ADDR 0x0118
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#define SW_PLD_CRC_BY_SW_OFFSET 7
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#define SW_PLD_CRC_BY_SW_MASK 0x00000080
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#define SW_FC_CRC_BY_SW_OFFSET 6
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#define SW_FC_CRC_BY_SW_MASK 0x00000040
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#define SW_PLD_CRC_INV_OFFSET 5
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#define SW_PLD_CRC_INV_MASK 0x00000020
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#define SW_FC_CRC_INV_OFFSET 4
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#define SW_FC_CRC_INV_MASK 0x00000010
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#define SW_PLD_CRC_INITIAL_OFFSET 3
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#define SW_PLD_CRC_INITIAL_MASK 0x00000008
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#define SW_FC_CRC_INITIAL_OFFSET 2
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#define SW_FC_CRC_INITIAL_MASK 0x00000004
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#define SW_PLD_CRC_MODE_OFFSET 1
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#define SW_PLD_CRC_MODE_MASK 0x00000002
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#define SW_FC_CRC_MODE_OFFSET 0
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#define SW_FC_CRC_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_FC_CRC_REM_ADDR 0x011C
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#define SW_FC_CRC_REMAIN_OFFSET 0
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#define SW_FC_CRC_REMAIN_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_PLD_CRC_REM_ADDR 0x0120
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#define SW_PLD_CRC_REMAIN_OFFSET 0
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#define SW_PLD_CRC_REMAIN_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_SOF_FC_FIELD_ADDR 0x0124
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#define SW_SOF_SYMB_NUM_START_OFFSET 24
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#define SW_SOF_SYMB_NUM_START_MASK 0x7F000000
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#define SW_SOF_PB_NUM_START_OFFSET 16
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#define SW_SOF_PB_NUM_START_MASK 0x007F0000
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#define SW_SOF_DCEM_START_OFFSET 8
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#define SW_SOF_DCEM_START_MASK 0x00007F00
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#define SW_SOF_DCBM_START_OFFSET 0
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#define SW_SOF_DCBM_START_MASK 0x0000007F
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//-----------------------------------
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#define CFG_BB_BEA_FC_FIELD_ADDR 0x0128
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#define SW_BEA_SYMB_NUM_START_OFFSET 24
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#define SW_BEA_SYMB_NUM_START_MASK 0x7F000000
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#define SW_BEA_PB_NUM_START_OFFSET 16
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#define SW_BEA_PB_NUM_START_MASK 0x007F0000
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#define SW_BEA_DCEM_START_OFFSET 8
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#define SW_BEA_DCEM_START_MASK 0x00007F00
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#define SW_BEA_DCBM_START_OFFSET 0
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#define SW_BEA_DCBM_START_MASK 0x0000007F
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//-----------------------------------
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#define CFG_BB_FULL_BAND_ADDR 0x0200
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#define SW_FULL_BAND_FC_NUM_OFFSET 27
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#define SW_FULL_BAND_FC_NUM_MASK 0xF8000000
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#define SW_FULL_BAND_END_TONE_OFFSET 16
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#define SW_FULL_BAND_END_TONE_MASK 0x07FF0000
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#define SW_FULL_BAND_START_TONE_OFFSET 0
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#define SW_FULL_BAND_START_TONE_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_LOW_BAND_ADDR 0x0204
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#define SW_LOW_BAND_FC_NUM_OFFSET 27
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#define SW_LOW_BAND_FC_NUM_MASK 0xF8000000
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#define SW_LOW_BAND_END_TONE_OFFSET 16
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#define SW_LOW_BAND_END_TONE_MASK 0x07FF0000
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#define SW_LOW_BAND_START_TONE_OFFSET 0
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#define SW_LOW_BAND_START_TONE_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_HIGH_BAND_ADDR 0x0208
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#define SW_HIGH_BAND_FC_NUM_OFFSET 27
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#define SW_HIGH_BAND_FC_NUM_MASK 0xF8000000
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#define SW_HIGH_BAND_END_TONE_OFFSET 16
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#define SW_HIGH_BAND_END_TONE_MASK 0x07FF0000
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#define SW_HIGH_BAND_START_TONE_OFFSET 0
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#define SW_HIGH_BAND_START_TONE_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_FULL_BAND_VLD_TONE_ADDR 0x200C
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#define SW_FULL_BAND_VLD_TONE_NUM_OFFSET 0
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#define SW_FULL_BAND_VLD_TONE_NUM_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_LOW_BAND_VLD_TONE_ADDR 0x2010
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#define SW_LOW_BAND_VLD_TONE_NUM_OFFSET 0
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#define SW_LOW_BAND_VLD_TONE_NUM_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_HIGH_BAND_VLD_TONE_ADDR 0x2014
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#define SW_HIGH_BAND_VLD_TONE_NUM_OFFSET 0
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#define SW_HIGH_BAND_VLD_TONE_NUM_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_FC_PLD_CNTR_CLR_ADDR 0x0500
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#define PLD_CRC_ERROR_CNTR_CLR_OFFSET 3
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#define PLD_CRC_ERROR_CNTR_CLR_MASK 0x00000008
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#define PLD_CRC_OK_CNTR_CLR_OFFSET 2
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#define PLD_CRC_OK_CNTR_CLR_MASK 0x00000004
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#define FC_CRC_ERROR_CNTR_CLR_OFFSET 1
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#define FC_CRC_ERROR_CNTR_CLR_MASK 0x00000002
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#define FC_CRC_OK_CNTR_CLR_OFFSET 0
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#define FC_CRC_OK_CNTR_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_FC_CRC_OK_CNTR_ADDR 0x0504
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#define FC_CRC_OK_CNTR_OFFSET 0
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#define FC_CRC_OK_CNTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_FC_CRC_ERROR_CNTR_ADDR 0x0508
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#define FC_CRC_ERROR_CNTR_OFFSET 0
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#define FC_CRC_ERROR_CNTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PLD_CRC_OK_CNTR_ADDR 0x050C
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#define PLD_CRC_OK_CNTR_OFFSET 0
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#define PLD_CRC_OK_CNTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PLD_CRC_ERROR_CNTR_ADDR 0x0510
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#define PLD_CRC_ERROR_CNTR_OFFSET 0
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#define PLD_CRC_ERROR_CNTR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_DBG_BUS_SEL_ADDR 0x0600
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#define BB_DBG_BUS_SEL_OFFSET 0
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#define BB_DBG_BUS_SEL_MASK 0x0000000F
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//-----------------------------------
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#define CFG_BB_RX_TD_DBG_BUS0_ADDR 0x0604
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#define RX_TD_DBG_BUS0_OFFSET 0
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#define RX_TD_DBG_BUS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_TD_DBG_BUS1_ADDR 0x0608
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#define RX_TD_DBG_BUS1_OFFSET 0
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#define RX_TD_DBG_BUS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_TD_DBG_BUS2_ADDR 0x060C
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#define RX_TD_DBG_BUS2_OFFSET 0
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#define RX_TD_DBG_BUS2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_TD_DBG_BUS3_ADDR 0x0610
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#define RX_TD_DBG_BUS3_OFFSET 0
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#define RX_TD_DBG_BUS3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_TMI_WORD0_ADDR 0x0614
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#define TMI_WORD0_OFFSET 0
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#define TMI_WORD0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_TMI_WORD1_ADDR 0x0618
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#define TMI_WORD1_OFFSET 0
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#define TMI_WORD1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_TMI_WORD2_ADDR 0x061C
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#define TMI_WORD2_OFFSET 0
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#define TMI_WORD2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_TX_TD_DBG_BUS_ADDR 0x0620
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#define TX_TD_DBG_BUS_OFFSET 0
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#define TX_TD_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_TX_FD_FSM_DBG_BUS_ADDR 0x0624
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#define TX_FD_FSM_DBG_BUS_OFFSET 0
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#define TX_FD_FSM_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PLD_FEC_DBG_BUS_ADDR 0x0628
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#define PLD_FEC_DBG_BUS_OFFSET 0
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#define PLD_FEC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_FC_FEC_DBG_BUS_ADDR 0x062C
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#define FC_FEC_DBG_BUS_OFFSET 0
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#define FC_FEC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PRE_DBG_BUS_ADDR 0x0630
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#define PRE_DBG_BUS_OFFSET 0
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#define PRE_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_AGC_DBG_BUS_ADDR 0x0634
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#define AGC_DBG_BUS_OFFSET 0
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#define AGC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_CH_EST_DBG_BUS_ADDR 0x0638
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#define CH_EST_DBG_BUS_OFFSET 0
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#define CH_EST_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_CH_EQU_DBG_BUS_ADDR 0x063C
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#define CH_EQU_DBG_BUS_OFFSET 0
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#define CH_EQU_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PLD_DE_FEC_DBG_BUS_ADDR 0x0640
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#define PLD_DE_FEC_DBG_BUS_OFFSET 0
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#define PLD_DE_FEC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_FC_CRC_DBG_BUS_ADDR 0x0644
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#define FC_CRC_DBG_BUS_OFFSET 0
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#define FC_CRC_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PB_CRC_DBG_BUS_ADDR 0x0648
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#define PB_CRC_DBG_BUS_OFFSET 0
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#define PB_CRC_DBG_BUS_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define PHY_READ_REG(addr) SOC_READ_REG(PHY_BASEADDR + addr)
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#define PHY_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_BASEADDR + addr,value)
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