kunlun/inc/hw/reg/riscv/14/phy_rx_fd_reg.h

//-----------------------------------
#define CFG_BB_RATE0_DET_BAND_ADDR 0x0000
#define SW_RATE0_DET_END_TONE_OFFSET 16
#define SW_RATE0_DET_END_TONE_MASK 0x07FF0000
#define SW_RATE0_DET_START_TONE_OFFSET 0
#define SW_RATE0_DET_START_TONE_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_RATE1_DET_BAND_ADDR 0x0004
#define SW_RATE1_DET_END_TONE_OFFSET 16
#define SW_RATE1_DET_END_TONE_MASK 0x07FF0000
#define SW_RATE1_DET_START_TONE_OFFSET 0
#define SW_RATE1_DET_START_TONE_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_RATE_OFFET_ADDR 0x0008
#define SW_CSI_RATE1_OFFSET_OFFSET 0
#define SW_CSI_RATE1_OFFSET_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_PKT_DET_ADDR 0x000C
#define SW_SYMB_DET_ALPHA_OFFSET 16
#define SW_SYMB_DET_ALPHA_MASK 0x00070000
#define SW_SYMB_DET_THR1_OFFSET 10
#define SW_SYMB_DET_THR1_MASK 0x0000FC00
#define SW_SYMB_DET_THR0_NUM_OFFSET 6
#define SW_SYMB_DET_THR0_NUM_MASK 0x000001C0
#define SW_SYMB_DET_THR0_OFFSET 0
#define SW_SYMB_DET_THR0_MASK 0x0000003F

//-----------------------------------
#define CFG_BB_FRAME_SYNC_ADDR 0x0010
#define SW_CSI_SYMB_CNTR_OFFSET 6
#define SW_CSI_SYMB_CNTR_MASK 0x000003C0
#define SW_FRAME_SYNC_THR_OFFSET 0
#define SW_FRAME_SYNC_THR_MASK 0x0000003F

//-----------------------------------
#define CFG_BB_SPUR_DET_ADDR 0x0014
#define SW_SPUR_DET_ALPHA_OFFSET 16
#define SW_SPUR_DET_ALPHA_MASK 0x00070000
#define SW_SPUR_MASK_WIDTH_OFFSET 8
#define SW_SPUR_MASK_WIDTH_MASK 0x00000F00
#define SW_SPUR_DET_THR_OFFSET 1
#define SW_SPUR_DET_THR_MASK 0x0000007E
#define SW_SPUR_DET_EN_OFFSET 0
#define SW_SPUR_DET_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_WIENER_FILTER0_ADDR 0x0018
#define SW_WIENER_FILTER_EN_OFFSET 16
#define SW_WIENER_FILTER_EN_MASK 0x00010000
#define SW_FILTER0_RANGE_OFFSET 0
#define SW_FILTER0_RANGE_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_WIENER_FILTER1_ADDR 0x001C
#define SW_FILTER1_RANGE_OFFSET 0
#define SW_FILTER1_RANGE_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_WIENER_FILTER2_ADDR 0x0020
#define SW_FILTER2_RANGE_OFFSET 0
#define SW_FILTER2_RANGE_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_WIENER_FILTER3_ADDR 0x0024
#define SW_FILTER3_RANGE_OFFSET 0
#define SW_FILTER3_RANGE_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_WIENER_FILTER4_ADDR 0x0028
#define SW_FILTER4_RANGE_OFFSET 0
#define SW_FILTER4_RANGE_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_TURBO_CTRL_ADDR 0x002C
#define SW_TURBO_DEC_MARGIN_OFFSET 16
#define SW_TURBO_DEC_MARGIN_MASK 0x07FF0000
#define SW_TURBO_DEC_MAX_NUM_ITER_OFFSET 4
#define SW_TURBO_DEC_MAX_NUM_ITER_MASK 0x000001F0
#define SW_SCRAMBLE_PB_EN_OFFSET 3
#define SW_SCRAMBLE_PB_EN_MASK 0x00000008
#define SW_TURBO_DEC_CRC_EN_OFFSET 2
#define SW_TURBO_DEC_CRC_EN_MASK 0x00000004
#define SW_SCRAMBLE_RESET_MODE_OFFSET 1
#define SW_SCRAMBLE_RESET_MODE_MASK 0x00000002
#define SW_SCRAMBLE_MODE_OFFSET 0
#define SW_SCRAMBLE_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_BB_SNR_ADDR 0x0030
#define SW_SNR_DUMP_START_TONE_OFFSET 16
#define SW_SNR_DUMP_START_TONE_MASK 0x07FF0000
#define SW_CSI_DUMP_SHIFT_OFFSET 8
#define SW_CSI_DUMP_SHIFT_MASK 0x00000700
#define SW_SNR_DUMP_MODE_OFFSET 2
#define SW_SNR_DUMP_MODE_MASK 0x0000000C
#define SW_SNR_DUMP_DONE_OFFSET 1
#define SW_SNR_DUMP_DONE_MASK 0x00000002
#define SW_SNR_DUMP_EN_OFFSET 0
#define SW_SNR_DUMP_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_FREQ_ERROR_ADDR 0x0034
#define SW_FREQ_ERROR_PPM_OFFSET 18
#define SW_FREQ_ERROR_PPM_MASK 0x0FFC0000
#define SW_FREQ_ERROR_MAX_OFFSET 9
#define SW_FREQ_ERROR_MAX_MASK 0x0003FE00
#define SW_KALMAN_BETA_OFFSET 6
#define SW_KALMAN_BETA_MASK 0x000001C0
#define SW_KALMAN_ALPHA_OFFSET 3
#define SW_KALMAN_ALPHA_MASK 0x00000038
#define SW_TRACKING_EN_OFFSET 2
#define SW_TRACKING_EN_MASK 0x00000004
#define SW_FD_COMP_EN_OFFSET 1
#define SW_FD_COMP_EN_MASK 0x00000002
#define SW_TD_COMP_EN_OFFSET 0
#define SW_TD_COMP_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_FC_SOFT_ERROR_CNT_ADDR 0x0040
#define SW_FC_SOFT_BIT_ERROR_CNTR_OFFSET 0
#define SW_FC_SOFT_BIT_ERROR_CNTR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_PLD_SOFT_ERROR_CNT_ADDR 0x0044
#define SW_PLD_SOFT_BIT_ERROR_CNTR_OFFSET 0
#define SW_PLD_SOFT_BIT_ERROR_CNTR_MASK 0x000FFFFF

//-----------------------------------
#define CFG_BB_TURBO_DEC_FC_INFO_ADDR 0x0048
#define FC_TURBO_FAIL_CNTR_OFFSET 16
#define FC_TURBO_FAIL_CNTR_MASK 0x001F0000
#define FC_TURBO_DEC_ERROR_CNTR_OFFSET 0
#define FC_TURBO_DEC_ERROR_CNTR_MASK 0x00001FFF

//-----------------------------------
#define CFG_BB_TURBO_DEC_PB_INFO_ADDR 0x004C
#define PB_TURBO_FAIL_CNTR_OFFSET 16
#define PB_TURBO_FAIL_CNTR_MASK 0x001F0000
#define PB_TURBO_DEC_ERROR_CNTR_OFFSET 0
#define PB_TURBO_DEC_ERROR_CNTR_MASK 0x00001FFF

//-----------------------------------
#define CFG_BB_FC101_ADDR 0x0050
#define SW_FC101_THR_OFFSET 1
#define SW_FC101_THR_MASK 0x0000007E
#define SW_FC101_EN_OFFSET 0
#define SW_FC101_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_DECISION_FEEDBACK_ADDR 0x0054
#define SW_DCFB_ALPHA_OFFSET 1
#define SW_DCFB_ALPHA_MASK 0x0000001E
#define SW_DCFB_EN_OFFSET 0
#define SW_DCFB_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_RIFS_ADDR 0x0058
#define SW_RIFT_TIME_OFFSET 0
#define SW_RIFT_TIME_MASK 0x0000FFFF

//HW module read/write macro
#define PHY_RX_FD_READ_REG(addr) SOC_READ_REG(PHY_RX_FD_BASEADDR + addr)
#define PHY_RX_FD_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_RX_FD_BASEADDR + addr,value)