45 lines
1.7 KiB
C
45 lines
1.7 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef RAM_HW_H
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#define RAM_HW_H
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#define RAM_SYSCLK_SET_AS_150M() \
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do {\
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clk_core_freq_set(CPU_FREQ_150M);\
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} while(0)
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#define RAM_CACHE_INIT() \
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do {\
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ahb_cache_disable(); \
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ahb_set_cache_buffer_mode(); \
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ahb_cache_enable(); \
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ahb_cache_fill_valid_space(); \
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} while (0)
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#define RAM_EFUSE_DUMP() ramEfuseDump(0, 128)
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#define RAM_IMG_OEM_TYPE imgV1OEM
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#define RAM_DEVICE_TYPE devV1Kunlun3
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#define RAM_CHIP_TYPE 3 /* KL3 */
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#define HASH_IV_BASE (0x140+EFUSE_BASEADDR)
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#define FLASH_RUN_ADDR_CHECK(addr) ((((addr & 0xff000000) == (ICACHE0_SFC_RAM_BASEADDR & 0xff000000)) || \
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((addr & 0xff000000) == (ICACHE1_SFC_RAM_BASEADDR & 0xff000000))) ? 1 : 0)
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#define REG_SFC_CFG0 (SFC_REG_BASEADDR + CFG_SFC_CFG0_ADDR)
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#define SFC_CRYPT_OFFSET SFC_CRYPT_MODE_MASK
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#endif //RAM_HW_H
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