132 lines
4.3 KiB
C
132 lines
4.3 KiB
C
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//-----------------------------------
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#define CFG_ADA_BASIC_CFG_ADDR 0x0000
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#define ADA_DMA_RDLR_OFFSET 16
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#define ADA_DMA_RDLR_MASK 0x0FFF0000
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#define ADA_DMA_TDLR_OFFSET 4
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#define ADA_DMA_TDLR_MASK 0x0000FFF0
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#define ADC_EN_OFFSET 3
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#define ADC_EN_MASK 0x00000008
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#define DAC_EN_OFFSET 2
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#define DAC_EN_MASK 0x00000004
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#define ADA_MEM_EB_OFFSET 1
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#define ADA_MEM_EB_MASK 0x00000002
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#define ADA_DMA_EB_OFFSET 0
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#define ADA_DMA_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADA_ADC_CFG0_ADDR 0x0004
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#define ADC_BYTES_SELECT_OFFSET 11
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#define ADC_BYTES_SELECT_MASK 0x00001800
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#define ADC_DUMP_SPEED_OFFSET 8
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#define ADC_DUMP_SPEED_MASK 0x00000700
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#define ADC_CLK_RATIO_OFFSET 4
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#define ADC_CLK_RATIO_MASK 0x000000F0
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#define ADC_DMSB_INV_OFFSET 3
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#define ADC_DMSB_INV_MASK 0x00000008
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#define ADC_DUMP_TRIG_POS_OFFSET 2
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#define ADC_DUMP_TRIG_POS_MASK 0x00000004
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#define ADC_DUMP_MODE_OFFSET 0
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#define ADC_DUMP_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_ADA_ADC_CFG1_ADDR 0x0008
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#define ADC_SAMPLE_SIZE_OFFSET 0
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#define ADC_SAMPLE_SIZE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADA_ADC_CFG2_ADDR 0x000C
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#define ADC_BUF_SIZE_OFFSET 0
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#define ADC_BUF_SIZE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADA_ADC_CFG3_ADDR 0x0010
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#define ADC_DUMP_DONE_OFFSET 1
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#define ADC_DUMP_DONE_MASK 0x00000002
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#define ADC_SAMPLE_CNT_CLR_OFFSET 0
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#define ADC_SAMPLE_CNT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADA_ADC_CFG4_ADDR 0x0014
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#define ADC_THRS_VAL_OFFSET 0
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#define ADC_THRS_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADA_ADC_CFG5_ADDR 0x0018
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#define ADC_TRIG_ADDR_OFFSET 0
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#define ADC_TRIG_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADA_DAC_CFG0_ADDR 0x001C
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#define DAC_CLK_RATIO_OFFSET 4
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#define DAC_CLK_RATIO_MASK 0x000000F0
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#define DAC_RAM_READ_DONE_OFFSET 3
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#define DAC_RAM_READ_DONE_MASK 0x00000008
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#define DAC_INIT_OFFSET 2
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#define DAC_INIT_MASK 0x00000004
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#define DAC_BYTES_SELECT_OFFSET 0
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#define DAC_BYTES_SELECT_MASK 0x00000003
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//-----------------------------------
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#define CFG_ADA_DAC_CFG1_ADDR 0x0020
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#define DAC_BUF_SIZE_OFFSET 0
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#define DAC_BUF_SIZE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADA_ADC_CFG6_ADDR 0x0024
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#define ADC_ADDR_OFFSET_EN_OFFSET 30
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#define ADC_ADDR_OFFSET_EN_MASK 0x40000000
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#define ADC_ADDR_OFFSET_OFFSET 0
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#define ADC_ADDR_OFFSET_MASK 0x3FFFFFFF
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//-----------------------------------
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#define CFG_ADA_DUMP_INT_RAW_ADDR 0x0050
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#define DAC_RAM_READ_DONE_INT_RAW_OFFSET 2
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#define DAC_RAM_READ_DONE_INT_RAW_MASK 0x00000004
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#define ADC_SAMPLE_DONE_INT_RAW_OFFSET 1
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#define ADC_SAMPLE_DONE_INT_RAW_MASK 0x00000002
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#define ADA_DUMP_FIFO_FULL_INT_RAW_OFFSET 0
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#define ADA_DUMP_FIFO_FULL_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADA_DUMP_INT_ST_ADDR 0x0054
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#define DAC_RAM_READ_DONE_INT_ST_OFFSET 2
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#define DAC_RAM_READ_DONE_INT_ST_MASK 0x00000004
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#define ADC_SAMPLE_DONE_INT_ST_OFFSET 1
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#define ADC_SAMPLE_DONE_INT_ST_MASK 0x00000002
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#define ADA_DUMP_FIFO_FULL_INT_ST_OFFSET 0
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#define ADA_DUMP_FIFO_FULL_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADA_DUMP_INT_ENA_ADDR 0x0058
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#define DAC_RAM_READ_DONE_INT_ENA_OFFSET 2
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#define DAC_RAM_READ_DONE_INT_ENA_MASK 0x00000004
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#define ADC_SAMPLE_DONE_INT_ENA_OFFSET 1
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#define ADC_SAMPLE_DONE_INT_ENA_MASK 0x00000002
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#define ADA_DUMP_FIFO_FULL_INT_ENA_OFFSET 0
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#define ADA_DUMP_FIFO_FULL_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADA_DUMP_INT_CLR_ADDR 0x005C
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#define DAC_RAM_READ_DONE_INT_CLR_OFFSET 2
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#define DAC_RAM_READ_DONE_INT_CLR_MASK 0x00000004
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#define ADC_SAMPLE_DONE_INT_CLR_OFFSET 1
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#define ADC_SAMPLE_DONE_INT_CLR_MASK 0x00000002
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#define ADA_DUMP_FIFO_FULL_INT_CLR_OFFSET 0
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#define ADA_DUMP_FIFO_FULL_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADA_TX_BUF_ADDR 0x0100
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#define ADA_FIFO_WDATA_OFFSET 0
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#define ADA_FIFO_WDATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADA_RX_BUF_ADDR 0x0180
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#define ADA_FIFO_RDATA_OFFSET 0
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#define ADA_FIFO_RDATA_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define ADA_READ_REG(addr) SOC_READ_REG(ADA_DUMP_BASEADDR + addr)
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#define ADA_WRITE_REG(addr,value) SOC_WRITE_REG(ADA_DUMP_BASEADDR + addr,value)
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