143 lines
4.2 KiB
C
Executable File
143 lines
4.2 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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***************************************************************************/
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#include "hw_reg_api.h"
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#include "phy_reg.h"
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#include "phy_dfe_reg.h"
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#include "plc_const.h"
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#include "phy_ppm.h"
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void phy_set_sw_nn_tx_ppm_en(uint8_t enable)
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{
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(void)enable;
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return;
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}
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uint32_t phy_get_sw_nn_tx_ppm_en(void)
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{
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return 0;
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}
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void phy_set_sw_nn_rx_ppm_en(uint8_t enable)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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tmp = PHY_DFE_READ_REG(CFG_BB_PPM_CFG2_ADDR);
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REG_FIELD_SET(SW_NN_PPM_EN, tmp, !!enable);
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PHY_DFE_WRITE_REG(CFG_BB_PPM_CFG2_ADDR, tmp);
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#else
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(void)enable;
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#endif
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return;
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}
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uint32_t phy_get_sw_nn_rx_ppm_en(void)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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return (uint32_t)REG_FIELD_GET(SW_NN_PPM_EN, \
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PHY_DFE_READ_REG(CFG_BB_PPM_CFG2_ADDR));
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#else
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return 0;
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#endif
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}
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uint32_t phy_set_sw_nn_ppm_para(uint32_t para_id, uint32_t nn_nid,
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int16_t nn_ppm)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp, reg_addr;
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int16_t self_ppm, rx_nn_phase_adj;
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if (para_id > PHY_SW_NN_PPM_PARA_MAX
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|| nn_ppm == PLC_MAX_PPM_SUPPORT) {
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return ERR_INVAL;
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}
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/* set nn nid */
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reg_addr = CFG_BB_PHY_NN_NID0_ADDR + \
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((CFG_BB_PHY_NN_NID1_ADDR - CFG_BB_PHY_NN_NID0_ADDR) * para_id);
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tmp = PHY_READ_REG(reg_addr);
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/* attention to the define of SW_PHY_NN_NID0~7 in the register header file
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* must be consistent.
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*/
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REG_FIELD_SET(SW_PHY_NN_NID0, tmp, nn_nid);
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PHY_WRITE_REG(reg_addr, tmp);
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/* st nn ppm and phase ppm adj*/
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self_ppm = REG_FIELD_GET(SW_RX_PPM, \
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PHY_DFE_READ_REG(CFG_BB_PPM_SETTING_ADDR));
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rx_nn_phase_adj = (int16_t)PHY_PPM_TO_NN_PHASE_ADJ(nn_ppm, (self_ppm >> 4));
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reg_addr = CFG_BB_NN_PPM_CFG0_ADDR + \
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((CFG_BB_NN_PPM_CFG1_ADDR - CFG_BB_NN_PPM_CFG0_ADDR) * para_id);
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tmp = PHY_DFE_READ_REG(reg_addr);
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/* attention to the define of SW_RX_NN_PPM0~7 & SW_RX_NN_PHASE_ADJ_VAL0~7
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* in the register header file must be consistent.
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*/
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REG_FIELD_SET(SW_RX_NN_PPM0, tmp, nn_ppm << 4);
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REG_FIELD_SET(SW_RX_NN_PHASE_ADJ_VAL0, tmp, rx_nn_phase_adj);
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PHY_DFE_WRITE_REG(reg_addr, tmp);
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#endif
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(void)para_id;
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(void)nn_nid;
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(void)nn_ppm;
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return ERR_OK;
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}
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uint32_t phy_get_sw_nn_rx_ppm_para(uint32_t para_id, uint32_t *nn_nid,
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int16_t *nn_ppm, int16_t *rx_nn_phase_adj)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp, reg_addr;
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if ((para_id > PHY_SW_NN_PPM_PARA_MAX) ||
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!(nn_nid && nn_ppm && rx_nn_phase_adj)) {
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return ERR_INVAL;
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}
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if (nn_nid) {
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reg_addr = CFG_BB_PHY_NN_NID0_ADDR + \
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((CFG_BB_PHY_NN_NID1_ADDR - CFG_BB_PHY_NN_NID0_ADDR) * para_id);
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*nn_nid = (uint32_t)(REG_FIELD_GET(SW_PHY_NN_NID0, \
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PHY_READ_REG(reg_addr)));
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}
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if (nn_ppm || rx_nn_phase_adj) {
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reg_addr = CFG_BB_NN_PPM_CFG0_ADDR + \
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((CFG_BB_NN_PPM_CFG1_ADDR - CFG_BB_NN_PPM_CFG0_ADDR) * para_id);
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tmp = PHY_DFE_READ_REG(reg_addr);
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if (nn_ppm) {
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*nn_ppm = (int16_t)(REG_FIELD_GET(SW_RX_NN_PPM0, tmp) >> 4);
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}
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if (rx_nn_phase_adj) {
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*rx_nn_phase_adj = (int16_t)(REG_FIELD_GET(\
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SW_RX_NN_PHASE_ADJ_VAL0, tmp));
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}
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}
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#endif
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(void)para_id;
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(void)nn_nid;
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(void)nn_ppm;
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(void)rx_nn_phase_adj;
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return ERR_OK;
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}
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uint32_t phy_get_sw_nn_tx_ppm_para(uint32_t para_id, uint32_t *nn_nid,
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int16_t *nn_ppm)
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{
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(void)para_id;
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(void)nn_nid;
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(void)nn_ppm;
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return ERR_OK;
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}
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