149 lines
6.6 KiB
C
Executable File
149 lines
6.6 KiB
C
Executable File
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//-----------------------------------
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#define CFG_MAC_INT_BASE_ADDR 0x0000
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#define MAC_INT_TX_START_BIT_OFFSET 31
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#define MAC_INT_TX_START_BIT_MASK 0x80000000
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#define MAC_INT_ZC2_CAP_BIT_OFFSET 30
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#define MAC_INT_ZC2_CAP_BIT_MASK 0x40000000
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#define MAC_INT_ZC1_CAP_BIT_OFFSET 29
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#define MAC_INT_ZC1_CAP_BIT_MASK 0x20000000
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#define MAC_INT_SCH_REQ_INT_OFFSET 28
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#define MAC_INT_SCH_REQ_INT_MASK 0x10000000
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#define MAC_INT_NTB_COMM_INT3_BIT_OFFSET 27
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#define MAC_INT_NTB_COMM_INT3_BIT_MASK 0x08000000
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#define MAC_INT_NTB_COMM_INT2_BIT_OFFSET 26
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#define MAC_INT_NTB_COMM_INT2_BIT_MASK 0x04000000
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#define MAC_INT_NTB_COMM_INT1_BIT_OFFSET 25
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#define MAC_INT_NTB_COMM_INT1_BIT_MASK 0x02000000
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#define MAC_INT_NTB_COMM_INT0_BIT_OFFSET 24
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#define MAC_INT_NTB_COMM_INT0_BIT_MASK 0x01000000
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#define MAC_INT_RX_TIMEOUT_BIT_OFFSET 23
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#define MAC_INT_RX_TIMEOUT_BIT_MASK 0x00800000
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#define MAC_INT_MAC_RX_ABORT_BIT_OFFSET 22
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#define MAC_INT_MAC_RX_ABORT_BIT_MASK 0x00400000
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#define MAC_INT_RD_PB_BUF_ERR_BIT_OFFSET 21
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#define MAC_INT_RD_PB_BUF_ERR_BIT_MASK 0x00200000
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#define MAC_INT_RD_PB_DESC_ERR_BIT_OFFSET 20
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#define MAC_INT_RD_PB_DESC_ERR_BIT_MASK 0x00100000
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#define MAC_INT_ZC_UP_BOUND_BIT_OFFSET 19
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#define MAC_INT_ZC_UP_BOUND_BIT_MASK 0x00080000
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#define MAC_INT_ZC_LOW_BOUND_BIT_OFFSET 18
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#define MAC_INT_ZC_LOW_BOUND_BIT_MASK 0x00040000
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#define MAC_INT_TX_AES_BIT_OFFSET 17
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#define MAC_INT_TX_AES_BIT_MASK 0x00020000
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#define MAC_INT_ZC_CAP_BIT_OFFSET 16
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#define MAC_INT_ZC_CAP_BIT_MASK 0x00010000
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#define MAC_INT_RX_LOW_WATERMARK_BIT_OFFSET 15
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#define MAC_INT_RX_LOW_WATERMARK_BIT_MASK 0x00008000
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#define MAC_INT_RX_PLD_OF_BIT_OFFSET 14
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#define MAC_INT_RX_PLD_OF_BIT_MASK 0x00004000
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#define MAC_INT_RX_DESC_OF_BIT_OFFSET 13
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#define MAC_INT_RX_DESC_OF_BIT_MASK 0x00002000
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#define MAC_INT_RX_FC_BIT_OFFSET 12
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#define MAC_INT_RX_FC_BIT_MASK 0x00001000
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#define MAC_INT_RX_PB_BIT_OFFSET 11
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#define MAC_INT_RX_PB_BIT_MASK 0x00000800
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#define MAC_INT_RX_MPDU_BIT_OFFSET 10
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#define MAC_INT_RX_MPDU_BIT_MASK 0x00000400
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#define MAC_INT_HWQ_TX_UNDERRUN_BIT_OFFSET 9
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#define MAC_INT_HWQ_TX_UNDERRUN_BIT_MASK 0x00000200
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#define MAC_INT_HWQ_END_DESC_ERR_BIT_OFFSET 8
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#define MAC_INT_HWQ_END_DESC_ERR_BIT_MASK 0x00000100
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#define MAC_INT_HWQ_START_DESC_ERR_BIT_OFFSET 7
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#define MAC_INT_HWQ_START_DESC_ERR_BIT_MASK 0x00000080
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#define MAC_INT_MAC_BUS_ERR_BIT_OFFSET 6
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#define MAC_INT_MAC_BUS_ERR_BIT_MASK 0x00000040
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#define MAC_INT_MPDU_TX_DONE_BIT_OFFSET 5
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#define MAC_INT_MPDU_TX_DONE_BIT_MASK 0x00000020
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#define MAC_INT_HWQ_DIS_DONE_BIT_OFFSET 4
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#define MAC_INT_HWQ_DIS_DONE_BIT_MASK 0x00000010
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#define MAC_INT_SCH_DIS_DONE_BIT_OFFSET 3
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#define MAC_INT_SCH_DIS_DONE_BIT_MASK 0x00000008
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#define MAC_INT_BCN_RECEIVED_BIT_OFFSET 2
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#define MAC_INT_BCN_RECEIVED_BIT_MASK 0x00000004
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#define MAC_INT_BCN_MISS_BIT_OFFSET 1
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#define MAC_INT_BCN_MISS_BIT_MASK 0x00000002
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#define MAC_INT_BCN_ALERT_BIT_OFFSET 0
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#define MAC_INT_BCN_ALERT_BIT_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_INT_EXT_ADDR 0x0004
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#define MAC_INT_HWQ68_NO_TIME_TX_OFFSET 31
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#define MAC_INT_HWQ68_NO_TIME_TX_MASK 0x80000000
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#define MAC_INT_HWQ35_NO_TIME_TX_OFFSET 30
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#define MAC_INT_HWQ35_NO_TIME_TX_MASK 0x40000000
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#define MAC_INT_HWQ02_NO_TIME_TX_OFFSET 29
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#define MAC_INT_HWQ02_NO_TIME_TX_MASK 0x20000000
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#define MAC_INT_PCS_BUSY_TIMEOUT_OFFSET 28
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#define MAC_INT_PCS_BUSY_TIMEOUT_MASK 0x10000000
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#define MAC_INT_PCS_IDLE_TIMEOUT_OFFSET 27
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#define MAC_INT_PCS_IDLE_TIMEOUT_MASK 0x08000000
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#define MAC_INT_VCS_BUSY_TIMEOUT_OFFSET 26
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#define MAC_INT_VCS_BUSY_TIMEOUT_MASK 0x04000000
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#define MAC_INT_RESP_TD_TIMEOUT_OFFSET 25
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#define MAC_INT_RESP_TD_TIMEOUT_MASK 0x02000000
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#define MAC_INT_HWQ_TX_DONE_ZERO_OFFSET 24
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#define MAC_INT_HWQ_TX_DONE_ZERO_MASK 0x01000000
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#define MAC_INT_ZC1_CAP_INT_EXT_OFFSET 23
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#define MAC_INT_ZC1_CAP_INT_EXT_MASK 0x00800000
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#define MAC_INT_ZC0_CAP_INT_EXT_OFFSET 22
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#define MAC_INT_ZC0_CAP_INT_EXT_MASK 0x00400000
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#define MAC_INT_PHY_TX_ABORT_OFFSET 21
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#define MAC_INT_PHY_TX_ABORT_MASK 0x00200000
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#define MAC_INT_TXPB_FIFO_FULL_OFFSET 20
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#define MAC_INT_TXPB_FIFO_FULL_MASK 0x00100000
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#define MAC_INT_MPDU_COLLECT_DONE_OFFSET 19
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#define MAC_INT_MPDU_COLLECT_DONE_MASK 0x00080000
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#define MAC_INT_METER_INT_OFFSET 18
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#define MAC_INT_METER_INT_MASK 0x00040000
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#define MAC_INT_MAC_RX_BUF_AHB_MST_INVALID_OFFSET 17
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#define MAC_INT_MAC_RX_BUF_AHB_MST_INVALID_MASK 0x00020000
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#define MAC_INT_GP_SACK_RESP_CONFIG_TIMEOUT_OFFSET 16
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#define MAC_INT_GP_SACK_RESP_CONFIG_TIMEOUT_MASK 0x00010000
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#define MAC_INT_COMPRESS_DONE_OFFSET 15
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#define MAC_INT_COMPRESS_DONE_MASK 0x00008000
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#define MAC_INT_RX_RING4_SOF_MPDU_DMA_DONE_OFFSET 14
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#define MAC_INT_RX_RING4_SOF_MPDU_DMA_DONE_MASK 0x00004000
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#define MAC_INT_RX_RING3_SOF_MPDU_DMA_DONE_OFFSET 13
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#define MAC_INT_RX_RING3_SOF_MPDU_DMA_DONE_MASK 0x00002000
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#define MAC_INT_RX_RING2_SOF_MPDU_DMA_DONE_OFFSET 12
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#define MAC_INT_RX_RING2_SOF_MPDU_DMA_DONE_MASK 0x00001000
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#define MAC_INT_RX_RING1_SOF_MPDU_DMA_DONE_OFFSET 11
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#define MAC_INT_RX_RING1_SOF_MPDU_DMA_DONE_MASK 0x00000800
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#define MAC_INT_RX_RING0_SOF_MPDU_DMA_DONE_OFFSET 10
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#define MAC_INT_RX_RING0_SOF_MPDU_DMA_DONE_MASK 0x00000400
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#define MAC_INT_RX_RING4_SOF_BURST_DMA_DONE_OFFSET 9
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#define MAC_INT_RX_RING4_SOF_BURST_DMA_DONE_MASK 0x00000200
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#define MAC_INT_RX_RING3_SOF_BURST_DMA_DONE_OFFSET 8
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#define MAC_INT_RX_RING3_SOF_BURST_DMA_DONE_MASK 0x00000100
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#define MAC_INT_RX_RING2_SOF_BURST_DMA_DONE_OFFSET 7
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#define MAC_INT_RX_RING2_SOF_BURST_DMA_DONE_MASK 0x00000080
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#define MAC_INT_RX_RING1_SOF_BURST_DMA_DONE_OFFSET 6
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#define MAC_INT_RX_RING1_SOF_BURST_DMA_DONE_MASK 0x00000040
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#define MAC_INT_RX_RING0_SOF_BURST_DMA_DONE_OFFSET 5
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#define MAC_INT_RX_RING0_SOF_BURST_DMA_DONE_MASK 0x00000020
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#define MAC_INT_RX_RING4_BURST_INT_TRIG_OFFSET 4
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#define MAC_INT_RX_RING4_BURST_INT_TRIG_MASK 0x00000010
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#define MAC_INT_RX_RING3_BURST_INT_TRIG_OFFSET 3
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#define MAC_INT_RX_RING3_BURST_INT_TRIG_MASK 0x00000008
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#define MAC_INT_RX_RING2_BURST_INT_TRIG_OFFSET 2
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#define MAC_INT_RX_RING2_BURST_INT_TRIG_MASK 0x00000004
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#define MAC_INT_RX_RING1_BURST_INT_TRIG_OFFSET 1
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#define MAC_INT_RX_RING1_BURST_INT_TRIG_MASK 0x00000002
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#define MAC_INT_RX_RING0_BURST_INT_TRIG_OFFSET 0
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#define MAC_INT_RX_RING0_BURST_INT_TRIG_MASK 0x00000001
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//-----------------------------------
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#define CFG_MAC_INT_RAW_ADDR 0x0008
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#define MAC_INT_PHY_TX_UNDERFLOW_OFFSET 4
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#define MAC_INT_PHY_TX_UNDERFLOW_MASK 0x00000010
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#define MAC_INT_PHY_TIMEOUT_OFFSET 3
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#define MAC_INT_PHY_TIMEOUT_MASK 0x00000008
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#define MAC_INT_RX_FC_ACK_INT_OFFSET 2
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#define MAC_INT_RX_FC_ACK_INT_MASK 0x00000004
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#define MAC_INT_RAW_TX_SACK_INT_OFFSET 1
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#define MAC_INT_RAW_TX_SACK_INT_MASK 0x00000002
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#define MAC_INT_RAW_TX_START_INT_OFFSET 0
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#define MAC_INT_RAW_TX_START_INT_MASK 0x00000001
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