3378 lines
99 KiB
C
Executable File
3378 lines
99 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef TX_DESC_REG_API
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#define TX_DESC_REG_API
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#include "mpdu_frame.h"
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#include "tx_pb_start.h"
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#include "tx_mpdu_start.h"
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#include "os_mem.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline \
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uint32_t mac_tx_pb_start_get_pb_ssn(uint32_t proto, tx_pb_start *pb_start)
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{
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IOT_ASSERT(pb_start);
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#if SUPPORT_SMART_GRID
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if (proto == PLC_PROTO_TYPE_SG) {
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sg_sof_pb_hdr_t pb_head = { 0 };
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*(uint8_t*) &pb_head = (uint8_t) pb_start->sof_pb_header;
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return pb_head.seq;
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}
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#endif
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#if SUPPORT_SOUTHERN_POWER_GRID
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if (proto == PLC_PROTO_TYPE_SPG) {
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spg_sof_pb_hdr_t pb_head = { 0 };
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*(uint8_t*) &pb_head = (uint8_t) pb_start->sof_pb_header;
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return pb_head.seq;
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}
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#endif
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IOT_ASSERT(0);
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return 0;
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}
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static inline \
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tx_pb_start * mac_tx_pb_start_get_next_pb(tx_pb_start *pb_start)
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{
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return (tx_pb_start*)pb_start->next_pb;
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}
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static inline \
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uint32_t mac_tx_mpdu_start_get_symppb(tx_mpdu_start *mpdu)
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{
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IOT_ASSERT(mpdu);
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return mpdu->tx_symbnum_ppb;
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}
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static inline \
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void * mac_tx_mpdu_start_get_fc_ptr(tx_mpdu_start *mpdu)
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{
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return &mpdu->fc;
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}
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static inline \
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void mac_tx_mpdu_start_set_hp10_fc(tx_mpdu_start *mpdu, uint32_t hp10fc)
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{
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#if SUPPORT_GREEN_PHY
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os_mem_cpy((uint8_t *)&mpdu->hp10_fc, (uint8_t *)&hp10fc, \
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sizeof(uint32_t));
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#else
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mpdu->resv1 = hp10fc;
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#endif
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}
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static inline \
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void mac_tx_mpdu_start_set_ts_high_bit(tx_mpdu_start *mpdu, uint32_t ts_hight_bit)
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{
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(void)mpdu;
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(void)ts_hight_bit;
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}
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static inline \
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void mac_tx_mpdu_start_set_pre_low_ntb(tx_mpdu_start *mpdu, uint32_t ts_low_bit)
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{
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(void)mpdu;
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(void)ts_low_bit;
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}
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static inline \
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void mac_tx_mpdu_start_set_pre_high_ntb(tx_mpdu_start *mpdu, uint32_t ts_high_bit)
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{
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(void)mpdu;
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(void)ts_high_bit;
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}
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void mac_beacon_send_fill_pb_start(uint32_t proto, \
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tx_pb_start *pb_start, uint32_t bcn_buf);
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#ifdef DESC_REG_API_INLINE
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//#define CFG_START_WORD0_ADDR 0x0000
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/* descriptor type */
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static __inline \
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void set_tx_mpdu_stt_type(uint32_t base, uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(DESC_TYPE, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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void get_tx_mpdu_stt_type(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(DESC_TYPE, temp);
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}
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/* protocol type */
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static __inline \
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void set_tx_mpdu_stt_proto_type(uint32_t base, uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(PROTO_TYPE, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_proto_type(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(PROTO_TYPE, temp);
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}
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/* tx port */
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static __inline \
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void set_tx_mpdu_stt_tx_port(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(TX_PORT, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_tx_port(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(TX_PORT, temp);
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}
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/* tx power */
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static __inline \
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void set_tx_mpdu_stt_tx_pwr(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(TX_POWER, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_tx_pwr(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(TX_POWER, temp);
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}
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/* tx phase */
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static __inline \
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void set_tx_mpdu_stt_tx_pha(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(TX_PHASE, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_tx_pha(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(TX_PHASE, temp);
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}
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/* need encry */
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static __inline \
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void set_tx_mpdu_stt_need_enc(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(NEED_ENCRY, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_need_enc(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(NEED_ENCRY, temp);
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}
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/* tx payload module mode */
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static __inline \
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void set_tx_mpdu_stt_pld_mm(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(TX_PLD_MODULE_MODE, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_pld_mm(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(TX_PLD_MODULE_MODE, temp);
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}
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/* tx rate mode */
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static __inline \
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void set_tx_mpdu_stt_rt_mode(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(TX_RATE_MODE, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_rt_mode(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(TX_RATE_MODE, temp);
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}
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/* SG band select */
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static __inline \
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void set_tx_mpdu_stt_sg_bdsel(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(SG_BANDSEL, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_sg_bdsel(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(SG_BANDSEL, temp);
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}
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/* need ack */
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static __inline \
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void set_tx_mpdu_stt_need_ack(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(NEED_ACK, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_need_ack(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(NEED_ACK, temp);
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}
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/* pb number */
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static __inline \
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void set_tx_mpdu_stt_pb_num(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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REG_FIELD_SET(PB_NUM, temp, value);
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TX_DESC_WRITE_REG(base, \
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CFG_START_WORD0_ADDR, temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_pb_num(uint32_t base)
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{
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uint32_t temp = \
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TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(PB_NUM, temp);
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}
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/* ppdu mode */
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static __inline \
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void set_tx_mpdu_stt_ppdu_mode(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD0_ADDR);
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REG_FIELD_SET(PPDU_MODE, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD0_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_ppdu_mode(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD0_ADDR);
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return REG_FIELD_GET(PPDU_MODE, temp);
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}
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//-----------------------------------
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//#define CFG_START_WORD1_ADDR 0x0004
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/* tx tone amp */
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static __inline \
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void set_tx_mpdu_stt_tone_amp(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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REG_FIELD_SET(TX_TONE_AMP, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_tone_amp(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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return REG_FIELD_GET(TX_TONE_AMP, temp);
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}
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/* tx symbol number pbb */
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static __inline \
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void set_tx_mpdu_stt_symnum_pbb(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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REG_FIELD_SET(TX_SYMBNUM_PPB, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_symnum_pbb(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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return REG_FIELD_GET(TX_SYMBNUM_PPB, temp);
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}
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/* sw tx flow pbb */
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static __inline \
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void set_tx_mpdu_stt_flw_pbb(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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REG_FIELD_SET(SW_TX_FL_PPB, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_flw_pbb(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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return REG_FIELD_GET(SW_TX_FL_PPB, temp);
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}
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/* pb header crc len */
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static __inline \
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void set_tx_mpdu_stt_pbhdr_crclen(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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REG_FIELD_SET(PB_HDR_CRC_LEN, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_pbhdr_crclen(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD1_ADDR);
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return REG_FIELD_GET(PB_HDR_CRC_LEN, temp);
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}
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//-----------------------------------
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//#define CFG_START_WORD2_ADDR 0x0008
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/* next poiter*/
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static __inline \
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void set_tx_mpdu_stt_next_ptr(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD2_ADDR);
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REG_FIELD_SET(NEXT, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD2_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_next_ptr(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD2_ADDR);
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return REG_FIELD_GET(NEXT, temp);
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}
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//-----------------------------------
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//#define CFG_START_WORD3_ADDR 0x000C
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/* tx status */
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static __inline \
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void set_tx_mpdu_stt_tx_st(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD3_ADDR);
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REG_FIELD_SET(TX_STATUS, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD3_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_tx_st(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD3_ADDR);
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return REG_FIELD_GET(TX_STATUS, temp);
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}
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//-----------------------------------
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//#define CFG_START_WORD4_ADDR 0x0010
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/* pb list */
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static __inline \
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void set_tx_mpdu_stt_pb_list(uint32_t base, \
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uint32_t value)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD4_ADDR);
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REG_FIELD_SET(PB_LIST, temp, value);
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TX_DESC_WRITE_REG(base, CFG_START_WORD4_ADDR, \
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temp);
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}
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static __inline \
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uint32_t get_tx_mpdu_stt_pb_list(uint32_t base)
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{
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uint32_t temp = TX_DESC_READ_REG(base, \
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CFG_START_WORD4_ADDR);
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return REG_FIELD_GET(PB_LIST, temp);
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}
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//-----------------------------------
|
|
//#define CFG_START_WORD5_ADDR 0x0014
|
|
/* FC0 */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_fc0(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD5_ADDR);
|
|
REG_FIELD_SET(FC0, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD5_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline
|
|
uint32_t get_tx_mpdu_stt_fc0(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD5_ADDR);
|
|
return REG_FIELD_GET(FC0, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD6_ADDR 0x0018
|
|
/* FC1 */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_fc1(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD6_ADDR);
|
|
REG_FIELD_SET(FC1, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD6_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_fc1(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD6_ADDR);
|
|
return REG_FIELD_GET(FC1, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD7_ADDR 0x001C
|
|
/* FC2 */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_fc2(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD7_ADDR);
|
|
REG_FIELD_SET(FC2, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD7_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_fc2(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base + \
|
|
CFG_START_WORD7_ADDR);
|
|
return REG_FIELD_GET(FC2, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD8_ADDR 0x0020
|
|
/* FC3 */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_fc3(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD8_ADDR);
|
|
REG_FIELD_SET(FC3, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD8_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_fc3(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD8_ADDR);
|
|
return REG_FIELD_GET(FC3, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD9_ADDR 0x0024
|
|
/* sw fc crc */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_sw_fc_crc(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
REG_FIELD_SET(SW_FC_CRC, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_sw_fc_crc(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
return REG_FIELD_GET(SW_FC_CRC, temp);
|
|
}
|
|
/* sw pb crc */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_sw_pb_crc(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
REG_FIELD_SET(SW_PB_CRC, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_sw_pb_crc(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
return REG_FIELD_GET(SW_PB_CRC, temp);
|
|
}
|
|
|
|
/* total bytes */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_tt_bytes(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
REG_FIELD_SET(TOTAL_BYTES, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_tt_bytes(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
return REG_FIELD_GET(TOTAL_BYTES, temp);
|
|
}
|
|
|
|
/* offset */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR);
|
|
REG_FIELD_SET(OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_START_WORD9_ADDR);
|
|
return REG_FIELD_GET(OFFSET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD10_ADDR 0x0028
|
|
/* start time */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_stt_time(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD10_ADDR);
|
|
REG_FIELD_SET(START_TIME, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD10_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_stt_time(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD10_ADDR);
|
|
return REG_FIELD_GET(START_TIME, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD11_ADDR 0x002C
|
|
/* swq id */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_swq_id(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD11_ADDR);
|
|
REG_FIELD_SET(SWQ_ID, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD11_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_swq_id(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD11_ADDR);
|
|
return REG_FIELD_GET(SWQ_ID, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD12_ADDR 0x0030
|
|
/* rts enable */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_rts_en(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(RTS_ENABLE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_rts_en(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(RTS_ENABLE, temp);
|
|
}
|
|
|
|
/* cts enable */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_cts_en(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(CTS_ENABLE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_cts_en(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(CTS_ENABLE, temp);
|
|
}
|
|
|
|
/* hw retry count */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_hw_retry_cnt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(HW_RETRY_CNT, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_hw_retry_cnt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(HW_RETRY_CNT, temp);
|
|
}
|
|
|
|
/* avln index */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_avln_idx(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(AVLN_IDX, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_avln_idx(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(AVLN_IDX, temp);
|
|
}
|
|
|
|
/* key table index */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_key_tbl_idx(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(KEY_TABLE_IDX, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_key_tbl_idx(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(KEY_TABLE_IDX, temp);
|
|
}
|
|
|
|
/* key index */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_key_idx(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(KEY_IDX, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_key_idx(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(KEY_IDX, temp);
|
|
}
|
|
|
|
/* list start */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_list_stt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(LIST_START, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_list_stt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(LIST_START, temp);
|
|
}
|
|
/* list end */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_list_end(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(LIST_END, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_list_end(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(LIST_END, temp);
|
|
}
|
|
|
|
/* PB buffer reuse */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_pbbuf_reuse(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(PB_BUF_REUSE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_pbbuf_reuse(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(PB_BUF_REUSE, temp);
|
|
}
|
|
|
|
/* tx desc reuse */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_txdesc_reuse(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(TX_DESC_REUSE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_txdesc_reuse(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(TX_DESC_REUSE, temp);
|
|
}
|
|
|
|
/* pause on xtretry */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_pause_on_xttry(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(PAUSE_ON_XTRETRY, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_pause_on_xttry(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(PAUSE_ON_XTRETRY, temp);
|
|
}
|
|
|
|
/* sw buffer offset */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_swbuf_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
REG_FIELD_SET(SW_BUF_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_swbuf_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR);
|
|
return REG_FIELD_GET(SW_BUF_OFFSET, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD13_ADDR 0x0034
|
|
/* hp10 fc */
|
|
static __inline \
|
|
void set_tx_mpdu_stt_hp10_fc(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD13_ADDR);
|
|
REG_FIELD_SET(HP10_FC, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD13_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_stt_hp10_fc(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD13_ADDR);
|
|
return REG_FIELD_GET(HP10_FC, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD0_ADDR 0x0000
|
|
/* tx done */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tx_done(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(TX_DONE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tx_done(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(TX_DONE, temp);
|
|
}
|
|
/* tx ok */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tx_ok(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(TX_OK, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tx_ok(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(TX_OK, temp);
|
|
}
|
|
|
|
/* phy error flag */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_phyerr(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(IS_PHYERR, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_phyerr(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(IS_PHYERR, temp);
|
|
}
|
|
|
|
/* phy error ID */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_phyerr_id(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(PHYERR_ID, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_phyerr_id(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(PHYERR_ID, temp);
|
|
}
|
|
|
|
/* filtered flag */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_is_fted(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(IS_FILTERED, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_is_fted(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(IS_FILTERED, temp);
|
|
}
|
|
|
|
/* mac error flag */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_macerr(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(IS_MACERR, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_macerr(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(IS_MACERR, temp);
|
|
}
|
|
|
|
/* mac event id */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_macevt_id(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(MAC_EVENT_ID, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_macevt_id(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(MAC_EVENT_ID, temp);
|
|
}
|
|
|
|
/* total retry count */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tt_rtry_cnt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(TOTAL_RETRY_CNT, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tt_rtry_cnt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(TOTAL_RETRY_CNT, temp);
|
|
}
|
|
|
|
/* sack bitmap */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_sack_bitmap(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
REG_FIELD_SET(SACK_BITMAP, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_scak_bitmap(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR);
|
|
return REG_FIELD_GET(SACK_BITMAP, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD1_ADDR 0x0004
|
|
/* first try time stamp */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_1st_try_ts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD1_ADDR);
|
|
REG_FIELD_SET(FIRST_TRY_TS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD1_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_1st_try_ts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD1_ADDR);
|
|
return REG_FIELD_GET(FIRST_TRY_TS, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD2_ADDR 0x0008
|
|
/* try0 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try0_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR);
|
|
REG_FIELD_SET(TRY0_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD2_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try0_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR);
|
|
return REG_FIELD_GET(TRY0_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try0 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_end_try0_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR);
|
|
REG_FIELD_SET(TRY0_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD2_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try0_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR);
|
|
return REG_FIELD_GET(TRY0_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try0 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try0_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR);
|
|
REG_FIELD_SET(TRY0_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD2_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try0_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR);
|
|
return REG_FIELD_GET(TRY0_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD3_ADDR 0x000c
|
|
/* try1 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try1_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR);
|
|
REG_FIELD_SET(TRY1_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD3_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try1_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR);
|
|
return REG_FIELD_GET(TRY1_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try1 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try1_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR);
|
|
REG_FIELD_SET(TRY1_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD3_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try1_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR);
|
|
return REG_FIELD_GET(TRY1_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try1 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try1_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR);
|
|
REG_FIELD_SET(TRY1_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD3_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try1_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR);
|
|
return REG_FIELD_GET(TRY1_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD4_ADDR 0x0010
|
|
/* try2 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try2_rtrytime_offset(uint32_t base,
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR);
|
|
REG_FIELD_SET(TRY2_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD4_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try2_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR);
|
|
return REG_FIELD_GET(TRY2_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try2 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try2_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR);
|
|
REG_FIELD_SET(TRY2_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD4_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try2_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR);
|
|
return REG_FIELD_GET(TRY2_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try2 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try2_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR);
|
|
REG_FIELD_SET(TRY2_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD4_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try2_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR);
|
|
return REG_FIELD_GET(TRY2_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD5_ADDR 0x0014
|
|
/* try3 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try3_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR);
|
|
REG_FIELD_SET(TRY3_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD5_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try3_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR);
|
|
return REG_FIELD_GET(TRY3_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try3 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try3_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR);
|
|
REG_FIELD_SET(TRY3_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD5_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try3_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR);
|
|
return REG_FIELD_GET(TRY3_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try3 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try3_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR);
|
|
REG_FIELD_SET(TRY3_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD5_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try3_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR);
|
|
return REG_FIELD_GET(TRY3_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD6_ADDR 0x0018
|
|
/* try4 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try4_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR);
|
|
REG_FIELD_SET(TRY4_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD6_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try4_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR);
|
|
return REG_FIELD_GET(TRY4_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try4 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try4_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR);
|
|
REG_FIELD_SET(TRY4_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD6_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try4_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD6_ADDR);
|
|
return REG_FIELD_GET(TRY4_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try4 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try4_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR);
|
|
REG_FIELD_SET(TRY4_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD6_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try4_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR);
|
|
return REG_FIELD_GET(TRY4_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD7_ADDR 0x001c
|
|
/* try5 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try5_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR);
|
|
REG_FIELD_SET(TRY5_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD7_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try5_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR);
|
|
return REG_FIELD_GET(TRY5_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try5 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try5_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR);
|
|
REG_FIELD_SET(TRY5_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD7_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try5_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR);
|
|
return REG_FIELD_GET(TRY5_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try5 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try5_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR);
|
|
REG_FIELD_SET(TRY5_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD7_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try5_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR);
|
|
return REG_FIELD_GET(TRY5_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD8_ADDR 0x0020
|
|
/* try6 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try6_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR);
|
|
REG_FIELD_SET(TRY6_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD8_ADDR, temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try6_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD8_ADDR);
|
|
return REG_FIELD_GET(TRY6_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try6 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try6_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR);
|
|
REG_FIELD_SET(TRY6_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD8_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try6_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR);
|
|
return REG_FIELD_GET(TRY6_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try6 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try6_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR);
|
|
REG_FIELD_SET(TRY6_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD8_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try6_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR);
|
|
return REG_FIELD_GET(TRY6_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD9_ADDR 0x0024
|
|
/* try7 retry time offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try7_rtrytime_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR);
|
|
REG_FIELD_SET(TRY7_RETRY_TIME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD9_ADDR,
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try7_rtrytime_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD9_ADDR);
|
|
return REG_FIELD_GET(TRY7_RETRY_TIME_OFFSET, temp);
|
|
}
|
|
|
|
/* try7 tx rtscts */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try7_tx_rtscts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR);
|
|
REG_FIELD_SET(TRY7_TX_RTSCTS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD9_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try7_tx_rtscts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD9_ADDR);
|
|
return REG_FIELD_GET(TRY7_TX_RTSCTS, temp);
|
|
}
|
|
|
|
/* try7 tx packet */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_try7_tx_pkt(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR);
|
|
REG_FIELD_SET(TRY7_TX_PACKET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD9_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_try7_tx_pkt(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR);
|
|
return REG_FIELD_GET(TRY7_TX_PACKET, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD10_ADDR 0x0028
|
|
/* sack time stamp */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_sack_ts(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD10_ADDR);
|
|
REG_FIELD_SET(SACK_TIMESTAMP, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD10_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_sack_ts(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD10_ADDR);
|
|
return REG_FIELD_GET(SACK_TIMESTAMP, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD11_ADDR 0x002c
|
|
/* pb0 status */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_pb0_st(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD11_ADDR);
|
|
REG_FIELD_SET(PB0_STATUS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_pb0_st(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
return REG_FIELD_GET(PB0_STATUS, temp);
|
|
}
|
|
|
|
/* pb1 status */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_pb1_st(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
REG_FIELD_SET(PB1_STATUS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_pb1_st(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
return REG_FIELD_GET(PB1_STATUS, temp);
|
|
}
|
|
/* pb2 status */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_pb2_st(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
REG_FIELD_SET(PB2_STATUS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_pb2_st(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
return REG_FIELD_GET(PB2_STATUS, temp);
|
|
}
|
|
|
|
/* pb3 status */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_pb3_st(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
REG_FIELD_SET(PB3_STATUS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_pb3_st(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR);
|
|
return REG_FIELD_GET(PB3_STATUS, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD12_ADDR 0x0030
|
|
/* tx frame current pointer */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tx_frm_ptr(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD12_ADDR);
|
|
REG_FIELD_SET(TX_FRAME_CUR_PTR, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD12_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tx_frm_ptr(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD12_ADDR);
|
|
return REG_FIELD_GET(TX_FRAME_CUR_PTR, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD13_ADDR 0x0034
|
|
/* tx frame byte */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tx_frm_byte(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD13_ADDR);
|
|
REG_FIELD_SET(TX_FRAME_BYTE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD13_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tx_frm_byte(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD13_ADDR);
|
|
return REG_FIELD_GET(TX_FRAME_BYTE, temp);
|
|
}
|
|
|
|
/* tx frame offset */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tx_frm_offset(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD13_ADDR);
|
|
REG_FIELD_SET(TX_FRAME_OFFSET, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD13_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tx_frm_offset(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD13_ADDR);
|
|
return REG_FIELD_GET(TX_FRAME_OFFSET, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD14_ADDR 0x0038
|
|
/* PB status */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_pb_st(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
REG_FIELD_SET(PB_STATUS, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_pb_st(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
return REG_FIELD_GET(PB_STATUS, temp);
|
|
}
|
|
/* minmum tx snn */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_min_tx_ssn(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
REG_FIELD_SET(MINTXSSN, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_min_tx_ssn(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
return REG_FIELD_GET(MINTXSSN, temp);
|
|
}
|
|
|
|
/* oldest pb try number */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_oldest_pbtry_num(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
REG_FIELD_SET(OLDEST_PB_TRY_NUMBER, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_oldest_pbtry_num(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
return REG_FIELD_GET(OLDEST_PB_TRY_NUMBER, temp);
|
|
}
|
|
|
|
/* tx window size */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_tx_wsz(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR);
|
|
REG_FIELD_SET(TXWINDSZ, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_tx_wsz(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD14_ADDR);
|
|
return REG_FIELD_GET(TXWINDSZ, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD15_ADDR 0x003c
|
|
/* MFS cmd */
|
|
static __inline \
|
|
void set_tx_mpdu_ed_mfscmd_st(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD15_ADDR);
|
|
REG_FIELD_SET(MFSCMD_STATE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD15_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_mpdu_ed_mfscmd_st(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base,
|
|
CFG_END_WORD15_ADDR);
|
|
return REG_FIELD_GET(MFSCMD_STATE, temp);
|
|
}
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_0_ADDR 0x0000
|
|
/* next pb pointer */
|
|
static __inline \
|
|
void set_tx_pb_stt_next_pb(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_0_ADDR);
|
|
REG_FIELD_SET(NEXT_PB, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_pb_stt_next_pb(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_0_ADDR);
|
|
return REG_FIELD_GET(NEXT_PB, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_1_ADDR 0x0004
|
|
/* pb buf addr */
|
|
static __inline \
|
|
void set_tx_pb_stt_pb_buf_addr(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_1_ADDR);
|
|
REG_FIELD_SET(PB_BUF_ADDR, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_1_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_pb_stt_pb_buf_addr(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_1_ADDR);
|
|
return REG_FIELD_GET(PB_BUF_ADDR, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_2_ADDR 0x0008
|
|
/* sof pb buf */
|
|
static __inline \
|
|
void set_tx_pb_stt_sof_pb_hdr(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_2_ADDR);
|
|
REG_FIELD_SET(SOF_PB_HEADER, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_2_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_pb_stt_sof_pb_hdr(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_2_ADDR);
|
|
return REG_FIELD_GET(SOF_PB_HEADER, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_3_ADDR 0x000c
|
|
/* pb crc */
|
|
static __inline \
|
|
void set_tx_pb_stt_pb_crc(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_3_ADDR);
|
|
REG_FIELD_SET(SOF_PB_HEADER, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_3_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_pb_stt_pb_crc(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_3_ADDR);
|
|
return REG_FIELD_GET(SOF_PB_HEADER, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_DUMMY_0_ADDR 0x0000
|
|
/* desc type */
|
|
static __inline \
|
|
void set_tx_dummy_desc_type(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_0_ADDR);
|
|
REG_FIELD_SET(DESC_TYPE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_DUMMY_0_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_dummy_desc_type(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_0_ADDR);
|
|
return REG_FIELD_GET(DESC_TYPE, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_DUMMY_1_ADDR 0x0004
|
|
/* tx done */
|
|
static __inline \
|
|
void set_tx_dummy_desc_type(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_1_ADDR);
|
|
REG_FIELD_SET(TX_DONE, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_DUMMY_1_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_dummy_desc_type(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_1_ADDR);
|
|
return REG_FIELD_GET(TX_DONE, temp);
|
|
}
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_DUMMY_2_ADDR 0x0008
|
|
/* dummy next */
|
|
static __inline \
|
|
void set_tx_dummy_next_dummy(uint32_t base, \
|
|
uint32_t value)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_2_ADDR);
|
|
REG_FIELD_SET(DUMMY_NEXT, temp, value);
|
|
TX_DESC_WRITE_REG(base, CFG_TX_DUMMY_2_ADDR, \
|
|
temp);
|
|
}
|
|
|
|
static __inline \
|
|
uint32_t get_tx_dummy_next_dummy(uint32_t base)
|
|
{
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_2_ADDR);
|
|
return REG_FIELD_GET(DUMMY_NEXT, temp);
|
|
}
|
|
#else
|
|
//#define CFG_START_WORD0_ADDR 0x0000
|
|
/* descriptor type */
|
|
#define set_tx_mpdu_stt_type(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(DESC_TYPE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_type(base) \
|
|
REG_FIELD_GET(DESC_TYPE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
|
|
/* protocol type */
|
|
#define set_tx_mpdu_stt_proto_type(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(PROTO_TYPE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_proto_type(base) \
|
|
REG_FIELD_GET(PROTO_TYPE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
|
|
/* tx port */
|
|
#define set_tx_mpdu_stt_tx_port(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(TX_PORT, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_tx_port(base) \
|
|
REG_FIELD_GET(TX_PORT, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
|
|
/* tx power */
|
|
#define set_tx_mpdu_stt_tx_pwr(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(TX_POWER, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_tx_pwr(base) \
|
|
REG_FIELD_GET(TX_POWER, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
|
|
/* tx phase */
|
|
#define set_tx_mpdu_stt_tx_pha(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR);\
|
|
REG_FIELD_SET(TX_PHASE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_tx_pha(base) \
|
|
REG_FIELD_GET(TX_PHASE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* need encry */
|
|
#define set_tx_mpdu_stt_need_enc(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(NEED_ENCRY, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_need_enc(base) \
|
|
REG_FIELD_GET(NEED_ENCRY, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* tx payload module mode */
|
|
#define set_tx_mpdu_stt_pld_mm(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(TX_PLD_MODULE_MODE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_pld_mm(base) \
|
|
REG_FIELD_GET(TX_PLD_MODULE_MODE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* tx rate mode */
|
|
#define set_tx_mpdu_stt_rt_mode(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(TX_RATE_MODE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_rt_mode(base) \
|
|
REG_FIELD_GET(TX_RATE_MODE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* SG band select */
|
|
#define set_tx_mpdu_stt_sg_bdsel(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(SG_BANDSEL, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_sg_bdsel(base) \
|
|
REG_FIELD_GET(SG_BANDSEL, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* need ack */
|
|
#define set_tx_mpdu_stt_need_ack(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(NEED_ACK, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_need_ack(base) \
|
|
REG_FIELD_GET(NEED_ACK, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* pb number */
|
|
#define set_tx_mpdu_stt_pb_num(base, value) \
|
|
do { \
|
|
uint32_t temp = \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(PB_NUM, temp, value); \
|
|
TX_DESC_WRITE_REG(base, \
|
|
CFG_START_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_pb_num(base) \
|
|
REG_FIELD_GET(PB_NUM, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
/* ppdu mode */
|
|
#define set_tx_mpdu_stt_ppdu_mode(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD0_ADDR); \
|
|
REG_FIELD_SET(PPDU_MODE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD0_ADDR, \
|
|
temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_ppdu_mode(base) \
|
|
REG_FIELD_GET(PPDU_MODE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD0_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD1_ADDR 0x0004
|
|
/* tx tone amp */
|
|
#define set_tx_mpdu_stt_tone_amp(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD1_ADDR); \
|
|
REG_FIELD_SET(TX_TONE_AMP, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_tone_amp(base) \
|
|
REG_FIELD_GET(TX_TONE_AMP, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD1_ADDR))
|
|
|
|
/* tx symbol number pbb */
|
|
#define set_tx_mpdu_stt_symnum_pbb(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD1_ADDR); \
|
|
REG_FIELD_SET(TX_SYMBNUM_PPB, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_symnum_pbb(base) \
|
|
REG_FIELD_GET(TX_SYMBNUM_PPB, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD1_ADDR))
|
|
|
|
/* sw tx flow pbb */
|
|
#define set_tx_mpdu_stt_flw_pbb(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD1_ADDR); \
|
|
REG_FIELD_SET(SW_TX_FL_PPB, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_flw_pbb(base) \
|
|
REG_FIELD_GET(SW_TX_FL_PPB, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD1_ADDR))
|
|
/* pb header crc len */
|
|
#define set_tx_mpdu_stt_pbhdr_crclen(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD1_ADDR); \
|
|
REG_FIELD_SET(PB_HDR_CRC_LEN, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_pbhdr_crclen(base) \
|
|
REG_FIELD_GET(PB_HDR_CRC_LEN, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD1_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD2_ADDR 0x0008
|
|
/* next poiter*/
|
|
#define set_tx_mpdu_stt_next_ptr(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD2_ADDR); \
|
|
REG_FIELD_SET(NEXT, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD2_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_next_ptr(base) \
|
|
REG_FIELD_GET(NEXT, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD2_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD3_ADDR 0x000C
|
|
/* tx status */
|
|
#define set_tx_mpdu_stt_tx_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD3_ADDR); \
|
|
REG_FIELD_SET(TX_STATUS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD3_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_tx_st(base) \
|
|
REG_FIELD_GET(TX_STATUS, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD3_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD4_ADDR 0x0010
|
|
/* pb list */
|
|
#define set_tx_mpdu_stt_pb_list(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD4_ADDR); \
|
|
REG_FIELD_SET(PB_LIST, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD4_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_pb_list(base) \
|
|
REG_FIELD_GET(PB_LIST, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD4_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD5_ADDR 0x0014
|
|
/* FC0 */
|
|
#define set_tx_mpdu_stt_fc0(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD5_ADDR); \
|
|
REG_FIELD_SET(FC0, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD5_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_fc0(base) \
|
|
REG_FIELD_GET(FC0, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD5_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD6_ADDR 0x0018
|
|
/* FC1 */
|
|
#define set_tx_mpdu_stt_fc1( base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD6_ADDR); \
|
|
REG_FIELD_SET(FC1, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD6_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_fc1(base) \
|
|
REG_FIELD_GET(FC1, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD6_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD7_ADDR 0x001C
|
|
/* FC2 */
|
|
#define set_tx_mpdu_stt_fc2(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD7_ADDR); \
|
|
REG_FIELD_SET(FC2, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD7_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_fc2(base) \
|
|
REG_FIELD_GET(FC2, \
|
|
TX_DESC_READ_REG(base + CFG_START_WORD7_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD8_ADDR 0x0020
|
|
/* FC3 */
|
|
#define set_tx_mpdu_stt_fc3(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD8_ADDR); \
|
|
REG_FIELD_SET(FC3, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD8_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_fc3(base) \
|
|
REG_FIELD_GET(FC3, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD8_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD9_ADDR 0x0024
|
|
/* sw fc crc */
|
|
#define set_tx_mpdu_stt_sw_fc_crc(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR); \
|
|
REG_FIELD_SET(SW_FC_CRC, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_sw_fc_crc(base) \
|
|
REG_FIELD_GET(SW_FC_CRC, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD9_ADDR))
|
|
/* sw pb crc */
|
|
#define set_tx_mpdu_stt_sw_pb_crc(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR); \
|
|
REG_FIELD_SET(SW_PB_CRC, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_sw_pb_crc(base) \
|
|
REG_FIELD_GET(SW_PB_CRC, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD9_ADDR))
|
|
|
|
/* total bytes */
|
|
#define set_tx_mpdu_stt_tt_bytes(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR); \
|
|
REG_FIELD_SET(TOTAL_BYTES, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_tt_bytes(base) \
|
|
REG_FIELD_GET(TOTAL_BYTES, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD9_ADDR))
|
|
|
|
/* offset */
|
|
#define set_tx_mpdu_stt_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD9_ADDR); \
|
|
REG_FIELD_SET(OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_offset(base) \
|
|
REG_FIELD_GET(OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD9_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD10_ADDR 0x0028
|
|
/* start time */
|
|
#define set_tx_mpdu_stt_stt_time(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD10_ADDR); \
|
|
REG_FIELD_SET(START_TIME, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD10_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_stt_time(base) \
|
|
REG_FIELD_GET(START_TIME, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD10_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD11_ADDR 0x002C
|
|
/* swq id */
|
|
#define set_tx_mpdu_stt_swq_id(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD11_ADDR); \
|
|
REG_FIELD_SET(SWQ_ID, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD11_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_swq_id(base) \
|
|
REG_FIELD_GET(SWQ_ID, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD11_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD12_ADDR 0x0030
|
|
/* rts enable */
|
|
#define set_tx_mpdu_stt_rts_en(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(RTS_ENABLE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_rts_en(base) \
|
|
REG_FIELD_GET(RTS_ENABLE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* cts enable */
|
|
#define set_tx_mpdu_stt_cts_en(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(CTS_ENABLE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_cts_en(base) \
|
|
REG_FIELD_GET(CTS_ENABLE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* hw retry count */
|
|
#define set_tx_mpdu_stt_hw_retry_cnt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(HW_RETRY_CNT, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_hw_retry_cnt(base) \
|
|
REG_FIELD_GET(HW_RETRY_CNT, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* avln index */
|
|
#define set_tx_mpdu_stt_avln_idx(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(AVLN_IDX, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_avln_idx(base) \
|
|
REG_FIELD_GET(AVLN_IDX, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* key table index */
|
|
#define set_tx_mpdu_stt_key_tbl_idx(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(KEY_TABLE_IDX, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_key_tbl_idx(base) \
|
|
REG_FIELD_GET(KEY_TABLE_IDX, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* key index */
|
|
#define set_tx_mpdu_stt_key_idx(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(KEY_IDX, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_key_idx(base) \
|
|
REG_FIELD_GET(KEY_IDX, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* list start */
|
|
#define set_tx_mpdu_stt_list_stt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(LIST_START, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_list_stt(base) \
|
|
REG_FIELD_GET(LIST_START, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
/* list end */
|
|
#define set_tx_mpdu_stt_list_end(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(LIST_END, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_list_end(base) \
|
|
REG_FIELD_GET(LIST_END, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* PB buffer reuse */
|
|
#define set_tx_mpdu_stt_pbbuf_reuse(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(PB_BUF_REUSE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_pbbuf_reuse(base) \
|
|
REG_FIELD_GET(PB_BUF_REUSE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* tx desc reuse */
|
|
#define set_tx_mpdu_stt_txdesc_reuse(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(TX_DESC_REUSE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR,temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_txdesc_reuse(base) \
|
|
REG_FIELD_GET(TX_DESC_REUSE, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* pause on xtretry */
|
|
#define set_tx_mpdu_stt_pause_on_xttry(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(PAUSE_ON_XTRETRY, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_pause_on_xttry(base) \
|
|
REG_FIELD_GET(PAUSE_ON_XTRETRY, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
|
|
/* sw buffer offset */
|
|
#define set_tx_mpdu_stt_swbuf_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD12_ADDR); \
|
|
REG_FIELD_SET(SW_BUF_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_swbuf_offset(base) \
|
|
REG_FIELD_GET(SW_BUF_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD12_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_START_WORD13_ADDR 0x0034
|
|
/* hp10 fc */
|
|
#define set_tx_mpdu_stt_hp10_fc(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_START_WORD13_ADDR); \
|
|
REG_FIELD_SET(HP10_FC, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_START_WORD13_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_stt_hp10_fc(base) \
|
|
REG_FIELD_GET(HP10_FC, \
|
|
TX_DESC_READ_REG(base, CFG_START_WORD13_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD0_ADDR 0x0000
|
|
/* tx done */
|
|
#define set_tx_mpdu_ed_tx_done(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(TX_DONE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tx_done(base) \
|
|
REG_FIELD_GET(TX_DONE, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
/* tx ok */
|
|
#define set_tx_mpdu_ed_tx_ok(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(TX_OK, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tx_ok(base) \
|
|
REG_FIELD_GET(TX_OK, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
|
|
/* phy error flag */
|
|
#define set_tx_mpdu_ed_phyerr(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(IS_PHYERR, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_phyerr(base) \
|
|
REG_FIELD_GET(IS_PHYERR, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
|
|
/* phy error ID */
|
|
#define set_tx_mpdu_ed_phyerr_id(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(PHYERR_ID, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_phyerr_id(base) \
|
|
REG_FIELD_GET(PHYERR_ID, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
|
|
/* filtered flag */
|
|
#define set_tx_mpdu_ed_is_fted(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(IS_FILTERED, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_is_fted(base) \
|
|
REG_FIELD_GET(IS_FILTERED, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR));
|
|
|
|
/* mac error flag */
|
|
#define set_tx_mpdu_ed_macerr(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(IS_MACERR, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_macerr(base) \
|
|
REG_FIELD_GET(IS_MACERR, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
|
|
/* mac event id */
|
|
#define set_tx_mpdu_ed_macevt_id(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(MAC_EVENT_ID, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_macevt_id(base) \
|
|
REG_FIELD_GET(MAC_EVENT_ID, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
|
|
/* total retry count */
|
|
#define set_tx_mpdu_ed_tt_rtry_cnt(base,value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(TOTAL_RETRY_CNT, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tt_rtry_cnt(base) \
|
|
REG_FIELD_GET(TOTAL_RETRY_CNT, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
|
|
/* sack bitmap */
|
|
#define set_tx_mpdu_ed_sack_bitmap(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD0_ADDR); \
|
|
REG_FIELD_SET(SACK_BITMAP, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_scak_bitmap(base) \
|
|
REG_FIELD_GET(SACK_BITMAP, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD0_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD1_ADDR 0x0004
|
|
/* first try time stamp */
|
|
#define set_tx_mpdu_ed_1st_try_ts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD1_ADDR); \
|
|
REG_FIELD_SET(FIRST_TRY_TS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_1st_try_ts(base) \
|
|
REG_FIELD_GET(FIRST_TRY_TS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD1_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD2_ADDR 0x0008
|
|
/* try0 retry time offset */
|
|
#define set_tx_mpdu_ed_try0_rtrytime_offset(base, value)\
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR); \
|
|
REG_FIELD_SET(TRY0_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD2_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try0_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY0_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, FG_END_WORD2_ADDR))
|
|
|
|
/* try0 tx rtscts */
|
|
#define set_tx_mpdu_end_try0_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR); \
|
|
REG_FIELD_SET(TRY0_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD2_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try0_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY0_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD2_ADDR))
|
|
|
|
/* try0 tx packet */
|
|
#define set_tx_mpdu_ed_try0_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD2_ADDR); \
|
|
REG_FIELD_SET(TRY0_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD2_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try0_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY0_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD2_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD3_ADDR 0x000c
|
|
/* try1 retry time offset */
|
|
#define set_tx_mpdu_ed_try1_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR); \
|
|
REG_FIELD_SET(TRY1_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD3_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try1_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY1_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD3_ADDR))
|
|
|
|
/* try1 tx rtscts */
|
|
#define set_tx_mpdu_ed_try1_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR); \
|
|
REG_FIELD_SET(TRY1_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD3_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try1_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY1_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD3_ADDR))
|
|
|
|
/* try1 tx packet */
|
|
#define set_tx_mpdu_ed_try1_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD3_ADDR); \
|
|
REG_FIELD_SET(TRY1_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD3_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try1_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY1_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD3_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD4_ADDR 0x0010
|
|
/* try2 retry time offset */
|
|
#define set_tx_mpdu_ed_try2_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR); \
|
|
REG_FIELD_SET(TRY2_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD4_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try2_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY2_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD4_ADDR))
|
|
|
|
/* try2 tx rtscts */
|
|
#define set_tx_mpdu_ed_try2_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR); \
|
|
REG_FIELD_SET(TRY2_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD4_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try2_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY2_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD4_ADDR))
|
|
|
|
/* try2 tx packet */
|
|
#define set_tx_mpdu_ed_try2_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD4_ADDR); \
|
|
REG_FIELD_SET(TRY2_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD4_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try2_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY2_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD4_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD5_ADDR 0x0014
|
|
/* try3 retry time offset */
|
|
#define set_tx_mpdu_ed_try3_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR); \
|
|
REG_FIELD_SET(TRY3_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD5_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try3_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY3_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD5_ADDR))
|
|
|
|
/* try3 tx rtscts */
|
|
#define set_tx_mpdu_ed_try3_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR); \
|
|
REG_FIELD_SET(TRY3_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD5_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try3_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY3_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD5_ADDR))
|
|
|
|
/* try3 tx packet */
|
|
#define set_tx_mpdu_ed_try3_tx_pkt(base, alue) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD5_ADDR); \
|
|
REG_FIELD_SET(TRY3_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD5_ADDR, temp);\
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try3_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY3_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD5_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD6_ADDR 0x0018
|
|
/* try4 retry time offset */
|
|
#define set_tx_mpdu_ed_try4_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR); \
|
|
REG_FIELD_SET(TRY4_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD6_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try4_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY4_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD6_ADDR))
|
|
|
|
/* try4 tx rtscts */
|
|
#define set_tx_mpdu_ed_try4_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR); \
|
|
REG_FIELD_SET(TRY4_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD6_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try4_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY4_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD6_ADDR))
|
|
|
|
/* try4 tx packet */
|
|
#define set_tx_mpdu_ed_try4_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD6_ADDR); \
|
|
REG_FIELD_SET(TRY4_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD6_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try4_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY4_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD6_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD7_ADDR 0x001c
|
|
/* try5 retry time offset */
|
|
#define set_tx_mpdu_ed_try5_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR); \
|
|
REG_FIELD_SET(TRY5_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD7_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try5_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY5_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD7_ADDR))
|
|
|
|
/* try5 tx rtscts */
|
|
#define set_tx_mpdu_ed_try5_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR); \
|
|
REG_FIELD_SET(TRY5_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD7_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try5_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY5_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD7_ADDR))
|
|
|
|
/* try5 tx packet */
|
|
#define set_tx_mpdu_ed_try5_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD7_ADDR); \
|
|
REG_FIELD_SET(TRY5_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD7_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try5_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY5_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD7_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD8_ADDR 0x0020
|
|
/* try6 retry time offset */
|
|
#define set_tx_mpdu_ed_try6_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR); \
|
|
REG_FIELD_SET(TRY6_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD8_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try6_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY6_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD8_ADDR))
|
|
|
|
/* try6 tx rtscts */
|
|
#define set_tx_mpdu_ed_try6_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR); \
|
|
REG_FIELD_SET(TRY6_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD8_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try6_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY6_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD8_ADDR))
|
|
|
|
/* try6 tx packet */
|
|
#define set_tx_mpdu_ed_try6_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD8_ADDR); \
|
|
REG_FIELD_SET(TRY6_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD8_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try6_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY6_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD8_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD9_ADDR 0x0024
|
|
/* try7 retry time offset */
|
|
#define set_tx_mpdu_ed_try7_rtrytime_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR); \
|
|
REG_FIELD_SET(TRY7_RETRY_TIME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try7_rtrytime_offset(base) \
|
|
REG_FIELD_GET(TRY7_RETRY_TIME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD9_ADDR))
|
|
|
|
/* try7 tx rtscts */
|
|
#define set_tx_mpdu_ed_try7_tx_rtscts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR); \
|
|
REG_FIELD_SET(TRY7_TX_RTSCTS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try7_tx_rtscts(base) \
|
|
REG_FIELD_GET(TRY7_TX_RTSCTS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD9_ADDR))
|
|
|
|
/* try7 tx packet */
|
|
#define set_tx_mpdu_ed_try7_tx_pkt(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD9_ADDR); \
|
|
REG_FIELD_SET(TRY7_TX_PACKET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD9_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_try7_tx_pkt(base) \
|
|
REG_FIELD_GET(TRY7_TX_PACKET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD9_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD10_ADDR 0x0028
|
|
/* sack time stamp */
|
|
#define set_tx_mpdu_ed_sack_ts(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD10_ADDR); \
|
|
REG_FIELD_SET(SACK_TIMESTAMP, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD10_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_sack_ts(base) \
|
|
REG_FIELD_GET(SACK_TIMESTAMP, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD10_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD11_ADDR 0x002c
|
|
/* pb0 status */
|
|
#define set_tx_mpdu_ed_pb0_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR); \
|
|
REG_FIELD_SET(PB0_STATUS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_pb0_st(base) \
|
|
REG_FIELD_GET(PB0_STATUS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD11_ADDR))
|
|
|
|
/* pb1 status */
|
|
#define set_tx_mpdu_ed_pb1_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR); \
|
|
REG_FIELD_SET(PB1_STATUS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_pb1_st(base) \
|
|
REG_FIELD_GET(PB1_STATUS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD11_ADDR))
|
|
/* pb2 status */
|
|
#define set_tx_mpdu_ed_pb2_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR); \
|
|
REG_FIELD_SET(PB2_STATUS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_pb2_st(base) \
|
|
REG_FIELD_GET(PB2_STATUS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD11_ADDR))
|
|
|
|
/* pb3 status */
|
|
#define set_tx_mpdu_ed_pb3_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD11_ADDR); \
|
|
REG_FIELD_SET(PB3_STATUS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD11_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_pb3_st(base) \
|
|
REG_FIELD_GET(PB3_STATUS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD11_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD12_ADDR 0x0030
|
|
/* tx frame current pointer */
|
|
#define set_tx_mpdu_ed_tx_frm_ptr(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD12_ADDR); \
|
|
REG_FIELD_SET(TX_FRAME_CUR_PTR, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD12_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tx_frm_ptr(base) \
|
|
REG_FIELD_GET(TX_FRAME_CUR_PTR, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD12_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD13_ADDR 0x0034
|
|
/* tx frame byte */
|
|
#define set_tx_mpdu_ed_tx_frm_byte(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD13_ADDR); \
|
|
REG_FIELD_SET(TX_FRAME_BYTE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD13_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tx_frm_byte(base) \
|
|
REG_FIELD_GET(TX_FRAME_BYTE, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD13_ADDR))
|
|
|
|
/* tx frame offset */
|
|
#define set_tx_mpdu_ed_tx_frm_offset(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD13_ADDR); \
|
|
REG_FIELD_SET(TX_FRAME_OFFSET, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD13_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tx_frm_offset(base) \
|
|
REG_FIELD_GET(TX_FRAME_OFFSET, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD13_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD14_ADDR 0x0038
|
|
/* PB status */
|
|
#define set_tx_mpdu_ed_pb_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR); \
|
|
REG_FIELD_SET(PB_STATUS, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, temp);\
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_pb_st(base) \
|
|
REG_FIELD_GET(PB_STATUS, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD14_ADDR))
|
|
/* minmum tx snn */
|
|
#define set_tx_mpdu_ed_min_tx_ssn(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR); \
|
|
REG_FIELD_SET(MINTXSSN, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_min_tx_ssn(base) \
|
|
REG_FIELD_GET(MINTXSSN, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD14_ADDR))
|
|
|
|
/* oldest pb try number */
|
|
#define set_tx_mpdu_ed_oldest_pbtry_num(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR); \
|
|
REG_FIELD_SET(OLDEST_PB_TRY_NUMBER, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_oldest_pbtry_num(base) \
|
|
REG_FIELD_GET(OLDEST_PB_TRY_NUMBER, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD14_ADDR))
|
|
|
|
/* tx window size */
|
|
#define set_tx_mpdu_ed_tx_wsz(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD14_ADDR); \
|
|
REG_FIELD_SET(TXWINDSZ, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD14_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_tx_wsz(base) \
|
|
REG_FIELD_GET(TXWINDSZ, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD14_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_END_WORD15_ADDR 0x003c
|
|
/* MFS cmd */
|
|
#define set_tx_mpdu_ed_mfscmd_st(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_END_WORD15_ADDR); \
|
|
REG_FIELD_SET(MFSCMD_STATE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_END_WORD15_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_mpdu_ed_mfscmd_st(base) \
|
|
REG_FIELD_GET(MFSCMD_STATE, \
|
|
TX_DESC_READ_REG(base, CFG_END_WORD15_ADDR))
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_0_ADDR 0x0000
|
|
/* next pb pointer */
|
|
#define set_tx_pb_stt_next_pb(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_0_ADDR); \
|
|
REG_FIELD_SET(NEXT_PB, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_pb_stt_next_pb(base) \
|
|
REG_FIELD_GET(NEXT_PB, \
|
|
TX_DESC_READ_REG(base, CFG_TX_PB_START_0_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_1_ADDR 0x0004
|
|
/* pb buf addr */
|
|
#define set_tx_pb_stt_pb_buf_addr(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_1_ADDR); \
|
|
REG_FIELD_SET(PB_BUF_ADDR, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_pb_stt_pb_buf_addr(base) \
|
|
REG_FIELD_GET(PB_BUF_ADDR, \
|
|
TX_DESC_READ_REG(base, CFG_TX_PB_START_1_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_2_ADDR 0x0008
|
|
/* sof pb buf */
|
|
#define set_tx_pb_stt_sof_pb_hdr(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_2_ADDR); \
|
|
REG_FIELD_SET(SOF_PB_HEADER, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_2_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_pb_stt_sof_pb_hdr(base) \
|
|
REG_FIELD_GET(SOF_PB_HEADER, \
|
|
TX_DESC_READ_REG(base, CFG_TX_PB_START_2_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_PB_START_3_ADDR 0x000c
|
|
/* pb crc */
|
|
#define set_tx_pb_stt_pb_crc(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_PB_START_3_ADDR); \
|
|
REG_FIELD_SET(SOF_PB_HEADER, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_PB_START_3_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_pb_stt_pb_crc(base) \
|
|
REG_FIELD_GET(SOF_PB_HEADER, \
|
|
TX_DESC_READ_REG(base, CFG_TX_PB_START_3_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_DUMMY_0_ADDR 0x0000
|
|
/* desc type */
|
|
#define set_tx_dummy0_desc_type(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_0_ADDR); \
|
|
REG_FIELD_SET(DESC_TYPE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_DUMMY_0_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_dummy0_desc_type(base) \
|
|
REG_FIELD_GET(DESC_TYPE, \
|
|
TX_DESC_READ_REG(base, CFG_TX_DUMMY_0_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_DUMMY_1_ADDR 0x0004
|
|
/* tx done */
|
|
#define set_tx_dummy1_desc_type(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_1_ADDR); \
|
|
REG_FIELD_SET(TX_DONE, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_DUMMY_1_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_dummy1_desc_type(base) \
|
|
REG_FIELD_GET(TX_DONE, \
|
|
TX_DESC_READ_REG(base, CFG_TX_DUMMY_1_ADDR))
|
|
|
|
//-----------------------------------
|
|
//#define CFG_TX_DUMMY_2_ADDR 0x0008
|
|
/* dummy next */
|
|
#define set_tx_dummy2_next_dummy(base, value) \
|
|
do { \
|
|
uint32_t temp = TX_DESC_READ_REG(base, \
|
|
CFG_TX_DUMMY_2_ADDR); \
|
|
REG_FIELD_SET(DUMMY_NEXT, temp, value); \
|
|
TX_DESC_WRITE_REG(base, CFG_TX_DUMMY_2_ADDR, temp); \
|
|
}while(0)
|
|
|
|
#define get_tx_dummy2_next_dummy(base) \
|
|
REG_FIELD_GET(DUMMY_NEXT, \
|
|
TX_DESC_READ_REG(base, CFG_TX_DUMMY_2_ADDR))
|
|
#endif
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|