635 lines
15 KiB
C
635 lines
15 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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***************************************************************************/
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#include "iot_config.h"
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#include "phy_dump.h"
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#include "phy_bb.h"
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#include "os_types.h"
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#include "hw_reg_api.h"
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#include "iot_io.h"
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#include "phy_reg.h"
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#include "phy_rxtd_reg.h"
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#include "phy_rx_fd_reg.h"
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#include "mac_sys_reg.h"
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#include "iot_errno_api.h"
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#include "hw_tonemask.h"
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#include "phy_ana.h"
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#include "phy_bb.h"
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#include "phy_dfe_reg.h"
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#include "phy_data.h"
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#include "hw_phy_api.h"
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#include "phy_phase.h"
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#include "math.h"
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#include "phy_ana.h"
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#include "math_log10.h"
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#include "hw_phy_api.h"
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#include "phy_dump_hw.h"
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#include "phy_tools.h"
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#include "phy_perf.h"
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uint32_t g_nf_buf[TONE_MAX_NUM] = {0};
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void phy_snr_dump_mode_set(phy_snr_dump_mode_t mode)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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/* select dump mode */
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
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REG_FIELD_SET(SW_SNR_DUMP_MODE,tmp, mode);
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//REG_FIELD_SET(SW_DUMP_DATA_SHIFT,tmp, 3);
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PHY_RX_FD_WRITE_REG(CFG_BB_SNR_ADDR,tmp);
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#else
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(void)mode;
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#endif
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}
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void phy_snr_dump_en(bool_t en)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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/* dump en */
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
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REG_FIELD_SET(SW_SNR_DUMP_EN, tmp, en);
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PHY_RX_FD_WRITE_REG(CFG_BB_SNR_ADDR,tmp);
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#else
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(void)en;
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#endif
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}
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bool_t phy_snr_dump_wait_done()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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int32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
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return REG_FIELD_GET(SW_SNR_DUMP_DONE,tmp);
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#endif
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}
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void phy_spur_dump_en(bool_t en)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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/* dump start */
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SPUR_STAT_ADDR);
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REG_FIELD_SET(SW_SPUR_STAT_START, tmp, en);
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PHY_RX_FD_WRITE_REG(CFG_BB_SPUR_STAT_ADDR,tmp);
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#else
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(void)en;
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#endif
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}
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bool_t phy_spur_dump_wait_done()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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int32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SPUR_STAT_ADDR);
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return REG_FIELD_GET(SW_SPUR_STAT_DONE,tmp);
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#endif
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}
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void phy_sound_dump_cond_set( \
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bool_t snid_en, \
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uint8_t snid, \
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bool_t dtei_en, \
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uint8_t dtei)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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int32_t tmp = 0;
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/* dump en */
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SOUND_DUMP_ADDR);
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REG_FIELD_SET(SW_MATCH_DTEI, tmp, dtei);
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REG_FIELD_SET(SW_MATCH_SNID, tmp, snid);
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REG_FIELD_SET(SW_MATCH_DTEI_EN, tmp, dtei_en);
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REG_FIELD_SET(SW_MATCH_SNID_EN, tmp, snid_en);
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PHY_RX_FD_WRITE_REG(CFG_BB_SOUND_DUMP_ADDR,tmp);
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#else
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(void)snid_en;
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(void)snid;
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(void)dtei_en;
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(void)dtei;
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#endif
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}
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/* snr calibrate */
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uint32_t phy_rx_snr_get( \
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uint32_t start, \
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uint32_t end, \
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int32_t *buf, \
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uint32_t dly_cnt)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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int32_t tmp = 0;
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int32_t snr = 0;
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uint32_t i = 0;
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uint32_t tone_idx = 0;
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/* det start and end tone */
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phy_rxfd_rate0_det(start,end);
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/* select dump mode */
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phy_snr_dump_mode_set(PHY_SNR_DUMP_SNR1);
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phy_snr_dump_en(true);
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/* wait until dump done */
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while(!phy_snr_dump_wait_done())
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{
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if(tmp++ > dly_cnt) {
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return ERR_FAIL;
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}
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}
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/* cal snr for every tone */
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for(tone_idx = start; tone_idx < end; )
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{
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tmp = SOC_READ_REG(BB_SNR_BASEADDR + tone_idx*2);
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#if PHY_DBG_EN
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iot_printf( \
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"[tone id-%d] signal:%d, noise:%d\n"
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"[tone id-%d] signal:%d, noise:%d\n", \
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tone_idx, (tmp >> 8) & 0xff,(tmp >> 0) & 0xff, \
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tone_idx+1, (tmp >> 24) & 0xff,(tmp >> 16) & 0xff);
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#endif
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snr = (int32_t)((( \
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((tmp >> 8) & 0xff) - ((tmp >> 0) & 0xff) \
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) * 3) >> 3);
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buf[i++] = snr;
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snr = (int32_t)((( \
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((tmp >> 24) & 0xff) - ((tmp >> 16) & 0xff) \
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)*3) >> 3);
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buf[i++] = snr;
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tone_idx += 2;
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}
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#else
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(void)start;
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(void)end;
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(void)buf;
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#endif
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return ERR_OK;
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}
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/* softbit dump */
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uint32_t phy_rx_softbit_get( \
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uint32_t start, \
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uint32_t end, \
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int32_t *buf, \
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uint32_t dly_cnt)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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int32_t tmp = 0;
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uint32_t i = 0;
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uint32_t tone_idx = 0;
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/* det start and end tone */
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phy_rxfd_rate0_det(start,end);
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/* select dump mode */
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PHY_WRITE_REG(CFG_BB_INT_CLR_0_EXT_ADDR, 0xffffffff);
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phy_snr_dump_mode_set(PHY_SNR_DUMP_SOFTBIT);
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phy_snr_dump_en(true);
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/* wait until dump done */
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while (!phy_snr_dump_wait_done())
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{
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if (tmp++ > dly_cnt) {
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return ERR_FAIL;
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}
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}
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/* softbit I/Q for every tone */
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for (tone_idx = start; tone_idx < end; )
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{
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tmp = SOC_READ_REG(BB_SNR_BASEADDR + tone_idx*2);
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#if PHY_DBG_EN
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int8_t pwr_i = 0, pwr_q = 0;
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/* tone idx 0 I */
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pwr_i = tmp & 0xff;
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/* tone idx 0 Q */
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pwr_q = (tmp >> 8) & 0xff;
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iot_printf("tone%d softbit:I=%d, Q=%d\n", \
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tone_idx, pwr_i, pwr_q);
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/* tone idx 0 I */
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pwr_i = (tmp >> 16) & 0xff;
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/* tone idx 0 Q */
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pwr_q = (tmp >> 24) & 0xff;
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iot_printf("tone%d softbit:I=%d,Q=%d\n", \
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tone_idx + 1, pwr_i, pwr_q);
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#endif
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buf[i++] = tmp;
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tone_idx += 2;
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}
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#else
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(void)start;
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(void)end;
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(void)buf;
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#endif
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return ERR_OK;
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}
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/* csi calibrate */
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uint32_t phy_rx_csi_get( \
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uint32_t start, \
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uint32_t end, \
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uint32_t *buf, \
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uint32_t dly_cnt)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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uint32_t i = 0;
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uint32_t tone_idx = 0;
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int16_t pwr_i = 0, pwr_q = 0;
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#if MAC_RX_TEST_ID == MAC_RX_CSI_SCAN && \
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HW_PLATFORM >= HW_PLATFORM_SILICON
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/* right shift for signal saturation */
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phy_gain_shift_set(0,0,0,3);
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#endif
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/* det start and end tone */
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phy_rxfd_rate0_det(start,end);
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/* select dump mode */
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phy_snr_dump_mode_set(PHY_SNR_DUMP_CSI);
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phy_snr_dump_en(true);
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/* wait until dump done */
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while(!phy_snr_dump_wait_done())
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{
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if(tmp++ > dly_cnt) {
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return ERR_FAIL;
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}
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}
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/* cal snr for every tone */
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for(tone_idx = start; tone_idx < end; )
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{
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tmp = SOC_READ_REG(BB_SNR_BASEADDR + tone_idx*2);
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/* tone idx 0 I */
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pwr_i = tmp & 0xff;
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if(pwr_i & 0x80) {
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pwr_i = pwr_i - 256;
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}
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/* tone idx 0 Q */
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pwr_q = (tmp >> 8) & 0xff;
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if(pwr_q & 0x80) {
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pwr_q = pwr_q - 256;
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}
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#if PHY_DBG_EN
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iot_printf("tone%d csi:I=%d,Q=%d\n", \
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tone_idx, pwr_i, pwr_q);
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#endif
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buf[i++] = pow(pwr_i, 2) + pow(pwr_q, 2);
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/* tone idx 1 I */
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pwr_i = (tmp >> 16) & 0xff;
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if(pwr_i & 0x80) {
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pwr_i = pwr_i - 256;
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}
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/* tone idx 1 Q */
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pwr_q = (tmp >> 24) & 0xff;
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if(pwr_q & 0x80) {
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pwr_q = pwr_q - 256;
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}
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#if PHY_DBG_EN
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iot_printf("tone%d csi:I=%d,Q=%d\n", \
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tone_idx + 1, pwr_i, pwr_q);
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#endif
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buf[i++] = pow(pwr_i, 2) + pow(pwr_q, 2);
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tone_idx += 2;
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}
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#else
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(void)start;
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(void)end;
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(void)buf;
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#endif
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return 0;
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}
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/* spur cal */
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uint32_t phy_rx_spur_get( \
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uint32_t start, \
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uint32_t end, \
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uint32_t *buf, \
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uint32_t dly_cnt)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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uint32_t tone_idx = 0;
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uint32_t i = 0;
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#if PHY_DBG_EN
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uint32_t start_time = 0, end_time = 0;
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int64_t time_span = 0;
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#endif
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/* det start and end tone */
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phy_rxfd_rate0_det(start,end);
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/* start spur */
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phy_spur_dump_en(true);
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#if PHY_DBG_EN
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/* start time after enable */
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start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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#endif
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/* wait until dump done */
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while (!phy_spur_dump_wait_done()) {
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if (tmp++ > dly_cnt) {
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return ERR_FAIL;
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}
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}
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#if PHY_DBG_EN
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/* end time after done */
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end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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time_span = end_time - start_time;
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/* wrap around */
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if (time_span < 0) {
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time_span = (0x100000000LL) - start_time + end_time;
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}
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iot_printf("[Spur][Elapsed Time] %lldns\r\n", time_span * 40);
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#endif
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/* cal spur for every tone */
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for (tone_idx = start; tone_idx < end; ) {
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tmp = SOC_READ_REG(BB_SNR_BASEADDR + tone_idx * 2);
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buf[i++] = tmp & 0xFFFF;
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buf[i++] = (tmp >> 16) & 0xFFFF;
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tone_idx += 2;
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}
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#else
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(void)start;
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(void)end;
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(void)buf;
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#endif
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return 0;
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}
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/* noise floor cal */
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uint32_t phy_rx_noise_floor_get( \
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uint32_t start, \
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uint32_t end, \
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uint32_t *buf, \
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uint32_t dly_cnt, \
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phy_snr_dump_mode_t mode)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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uint32_t tone_idx = 0;
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uint32_t i = 0;
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#if PHY_DBG_EN
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uint32_t start_time = 0, end_time = 0;
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int64_t time_span = 0;
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#endif
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#if HW_PLATFORM == HW_PLATFORM_SILICON
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/* right shift for signal saturation */
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phy_gain_shift_set(0, 0, 0, 3);
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#endif
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/* det start and end tone */
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phy_rxfd_rate0_det(start,end);
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/* en noise floor */
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phy_snr_dump_mode_set(mode);
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phy_snr_dump_en(true);
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#if PHY_DBG_EN
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/* start time after enable */
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start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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#endif
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/* wait until dump done */
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while(!phy_snr_dump_wait_done())
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{
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if(tmp++ > dly_cnt) {
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return ERR_FAIL;
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}
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}
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#if PHY_DBG_EN
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/* end time after done */
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end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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time_span = end_time - start_time;
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if (time_span < 0) { // wrap around
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time_span = (0x100000000LL) - start_time + end_time;
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}
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iot_printf("[Noise Floor][Elapsed Time] %lldns\r\n", time_span*40);
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#endif
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/* cal noise floor for every tone */
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for(tone_idx = start; tone_idx < end; )
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{
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tmp = SOC_READ_REG(BB_SNR_BASEADDR+tone_idx*2);
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buf[i++] = tmp & 0xFFFF;
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buf[i++] = (tmp >> 16) & 0xFFFF;
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tone_idx += 2;
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}
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#if HW_PLATFORM == HW_PLATFORM_SILICON
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/* recover right shift */
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phy_gain_shift_set(0, 0, 0, 0);
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#endif
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#else
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(void)start;
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(void)end;
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(void)buf;
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#endif
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return 0;
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}
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/* sound dump */
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uint32_t phy_rx_sound_snr_get( \
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uint32_t start, \
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uint32_t end, \
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int32_t *buf, \
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uint32_t dly_cnt)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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int32_t tmp = 0;
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int32_t snr = 0;
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uint32_t i = 0;
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uint32_t tone_idx = 0;
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/* det start and end tone */
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phy_rxfd_rate0_det(start,end);
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/* select dump mode */
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phy_snr_dump_mode_set(PHY_SNR_DUMP_SOUND_EST);
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phy_snr_dump_en(true);
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/* wait until dump done */
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while(!phy_snr_dump_wait_done())
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{
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if(tmp++ > dly_cnt) {
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return ERR_FAIL;
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}
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}
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/* cal snr for every tone */
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for(tone_idx = start; tone_idx < end; )
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{
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tmp = SOC_READ_REG(BB_SNR_BASEADDR + tone_idx*2);
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#if PHY_DBG_EN
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iot_printf( \
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"[tone id-%d] signal:%d, noise:%d\n"
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"[tone id-%d] signal:%d, noise:%d\n", \
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tone_idx, (tmp >> 8) & 0xff,(tmp >> 0) & 0xff, \
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tone_idx+1, (tmp >> 24) & 0xff,(tmp >> 16) & 0xff);
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#endif
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snr = (int32_t)((( \
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((tmp >> 8) & 0xff) - ((tmp >> 0) & 0xff) \
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) * 3) >> 3);
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buf[i++] = snr;
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snr = (int32_t)((( \
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|
((tmp >> 24) & 0xff) - ((tmp >> 16) & 0xff) \
|
|
)*3) >> 3);
|
|
buf[i++] = snr;
|
|
tone_idx += 2;
|
|
}
|
|
#else
|
|
(void)start;
|
|
(void)end;
|
|
(void)buf;
|
|
#endif
|
|
return 0;
|
|
}
|
|
uint32_t phy_rx_noise_dump( \
|
|
uint32_t *buf_ptr, \
|
|
int8_t gain, \
|
|
uint8_t pkt_idx, \
|
|
uint8_t pkt_max)
|
|
{
|
|
uint32_t ret = ERR_OK;
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
|
|
/* check pkt idx and max valid */
|
|
IOT_ASSERT(pkt_idx < pkt_max && pkt_max <= FFT_DUMP_PKT_MAX);
|
|
|
|
/* first dump pkt */
|
|
if(pkt_idx == 0) {
|
|
/* save force value */
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
|
|
g_phy_ctxt.dep.rx_phase_force_en = \
|
|
REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp);
|
|
g_phy_ctxt.dep.rx_phase_force = \
|
|
REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL, tmp);
|
|
|
|
/* fix gain and disable agc */
|
|
phy_agc_gain_lvl_set(1,gain,-24,0);
|
|
|
|
/* enable rx all phase */
|
|
phy_rx_phase_force_set(true, PLC_PHASE_ALL);
|
|
|
|
ret = phy_rx_noise_floor_get(0, TONE_MAX_NUM, g_nf_buf, PHY_DUMP_DLY_CNT, PHY_SNR_DUMP_NF);
|
|
/* disable fix gain */
|
|
phy_agc_gain_lvl_set(0,60,-24,0);
|
|
|
|
if(ret != ERR_OK) {
|
|
iot_printf("file=%s,func=%s,line=%d fail!\n", \
|
|
__FILE__, __FUNCTION__, __LINE__);
|
|
return ret;
|
|
}
|
|
|
|
/* enable sw csi buf access */
|
|
enable_sw_access_csi_buf(1);
|
|
}
|
|
|
|
/* memcpy data from csi buf to buf */
|
|
os_mem_cpy(buf_ptr, \
|
|
g_nf_buf + pkt_idx * (IOT_PHY_CSI_BUF_LEN >> 2), \
|
|
IOT_PHY_CSI_BUF_LEN);
|
|
|
|
/* last dump pkt */
|
|
if(pkt_idx == (pkt_max - 1)) {
|
|
/* enable sw csi buf access */
|
|
enable_sw_access_csi_buf(0);
|
|
|
|
/* recover force */
|
|
phy_rx_phase_force_set( \
|
|
g_phy_ctxt.dep.rx_phase_force_en, \
|
|
g_phy_ctxt.dep.rx_phase_force);
|
|
}
|
|
#else
|
|
(void)buf_ptr;
|
|
(void)gain;
|
|
(void)pkt_idx;
|
|
(void)pkt_max;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
void phy_fft_dump_prepare()
|
|
{
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
uint32_t fft_loop = 1;
|
|
|
|
/* config det tone */
|
|
phy_rxfd_rate0_det(0, TOTAL_TONE_MASK_NUM - 4);
|
|
|
|
/* tone disable */
|
|
phy_dfe_tone_cfg(0,0,0);
|
|
|
|
/* force inte rx state */
|
|
phy_txrx_ovr_set(1,1);
|
|
|
|
/* disable packet detect timeout */
|
|
phy_pkt_time_out_disable(true);
|
|
|
|
/* bypass dc blocker */
|
|
tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
|
|
REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, 1);
|
|
PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);
|
|
|
|
/* disable adj req and sat */
|
|
phy_agc_sat_adj_set(1,1);
|
|
|
|
tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
|
|
REG_FIELD_SET(SW_LOOPBACK_EN, tmp, 1);
|
|
PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
|
|
|
|
/* en adc and rx, disable dac and tx */
|
|
phy_ana_tx_en(false);
|
|
phy_ana_rx_en(true);
|
|
phy_ana_enlic_en(PHY_ENLIC_TXRX_RX);
|
|
|
|
/* trig fft */
|
|
tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
|
|
REG_FIELD_SET(SW_LOOP_FFT_CYCLE, tmp, fft_loop);
|
|
REG_FIELD_SET(SW_LOOP_FFT_START, tmp, 1);
|
|
PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
|
|
#endif
|
|
}
|
|
|
|
void phy_increase_tgt_pwr(uint32_t spur_exist)
|
|
{
|
|
(void)spur_exist;
|
|
}
|
|
|