952 lines
21 KiB
C
952 lines
21 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "ada_reg.h"
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#include "phy_ana.h"
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#include "ahb.h"
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#include "hw_reg_api.h"
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#include "phy_bb.h"
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#include "phy_chn.h"
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#include "phy_rxtd_reg.h"
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#include "phy_rx_fd_reg.h"
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#include "phy_dfe_reg.h"
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#include "iot_io.h"
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#include "hw_phy_api.h"
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#include "phy_reg.h"
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#include "phy_ana_reg.h"
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#include "phy_agc.h"
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#include "phy_ana.h"
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#include "phy_ana_hw.h"
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#include "phy_cal.h"
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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#include "granite_reg.h"
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#endif
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extern uint32_t all_mask_gain_table[];
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/* ada reg clk enable */
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void enable_ada(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* ada rst */
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void warm_rst_ada()
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{
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return;
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}
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/* ada power on enable */
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void phy_ada_enable(uint32_t enable)
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{
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(void)enable;
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return;
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}
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void phy_ada_clk_ratio_cfg(uint8_t data) {
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(void)data;
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}
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/***************************************DAC******************************************/
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/* dac buf size conf */
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void phy_dac_buf_size_cfg(uint32_t size)
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{
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(void)size;
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return;
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}
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/* dac mux conf, 0-DA_B come from phy and DA_A come from tone, 1 reverse */
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void phy_dac_mux_cfg(DA_B_PATH_CFG path)
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{
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(void)path;
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return;
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}
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/* dac clk inv en conf */
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void phy_dac_clk_inv_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* dac enable conf */
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void phy_dac_en_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* dac mux conf */
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void phy_dac_tone_mode_en_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* dac tone num conf */
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void phy_dac_tone_num_cfg(uint32_t tone_num)
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{
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(void)tone_num;
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return;
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}
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/***************************************ADC******************************************/
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/* adc enable conf */
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void phy_adc_en_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* adc mode conf */
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void phy_adc_mode_cfg(ADC_MODE_CFG mode)
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{
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(void)mode;
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return;
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}
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/* adc buf size conf */
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void phy_adc_buf_size_cfg(uint32_t buf_size)
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{
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(void)buf_size;
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return;
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}
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/* adc sample size conf */
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void phy_adc_sample_size_cfg(uint32_t sample_size)
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{
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(void)sample_size;
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return;
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}
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/* adc threshhold conf */
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void phy_adc_thrd_cfg(uint32_t thrd)
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{
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(void)thrd;
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return;
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}
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/* adc clk inv conf */
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void phy_adc_clk_inv_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* adc dmsb inv conf */
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void phy_adc_dmsb_inv_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* adc sample done status */
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bool_t phy_adc_is_sample_done()
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{
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return 1;
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}
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/* adc trig en */
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void phy_adc_trig_en_cfg(uint32_t enable)
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{
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(void)enable;
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return;
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}
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/* adc trig addr */
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uint32_t phy_adc_trig_addr_get()
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{
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uint32_t trig_offset = 0;
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return trig_offset;
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}
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/* get ada power */
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uint32_t phy_ada_get_power_on()
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{
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// TODO: need add.
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return 0;
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}
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/*************************************************************************************/
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/* DAC cfg */
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void phy_ada_tx_cfg(DaTxPara_t *tp)
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{
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/*clk enable*/
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enable_ada(true);
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//warm_rst_ada();
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/* DAC buf size */
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phy_dac_buf_size_cfg(tp->buf_size);
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/* DAC mux */
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phy_dac_mux_cfg(tp->path);
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/* DAC clk inv */
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phy_dac_clk_inv_cfg(tp->inv_en);
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/* dac mux conf */
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phy_dac_tone_mode_en_cfg(tp->tone_mode_en);
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/* dac tone num conf */
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phy_dac_tone_num_cfg(tp->tone_num);
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/* DAC en */
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phy_dac_en_cfg(false);//mode from phy
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}
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/* ADC cfg */
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void phy_ada_rx_cfg(DaRxPara_t *rp)
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{
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/*clk enable*/
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enable_ada(true);
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/* adc mode select */
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phy_adc_mode_cfg(rp->mode);
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/* ADC buf size conf */
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phy_adc_buf_size_cfg(rp->buf_size);
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/* ADC sample size conf */
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phy_adc_sample_size_cfg(rp->sample_size);
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/* ADC threshhold conf */
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phy_adc_thrd_cfg(rp->thrd);
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/* ADC clk inv conf */
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phy_adc_clk_inv_cfg(rp->clk_inv_en);
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/* ADC dmsb inv conf */
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phy_adc_dmsb_inv_cfg(rp->dmsb_inv_en);
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/* ADC en */
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//phy_adc_en_cfg(true);
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/* valid data from bit[0:9] */
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phy_agc_adc_data_set(1,4);
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}
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void phy_ana_tx_set(bool_t tx_en, bool_t dac_en)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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if (phy_tx_dac_en_flag_get()) {
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// sw_tx_dac_en always enable
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dac_en = 1;
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}
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
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REG_FIELD_SET(SW_TX_EN, tmp, tx_en);
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REG_FIELD_SET(SW_TX_DAC_EN, tmp, dac_en);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
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#else
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(void)tx_en;
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(void)dac_en;
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#endif
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}
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void phy_ana_rx_set(bool_t rx_en, bool_t adc_en)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
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REG_FIELD_SET(SW_RX_FE_EN, tmp, rx_en);
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REG_FIELD_SET(SW_ADC_EN, tmp, adc_en);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
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#else
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(void)rx_en;
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(void)adc_en;
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#endif
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}
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void phy_ana_sadc_enable(bool_t enable)//KL2 sadc in soc.
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{
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}
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/* bb ana tx/rx */
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void phy_ana_dfe_init(void)
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{
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uint32_t tmp = 0;
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_ADDR);
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REG_FIELD_SET(SW_TX_START_CFG_DATA, tmp, 0x107);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, tmp);
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_END_CFG_ADDR);
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REG_FIELD_SET(SW_TX_END_CFG_DATA, tmp, 0x107);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_END_CFG_ADDR, tmp);
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_START_CFG_ADDR);
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REG_FIELD_SET(SW_RX_START_CFG_DATA, tmp, 0x2f8);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_CFG_ADDR, tmp);
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_END_CFG_ADDR);
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REG_FIELD_SET(SW_RX_END_CFG_DATA, tmp, 0x2f8);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_END_CFG_ADDR, tmp);
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}
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void phy_ana_set_filter_init(uint32_t band_id)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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(void)band_id;
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uint32_t wdata = 0;
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uint32_t tmp = 0;
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uint32_t end_tone = 0;
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uint32_t start_tone = 0;
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/* get start tone */
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tmp = PHY_READ_REG(CFG_BB_R0_B0_TONE_ADDR);
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start_tone = REG_FIELD_GET(SW_RATE0_BAND0_START_TONE, tmp);
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tmp = PHY_READ_REG(CFG_BB_R1_B0_TONE_ADDR);
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if (start_tone > REG_FIELD_GET(SW_RATE0_BAND0_START_TONE, tmp)) {
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start_tone = REG_FIELD_GET(SW_RATE0_BAND0_START_TONE, tmp);
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}
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if (start_tone <= 32) {
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wdata = 3; /* 500k */
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} else if (start_tone <= 80){
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wdata = 2; /* 1m */
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} else if (start_tone <= 100){
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wdata = 1; /* 2m */
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} else {
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wdata = 0; /* 4m */
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}
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phy_ana_rx_fe_selc_hpf(wdata);
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iot_printf("%s high pass filter set value: %d.\n", __FUNCTION__, wdata);
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/* get end tone */
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tmp = PHY_READ_REG(CFG_BB_R0_B0_TONE_ADDR);
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end_tone = REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp);
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tmp = PHY_READ_REG(CFG_BB_R1_B0_TONE_ADDR);
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if (end_tone < REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp)) {
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end_tone = REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp);
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}
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/* TODO: set mutiband filter */
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if (end_tone <= 120) {
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wdata = 42;
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} else if (end_tone <= 230) {
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wdata = g_phy_ctxt.dep.band_8m_cap_set > 0 ?
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g_phy_ctxt.dep.band_8m_cap_set : 68;
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} else if (end_tone <= 370) {
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wdata = 89; /* rx safe with 12M */
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} else if (end_tone <= 500) {
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wdata = g_phy_ctxt.dep.band_15m_cap_set > 0
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? g_phy_ctxt.dep.band_15m_cap_set : 97;
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} else if (end_tone <= 743) {
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wdata = g_phy_ctxt.dep.band_20m_cap_set > 0 ?
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g_phy_ctxt.dep.band_20m_cap_set : 106;
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} else if (end_tone <= 1000) {
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wdata = 110;
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} else {
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wdata = 115;
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}
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phy_ana_rx_fe_selc_pgf_bq(wdata);
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iot_printf("%s bandwidth filter set value: %d.\n", \
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__FUNCTION__, wdata);
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#else
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(void)band_id;
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#endif
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}
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void phy_sadc_pt_init()//KL2: sadc in soc
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{
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/* not support for kunlun2 */
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}
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void phy_ana_i2c_write(uint32_t reg_id, uint32_t wdata, uint32_t mask)
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{
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(void)reg_id;
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(void)wdata;
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(void)mask;
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}
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void phy_ana_i2c_read(uint32_t reg_id, uint32_t *rdata, uint8_t *rodata)
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{
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(void)reg_id;
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(void)rdata;
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(void)rodata;
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}
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void phy_ana_tx_comp_set(bool_t tx_en)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_CFG_0_ADDR);
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REG_FIELD_SET(SW_TX_COMPEN, tmp, tx_en);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_CFG_0_ADDR, tmp);
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#else
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(void)tx_en;
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#endif
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}
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uint32_t phy_ana_tx_pgacomp_read()
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_CFG_0_ADDR);
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return REG_FIELD_GET(SW_TX_PGACOMP, tmp);
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#else
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return 0;
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#endif
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}
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void phy_ana_tx_gpga_set(uint32_t data)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR);
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REG_FIELD_SET(SW_TX_GPGA, tmp, data);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_GAIN_ADDR, tmp);
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#else
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(void)data;
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#endif
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}
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void phy_ana_rx_pgfloop_set(bool_t en)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
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REG_FIELD_SET(SW_RX_FE_PGFLOOPEN, tmp, en);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
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#else
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(void)en;
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#endif
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}
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void phy_ana_rx_fe_set(bool_t en)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
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REG_FIELD_SET(SW_RX_FE_EN, tmp, en);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
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#else
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(void)en;
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#endif
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}
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void phy_ana_rx_fe_gpga_offset(uint32_t data)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
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REG_FIELD_SET(SW_RX_FE_PGAOFFSET, tmp, data);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
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#else
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(void)data;
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#endif
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}
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void phy_ana_rx_fe_gpga(uint8_t data)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
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REG_FIELD_SET(SW_RX_FE_GPGA, tmp, data);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
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#else
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(void)data;
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#endif
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}
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void phy_ana_rx_bq_qvalue(uint8_t data)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
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REG_FIELD_SET(SW_RX_BQ_QVALUE, tmp, data);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
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#else
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(void)data;
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#endif
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}
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void phy_ana_rx_fe_gbq(uint8_t data)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
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REG_FIELD_SET(SW_RX_FE_GBQ, tmp, data);
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PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
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#else
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(void)data;
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#endif
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}
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void phy_ana_rx_fe_gpgf_offset(uint32_t data)
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{
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#if HW_PLATFORM > HW_PLATFORM_FPGA
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uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_PGFOFFSET, tmp, data);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
|
|
#else
|
|
(void)data;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_fe_gpgf(uint8_t data)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_GPGF, tmp, data);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
|
|
#else
|
|
(void)data;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_fe_hpfenord2_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_HPFENORD2, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_fe_byphpf_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_BYPHPF, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_fe_pwdpgf_offset_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_PWDPGFOFFSET, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
void phy_ana_rx_fe_pwdpga_offset_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_PWDPGAOFFSET, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_glna(uint8_t data)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
|
|
REG_FIELD_SET(SW_RX_GLNA, tmp, data);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
|
|
#else
|
|
(void)data;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_pga_gain_set(uint32_t val)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR);
|
|
REG_FIELD_SET(SW_TX_GPGA, tmp, val);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_GAIN_ADDR, tmp);
|
|
#else
|
|
(void)val;
|
|
#endif
|
|
}
|
|
|
|
uint32_t phy_ana_pga_gain_get(void)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
return (uint32_t)REG_FIELD_GET(SW_TX_GPGA,
|
|
PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR));
|
|
#else
|
|
return 3;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_tx_en(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
|
|
uint32_t tmp = 0;
|
|
uint8_t sw_tx_dac_en;
|
|
|
|
if (phy_tx_dac_en_flag_get()) {
|
|
// sw_tx_dac_en always enable
|
|
sw_tx_dac_en = 1;
|
|
} else {
|
|
sw_tx_dac_en = en;
|
|
}
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_TX_EN, tmp, en);
|
|
REG_FIELD_SET(SW_TX_DAC_EN, tmp, sw_tx_dac_en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
|
|
}
|
|
|
|
void phy_ana_rx_en(bool_t en)
|
|
{
|
|
#if HW_PLATFORM == HW_PLATFORM_SILICON
|
|
uint32_t tmp = 0;
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_EN, tmp, en);
|
|
REG_FIELD_SET(SW_ADC_EN, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_enlic_en(uint8_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp =0 ;
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ENLIC_RX, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ENLIC_TX, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
|
|
}
|
|
|
|
void phy_ana_dbg_print()
|
|
{
|
|
#if HW_PLATFORM == HW_PLATFORM_SILICON
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_CFG_0_ADDR);
|
|
iot_printf("Analog rx0:0x%x, ", tmp);
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
|
|
iot_printf("tx6:0x%x, ", tmp);
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
iot_printf("top10:0x%x\n", tmp);
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_tx_en(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_TX_EN, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_rx_en(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_EN, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_adc_en(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ADC_EN, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_dac_en(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
|
|
if (phy_tx_dac_en_flag_get()) {
|
|
// sw_tx_dac_en always enable
|
|
en = 1;
|
|
}
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_TX_DAC_EN, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_enlic_rx_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ENLIC_RX, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_enlic_tx_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ENLIC_TX, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_top_reset_n_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ADC_RESET_N, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_fe_selc_hpf(uint8_t data)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
|
|
REG_FIELD_SET(SW_RX_FE_SELC_HPF, tmp, data);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
|
|
#else
|
|
(void)data;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_rx_fe_selc_pgf_bq(uint8_t data)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_CFG0_ADDR);
|
|
/* fixed pgf filter value 109 (26.58MHz) */
|
|
REG_FIELD_SET(SW_RX_FE_PGF_SELC, tmp, 115);
|
|
REG_FIELD_SET(SW_RX_FE_BQ_SELC1, tmp, data);
|
|
REG_FIELD_SET(SW_RX_FE_BQ_SELC2, tmp, data);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_CFG0_ADDR, tmp);
|
|
#else
|
|
(void)data;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_adc_set(bool_t en)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
|
|
REG_FIELD_SET(SW_ADC_EN, tmp, en);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
|
|
#else
|
|
(void)en;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_bias_ic0_cfg(uint32_t value)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC0_ADDR);
|
|
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT0, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC0_ADDR, tmp);
|
|
#else
|
|
(void)value;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_bias_ic1_cfg(uint32_t value)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC1_ADDR);
|
|
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT1, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC1_ADDR, tmp);
|
|
#else
|
|
(void)value;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_bias_ir0_cfg(uint32_t value)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR0_ADDR);
|
|
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT0, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR0_ADDR, tmp);
|
|
#else
|
|
(void)value;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_bias_ir1_cfg(uint32_t value)
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR1_ADDR);
|
|
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT1, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR1_ADDR, tmp);
|
|
#else
|
|
(void)value;
|
|
#endif
|
|
}
|
|
|
|
void phy_ana_hw_en_bitmap(uint32_t value)
|
|
{
|
|
uint32_t tmp;
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_HWEN_ADDR);
|
|
REG_FIELD_SET(SW_TOP_HW_EN, tmp, value);
|
|
if (phy_tx_dac_en_flag_get()) {
|
|
// sw_tx_dac_en always sw ctrl
|
|
REG_FIELD_SET(SW_TX_DAC_EN_HW_EN, tmp, 0);
|
|
}
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_HWEN_ADDR, tmp);
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RXGAIN_HWEN_ADDR);
|
|
REG_FIELD_SET(SW_RXGAIN_HW_EN, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_RXGAIN_HWEN_ADDR, tmp);
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TXGAIN_HWEN_ADDR);
|
|
REG_FIELD_SET(SW_TXGAIN_HW_EN, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_TXGAIN_HWEN_ADDR, tmp);
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_EXT0_HWEN_ADDR);
|
|
REG_FIELD_SET(SW_EXT0_HW_EN, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_EXT0_HWEN_ADDR, tmp);
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_EXT1_HWEN_ADDR);
|
|
REG_FIELD_SET(SW_EXT1_HW_EN, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_EXT1_HWEN_ADDR, tmp);
|
|
|
|
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_EXT2_HWEN_ADDR);
|
|
REG_FIELD_SET(SW_EXT2_HW_EN, tmp, value);
|
|
PHY_ANA_WRITE_REG(CFG_BB_ANA_EXT2_HWEN_ADDR, tmp);
|
|
}
|
|
|
|
void phy_ana_filter_set(uint8_t val)
|
|
{
|
|
/* TODO: update as soon as possible */
|
|
}
|
|
|
|
/* get the gain table */
|
|
void phy_pgf_bq_pga_gain_get(uint16_t gain_idx, \
|
|
volatile uint8_t *pgf, \
|
|
volatile uint8_t *bq, \
|
|
volatile uint8_t *pga, \
|
|
volatile uint8_t *lna, \
|
|
volatile uint8_t *byphpf, \
|
|
volatile uint8_t *enord2, \
|
|
volatile uint8_t *bq_qvalue)
|
|
{
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
|
uint32_t tmp = 0;
|
|
|
|
IOT_ASSERT(gain_idx < 170);
|
|
|
|
tmp = all_mask_gain_table[gain_idx];
|
|
*pgf = REG_FIELD_GET(SW_RX_FE_GPGF, tmp);
|
|
*bq = REG_FIELD_GET(SW_RX_FE_GBQ, tmp );
|
|
*pga = REG_FIELD_GET(SW_RX_FE_GPGA, tmp);
|
|
*lna = REG_FIELD_GET(SW_RX_GLNA , tmp);
|
|
*byphpf = REG_FIELD_GET(SW_RX_FE_BYPHPF, tmp);
|
|
*enord2 = REG_FIELD_GET(SW_RX_FE_HPFENORD2, tmp);
|
|
*bq_qvalue = REG_FIELD_GET(SW_RX_BQ_QVALUE, tmp);
|
|
|
|
#else
|
|
(void)gain_idx;
|
|
(void)pgf;
|
|
(void)bq;
|
|
(void)pga;
|
|
(void)lna;
|
|
(void)byphpf;
|
|
(void)enord2;
|
|
(void)bq_qvalue;
|
|
#endif
|
|
}
|
|
|