113 lines
2.5 KiB
C
Executable File
113 lines
2.5 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "os_types.h"
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#include "iot_img_hdr.h"
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#include "os_mem.h"
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#include "iot_wdg.h"
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#include "iot_io.h"
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#include "dbg_io.h"
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#include "clk.h"
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#include "ahb.h"
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#include "ddrc.h"
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#include "flash.h"
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#include "ana.h"
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#define APP_RAM_ADDR 0x0ffe0000
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#define APP_FLASH_ADDR 0x1c008000
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#define REG32(a) (*((volatile uint32_t *)(a)))
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//#define SP_DEBUG_UART_PORT 3
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static int app_image_copy( )
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{
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uint8_t *dst= (uint8_t*)APP_RAM_ADDR;
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uint8_t *src = (uint8_t*)APP_FLASH_ADDR;
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static char block[64];
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imgHdr hdr = {0};
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os_mem_cpy(block, src, sizeof(imgHdr));
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img_header_construct(&hdr, block);
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os_mem_cpy(dst, src + sizeof(imgHdr), iot_imghdr_get_imgSize(&hdr));
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return 0;
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}
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static int app_core_start()
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{
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ahb_core0_set_start(APP_RAM_ADDR);
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ahb_core0_enable();
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ahb_core0_reset();
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return 0;
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}
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void sp_boot_hw_init()
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{
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//disable auto-baud;
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REG32(0x44001020) &= ~0x1;
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REG32(0x50000008) |= 0x80;
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//change CPU core to 150M.
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clk_core_freq_set(CPU_FREQ_150M);
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//uart init;
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//dbg_uart_init_port(3, 1);
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//flash init;
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flash_init(1);
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// disable cache
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ahb_cache_disable();
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#if RUN_IN_PSRAM
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//ddr init;
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ddr_cache_init();
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#else
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ahb_set_cache_buffer_mode();
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#endif
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// enable ahb cache
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ahb_cache_enable();
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//ahb_cache_reset();
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#if RUN_IN_PSRAM
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//enable dmc cache;
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ahb_dmc_cache_enable();
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#endif
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//cache space init;
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ahb_cache_fill_valid_space();
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}
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void sp_boot_load_sbl()
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{
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app_image_copy();
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app_core_start();
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}
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void sp_boot_main_loop()
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{
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//disable cpu1's wdt;
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wdg_deinit(HAL_WDG_CPU_1);
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while(1){
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__asm volatile ("nop");
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}
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}
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