668 lines
21 KiB
C
Executable File
668 lines
21 KiB
C
Executable File
/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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#include "os_types.h"
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#include "chip_reg_base.h"
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#include "hw_reg_api.h"
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#include "ate_main.h"
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#include "iot_bitops.h"
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#include "dbg_io.h"
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#include "iot_io.h"
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#include "iot_clock.h"
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#include "gp_timer.h"
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#include "phy_cal.h"
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#include "mac_rx_test.h"
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#include <string.h>
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#include "phy_bb.h"
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#include "plc_protocol.h"
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#include "plc_mpdu_header.h"
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#include "granite_reg.h"
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#include "phy_dfe_reg.h"
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#include "phy_ana_glb.h"
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#include "phy_ana.h"
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#include "clk.h"
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#include "math_log10.h"
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#include "efuse.h"
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#include "efuse_mapping.h"
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#include "hw_phy_init.h"
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#include "mac_reset.h"
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//#include "sadc_t.h"
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#include "ahb_rf.h"
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#include "apb_glb_reg.h"
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#include "mac_sys_reg.h"
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#include "os_mem.h"
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#include "iot_errno.h"
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#include "wdg_reg.h"
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#include "watchdog.h"
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#include "phy_rxtd_reg.h"
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#include "phy_phase.h"
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#include "phy_tools.h"
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#include "hal_rx.h"
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#include "sfc_rf.h"
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#include "sfc.h"
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#include "flash.h"
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#include "gpio_mtx.h"
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#include "apb.h"
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#include "iot_gpio_api.h"
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#include "sadc_hw.h"
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#include "sadc_t.h"
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#include "hal_sadc.h"
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#include "ana_pmu_wrap_rf.h"
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#include "hw_sadc.h"
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#include "iot_wdg_api.h"
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/* ate global structure */
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ate_info_t *glb_ate_info = (ate_info_t *) 0xfff8000;//0x73FC2000
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/********************************************************************************
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Test item
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TX gain setting
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sw_tone_0_att sw_tx_pwr_scale TX_PGA_gain
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RX gain setting
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RX_PGF_gain RX_BQ_gain RX_PGA_gain sw_rx_gain_shift CSI_power(I^2+Q^2)(dBLSB)
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TX gain
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-24 0 -4.53 -6 0 0 0 70.269
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-24 0 1.47 -6 0 0 1 70.269
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-24 0 7.47 -6 0 0 2 70.269
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-24 0 13.47 -6 0 0 3 70.269
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RX gain
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-24 0 1.47 -6 0 0 1 70.269
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-24 0 1.47 -6 -6 12 2 70.269
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-24 0 1.47 -6 12 0 3 70.269
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-24 0 1.47 -6 0 6 2 70.269
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TX PGA
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0~3 -4.5， 1.5， 7.5， 13.5
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********************************************************************************/
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ate_loop_back_gain_list_t ate_granite_lpbk_gain_list[] =
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{
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{1, 0, 0, 0, 1, 0, 1, 0},
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{2, 0, 1, 0, 1, 0, 1, 0},
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{3, 0, 2, 0, 1, 0, 0, 0},
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{4, 0, 3, 0, 1, 0, 0, 0},
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{1, 0, 0, 0, 1, 0, 0, 0},
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{2, 0, 0, 0, 0, 8, 0, 0},
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{3, 0, 1, 0, 1, 4, 0, 0},
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{4, 0, 1, 0, 3, 0, 0, 0},
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};
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/*tx_tone_att, tx_factor, tx_pga_gain, rx_pgf_gain, rx_bq_gain, rx_pga_gain, rx_shift, rx_lna_gain*/
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ate_loop_back_gain_list_t ate_geode_lpbk_gain_list[] =
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{
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{1, 0, 1, 3, 0, 0, 0, 1},
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{1, 0, 1, 2, 0, 0, 0, 2},
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{1, 0, 1, 1, 0, 0, 0, 3},
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{1, 0, 1, 0, 0, 0, 0, 4},
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{1, 0, 0, 0, 0, 0, 0, 5},
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{2, 0, 0, 0, 0, 0, 0, 6},
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{3, 0, 0, 0, 0, 0, 0, 7},
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};
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/* initialize ate */
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void ate_init(void)
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{
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uint32_t tmp = 0;
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/* init global info */
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memset(glb_ate_info, 0, sizeof(ate_info_t));
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/* change clk to 150M */
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clk_core_freq_set(CPU_FREQ_150M);
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gp_timer_init();
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gp_timer_enable(0,0,0);
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/* alloc 1K size ram */
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os_mem_init((uint8_t *)0xffffc00, 0x1000);
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/* eb clk */
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tmp = 0xFFFFFFFF;
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AHB_RF_WRITE_REG(CFG_AHB_REG1_ADDR, tmp);
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/* sadc eb */
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tmp = APB_GLB_READ_REG(CFG_APB_GLB_GEN0_ADDR);
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REG_FIELD_SET(SADC_EB, tmp, 1);
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APB_GLB_WRITE_REG(CFG_APB_GLB_GEN0_ADDR, tmp);
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/* basic data struct init for bit ops */
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iot_bitops_init();
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/* reset mac */
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mac_reset(MAC_RST_REASON_COLD);
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/* reset phy */
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phy_reset(PHY_RST_REASON_COLD);
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/* reset mac */
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mac_reset(MAC_RST_REASON_COLD);
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/* phy param init */
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phy_param_init(PHY_PROTO_TYPE_GET());
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iot_wdg_enable();
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/* print software version */
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iot_printf("[ATE]software version:%s\r\n", ATE_SW_VER);
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}
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uint32_t mac_granite_loop_back()
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{
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uint32_t ret = ERR_OK;
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uint32_t tmp = 0;
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uint32_t tone_idx = 0;
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uint32_t fft_loop = 1;
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int16_t csi_i = 0, csi_q = 0;
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uint32_t golden_data = 0, noise_data = 0;
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uint32_t *csi_buf = (uint32_t *)BB_CSI_BASEADDR;
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/* reset phy */
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phy_reset(PHY_RST_REASON_WARM);
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/* Must cfg start adn end tone */
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mac_rx_init(IOT_PLC_PHY_BAND_DFT);
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/* config det tone */
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phy_rxfd_rate0_det(0, TOTAL_TONE_MASK_NUM - 4);
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phy_rxfd_rate1_det(0, TOTAL_TONE_MASK_NUM - 4);
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#if IOT_DTEST_ONLY_SUPPORT == 1
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/* tone 3M */
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phy_dfe_tone_cfg(1, 41, 0);
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/* att */
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phy_dfe_tone_att_cfg(0, 3, 3);
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#endif
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/* sw control tx rx */
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phy_ana_hw_en_bitmap(0);
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/* enable ana loopback */
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phy_txrx_loop_back_begin(0, TXRX_LOOP_BACK_GRANITE);
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for(uint32_t i = 0; \
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i < sizeof(ate_granite_lpbk_gain_list)/sizeof(ate_loop_back_gain_list_t); i++)
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{
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/* tone atten and tx factor */
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phy_dfe_tone_att_cfg(0, ate_granite_lpbk_gain_list[i].tx_tone_att, 0);
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//*(uint32_t *)0x51c00404 = ate_granite_lpbk_gain_list[i].tx_tone_att;
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phy_tx_gain_factor_set(ate_granite_lpbk_gain_list[i].tx_factor);
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/* tx pga */
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phy_ana_rx_fe_gpga(ate_granite_lpbk_gain_list[i].tx_pga_gain);
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/* rx pgf bq pga*/
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phy_ana_rx_fe_gpgf(ate_granite_lpbk_gain_list[i].rx_pgf_gain);
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phy_ana_rx_fe_gbq(ate_granite_lpbk_gain_list[i].rx_bq_gain);
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phy_ana_rx_fe_gpga(ate_granite_lpbk_gain_list[i].rx_pga_gain);
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/* rx scale */
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if (ate_granite_lpbk_gain_list[i].rx_gain_shift > 0) {
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phy_gain_shift_set(0, 0, 0, ate_granite_lpbk_gain_list[i].rx_gain_shift);
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} else {
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ate_granite_lpbk_gain_list[i].rx_gain_shift = -ate_granite_lpbk_gain_list[i].rx_gain_shift;
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phy_gain_shift_set(0, 0, 1, ate_granite_lpbk_gain_list[i].rx_gain_shift);
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}
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/* trig fft */
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tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
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REG_FIELD_SET(SW_LOOP_FFT_CYCLE, tmp, fft_loop);
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REG_FIELD_SET(SW_LOOP_FFT_START, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
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/* wait fft done */
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do{
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tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
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}while(!REG_FIELD_GET(LOOP_FFT_DONE, tmp));
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/* enable sw csi buf access */
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enable_sw_access_csi_buf(1);
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/* get tone power */
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tone_idx = ATE_TONE_3M;
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csi_i = (int16_t)(*(csi_buf + tone_idx * 3) & 0xFFFF);
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csi_q = (int16_t)(*(csi_buf + tone_idx * 3) >> 16);
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golden_data = csi_i * csi_i + csi_q * csi_q;
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noise_data = 0;
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/* cal csi for every tone */
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for(tone_idx = 6; tone_idx < TONE_MAX_NUM; tone_idx++)
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{
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if (tone_idx != ATE_TONE_3M * 3) {
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csi_i = (int16_t)(*(csi_buf + tone_idx) & 0xFFFF);
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csi_q = (int16_t)(*(csi_buf + tone_idx) >> 16);
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noise_data += csi_i * csi_i + csi_q * csi_q;
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} else {
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csi_i = (int16_t)(*(csi_buf + tone_idx) & 0xFFFF);
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csi_q = (int16_t)(*(csi_buf + tone_idx) >> 16);
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}
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#if ATE_DEBUG_LEVEL > 1
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iot_printf("%d,%d,%d\r\n", tone_idx, csi_i, csi_q);
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#endif
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}
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/* enable sw csi buf access */
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enable_sw_access_csi_buf(0);
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/* get AMP(-30dB) and SNR */
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glb_ate_info->csi_amp[i] = 10 * mlog10(golden_data/1000);
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glb_ate_info->csi_snr[i] = 10 * mlog10(golden_data/noise_data);
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if (glb_ate_info->csi_snr[i] >= 15) {
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iot_printf("[ATE]Granite AMP %d, snr %d, ###success###\r\n", \
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glb_ate_info->csi_amp[i], glb_ate_info->csi_snr[i]);
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} else {
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iot_printf("[ATE]Granite AMP %d, snr %d, ###fail###\r\n", \
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glb_ate_info->csi_amp[i], glb_ate_info->csi_snr[i]);
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ret = ERR_FAIL;
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}
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}
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/* recover to the state set in ana loopback */
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phy_txrx_loop_back_end();
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/* hw control tx rx */
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phy_ana_hw_en_bitmap(~0);
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return ret;
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}
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uint32_t mac_geode_loop_back()
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{
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uint32_t ret = ERR_OK;
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uint32_t tmp = 0;
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uint32_t tone_idx = 0;
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uint32_t fft_loop = 1;
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int16_t csi_i = 0, csi_q = 0;
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uint32_t golden_data = 0, noise_data = 0;
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uint32_t *csi_buf = (uint32_t *)BB_CSI_BASEADDR;
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/* reset phy */
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phy_reset(PHY_RST_REASON_WARM);
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/* cfg det tone range */
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phy_rxfd_rate0_det(0, TOTAL_TONE_MASK_NUM - 4);
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phy_rxfd_rate1_det(0, TOTAL_TONE_MASK_NUM - 4);
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/* tone 3M */
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phy_dfe_tone_cfg(1, ATE_TONE_3M, 0);
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/* sw control tx rx */
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phy_ana_hw_en_bitmap(0);
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/* ovr phase A/B/C */
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tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_0_ADDR);
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REG_FIELD_SET(SW_ENLIC_A_OVR_EN, tmp, 1);
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REG_FIELD_SET(SW_ENLIC_A_OVR, tmp, 3);
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REG_FIELD_SET(SW_ENLIC_B_OVR_EN, tmp, 1);
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REG_FIELD_SET(SW_ENLIC_B_OVR, tmp, 3);
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REG_FIELD_SET(SW_ENLIC_C_OVR_EN, tmp, 1);
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REG_FIELD_SET(SW_ENLIC_C_OVR, tmp, 3);
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PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_0_ADDR, tmp);
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/* enable ana lic tx rx */
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phy_ana_top_enlic_rx_set(1);
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phy_ana_top_enlic_tx_set(1);
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/* enable ana loopback */
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phy_txrx_loop_back_begin(0, TXRX_LOOP_BACK_GEODE);
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for(uint32_t i = 0; \
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i < sizeof(ate_geode_lpbk_gain_list)/sizeof(ate_loop_back_gain_list_t); i++)
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{
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#if ATE_DEBUG_LEVEL >= 0
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iot_printf("att:%d,factor:%d,tx_pga:%d,rx_pgf:%d,rx_bq:%d,rx_pga:%d,rx_shift:%d,lna:%d\r\n", \
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ate_geode_lpbk_gain_list[i].tx_tone_att, \
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ate_geode_lpbk_gain_list[i].tx_factor, \
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ate_geode_lpbk_gain_list[i].tx_pga_gain, \
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ate_geode_lpbk_gain_list[i].rx_pgf_gain, \
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ate_geode_lpbk_gain_list[i].rx_bq_gain, \
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ate_geode_lpbk_gain_list[i].rx_pga_gain, \
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ate_geode_lpbk_gain_list[i].rx_gain_shift, \
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ate_geode_lpbk_gain_list[i].rx_lna_gain);
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#endif
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/* tone atten and tx factor */
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phy_dfe_tone_att_cfg(0, ate_geode_lpbk_gain_list[i].tx_tone_att, 0);
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*(uint32_t *)0x51c00404=ate_geode_lpbk_gain_list[i].tx_tone_att;
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phy_tx_gain_factor_set(ate_geode_lpbk_gain_list[i].tx_factor);
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/* tx pga */
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phy_ana_rx_fe_gpga(ate_granite_lpbk_gain_list[i].tx_pga_gain);
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/* rx pgf bq pga*/
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phy_ana_rx_fe_gpgf(ate_granite_lpbk_gain_list[i].rx_pgf_gain);
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phy_ana_rx_fe_gbq(ate_granite_lpbk_gain_list[i].rx_bq_gain);
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phy_ana_rx_fe_gpga(ate_granite_lpbk_gain_list[i].rx_pga_gain);
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/* rx lna */
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phy_ana_rx_glna(ate_geode_lpbk_gain_list[i].rx_lna_gain);
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/* rx scale */
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if (ate_geode_lpbk_gain_list[i].rx_gain_shift > 0) {
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phy_gain_shift_set(0, 0, 0, ate_geode_lpbk_gain_list[i].rx_gain_shift);
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} else {
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ate_geode_lpbk_gain_list[i].rx_gain_shift = 0 - ate_geode_lpbk_gain_list[i].rx_gain_shift;
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phy_gain_shift_set(0, 0, 1, ate_geode_lpbk_gain_list[i].rx_gain_shift);
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}
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/* trig fft */
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tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
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REG_FIELD_SET(SW_LOOP_FFT_CYCLE, tmp, fft_loop);
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REG_FIELD_SET(SW_LOOP_FFT_START, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
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/* wait fft done */
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do{
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tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
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}while(!REG_FIELD_GET(LOOP_FFT_DONE, tmp));
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/* enable sw csi buf access */
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enable_sw_access_csi_buf(1);
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/* get tone power */
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tone_idx = ATE_TONE_3M;
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csi_i = (int16_t)(*(csi_buf + tone_idx * 3) & 0xFFFF);
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csi_q = (int16_t)(*(csi_buf + tone_idx * 3) >> 16);
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golden_data = csi_i * csi_i + csi_q * csi_q;
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noise_data = 0;
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/* cal csi for every tone */
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for(tone_idx = 6; tone_idx < TONE_MAX_NUM; tone_idx++)
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{
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if(tone_idx != ATE_TONE_3M * 3){
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csi_i = (int16_t)(*(csi_buf + tone_idx) & 0xFFFF);
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csi_q = (int16_t)(*(csi_buf + tone_idx) >> 16);
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noise_data += csi_i * csi_i + csi_q * csi_q;
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#if 0
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iot_printf("%d %d \n", tone_idx, csi_i * csi_i + csi_q * csi_q);
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#endif
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} else {
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csi_i = (int16_t)(*(csi_buf + tone_idx) & 0xFFFF);
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csi_q = (int16_t)(*(csi_buf + tone_idx) >> 16);
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#if 0
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iot_printf("%d %d \n", tone_idx, csi_i * csi_i + csi_q * csi_q);
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#endif
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}
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}
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/* disable sw csi buf access */
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enable_sw_access_csi_buf(0);
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//iot_printf("golden_data %d noise_data %d \n", golden_data, noise_data);
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/* get AMP(-30dB) and SNR */
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glb_ate_info->csi_amp[8+i] = 10 * mlog10(golden_data/1000);
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glb_ate_info->csi_snr[8+i] = 10 * mlog10(golden_data/noise_data);
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if (glb_ate_info->csi_snr[8+i] >= 10) {
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iot_printf("[ATE]geode amp %d, snr %d, ###success###\r\n", \
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glb_ate_info->csi_amp[8+i], glb_ate_info->csi_snr[8+i]);
|
||
} else {
|
||
iot_printf("[ATE]geode amp %d, snr %d, ###fail###\r\n", \
|
||
glb_ate_info->csi_amp[8+i], glb_ate_info->csi_snr[8+i]);
|
||
ret = ERR_FAIL;
|
||
}
|
||
|
||
}
|
||
|
||
/* recover to the state set in ana loopback */
|
||
phy_txrx_loop_back_end();
|
||
|
||
/* hw control tx rx */
|
||
phy_ana_hw_en_bitmap(~0);
|
||
|
||
return ret;
|
||
}
|
||
|
||
uint32_t ate_nf_test()
|
||
{
|
||
uint32_t tmp = 0;
|
||
uint32_t ret = ERR_OK;
|
||
uint32_t valid_nf_num = 0;
|
||
uint32_t nf_tmp = 0;
|
||
uint32_t idx = 0;
|
||
|
||
/* reset phy reg */
|
||
phy_reset(PHY_RST_REASON_COLD);
|
||
|
||
/* fix 60dB gain */
|
||
phy_agc_gain_lvl_set(1, 60, -24, 0);
|
||
|
||
/* disable packet detect timeout */
|
||
tmp = PHY_RXTD_READ_REG(CFG_BB_PKT_TIME_OUT_ADDR);
|
||
REG_FIELD_SET(SW_PKT_DET_TIME_OUT_DISABLE, tmp, 0);
|
||
PHY_RXTD_WRITE_REG(CFG_BB_PKT_TIME_OUT_ADDR, tmp);
|
||
|
||
/* disable reset by full */
|
||
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR);
|
||
REG_FIELD_SET(SW_ADJ_REQ_DIS, tmp, 0);
|
||
REG_FIELD_SET(SW_SAT_DIS, tmp, 0);
|
||
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR, tmp);
|
||
|
||
/* ad/da bits shift */
|
||
phy_gain_shift_set(0, 0, 0, 0);
|
||
tmp = PHY_DFE_READ_REG(CFG_BB_AGC_SWCFG_EN_ADDR);
|
||
REG_FIELD_SET(SW_AR1540_EN, tmp, 0x0);
|
||
PHY_DFE_WRITE_REG(CFG_BB_AGC_SWCFG_EN_ADDR, tmp);
|
||
|
||
/* config default RX ON regsiter */
|
||
phy_agc_gain_adj_dis(0xE7FFC0FF);
|
||
|
||
/* sw control tx rx */
|
||
phy_ana_hw_en_bitmap(0);
|
||
|
||
/* en adc and rx, disable dac and tx */
|
||
phy_ana_top_tx_en(0);
|
||
phy_ana_top_rx_en(1);
|
||
phy_ana_top_adc_en(1);
|
||
phy_ana_top_dac_en(0);
|
||
phy_ana_top_enlic_rx_set(1);
|
||
phy_ana_top_enlic_tx_set(0);
|
||
|
||
/* force phy in rx state */
|
||
phy_txrx_ovr_set(true, 1);
|
||
/* enable geode */
|
||
phy_phase_ovr_set(PHY_PHASE_OVR_A, true, PHY_TXRX_OVR_RX);
|
||
phy_phase_ovr_set(PHY_PHASE_OVR_B, true, PHY_TXRX_OVR_RX);
|
||
phy_phase_ovr_set(PHY_PHASE_OVR_C, true, PHY_TXRX_OVR_RX);
|
||
|
||
/* disable tone */
|
||
phy_dfe_tone_cfg(0, 0, 0);
|
||
/* diable analog loopen */
|
||
phy_ana_rx_pgfloop_set(0);
|
||
|
||
/* rx pgf bq pga*/
|
||
phy_ana_rx_fe_gpgf(1);
|
||
phy_ana_rx_fe_gbq(1);
|
||
phy_ana_rx_fe_gpga(0);
|
||
phy_ana_rx_fe_gpga_offset(PHY_RX_PGA_OFFSET_DFT);
|
||
phy_ana_rx_fe_gpgf_offset(PHY_RX_PGF_OFFSET_DFT);
|
||
phy_ana_rx_fe_hpfenord2_set(0);
|
||
phy_ana_rx_fe_byphpf_set(0);
|
||
phy_ana_rx_fe_pwdpgf_offset_set(0);
|
||
phy_ana_rx_fe_pwdpga_offset_set(0);
|
||
|
||
glb_ate_info->nf = 0;
|
||
/* nf get */
|
||
for (idx = 0; idx < PHY_NF_RTY_CNT; idx++)
|
||
{
|
||
nf_tmp = phy_rx_nf_by_rxtd_get(14);
|
||
/*121 is reset value, not valid value*/
|
||
if (nf_tmp != PHY_NF_RST_VAL) {
|
||
glb_ate_info->nf += nf_tmp;
|
||
//iot_printf("[ATE]nf:%d\n", nf_tmp);
|
||
valid_nf_num++;
|
||
}
|
||
}
|
||
glb_ate_info->nf = glb_ate_info->nf/valid_nf_num;
|
||
if (glb_ate_info->nf >= 30) {
|
||
iot_printf("[ATE] current nf:%d ###fail###\n", glb_ate_info->nf);
|
||
ret = ERR_FAIL;
|
||
} else {
|
||
iot_printf("[ATE] current nf:%d ###success###\n", glb_ate_info->nf);
|
||
}
|
||
/* hw control tx rx */
|
||
phy_ana_hw_en_bitmap(~0);
|
||
|
||
return ret;
|
||
}
|
||
|
||
void meter_test(void)
|
||
{
|
||
int32_t doffset_avg = 0;
|
||
int32_t dx_avg = 0;
|
||
int32_t dy_avg = 0;
|
||
float vref = 0;
|
||
int32_t dc_offset = 0;
|
||
int32_t dv = 0;
|
||
int32_t ch1_adc3_v = 0;
|
||
|
||
iot_printf("doffset_avg************0x%x\n", &glb_ate_info->doffset_avg);
|
||
doffset_avg = sadc_ref_voltg_test(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_VCM_VCM, CP);
|
||
glb_ate_info->doffset_avg = doffset_avg;
|
||
|
||
/* cp test,single phase DIFF_CH10 */
|
||
iot_printf("dx_avg*****************0x%x\n",&glb_ate_info->dx_avg);
|
||
dx_avg = sadc_ref_voltg_test(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_DIFF_CH10, CP);
|
||
glb_ate_info->dx_avg = dx_avg;
|
||
|
||
/* cp test,single phase DIFF_CH32 */
|
||
iot_printf("dy_avg****************0x%x\n",&glb_ate_info->dy_avg);
|
||
dy_avg = sadc_ref_voltg_test(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_DIFF_CH32, CP);
|
||
glb_ate_info->dy_avg = dy_avg;
|
||
|
||
vref = (dx_avg - doffset_avg)/46786.0 + (dy_avg - doffset_avg)/23393.0;
|
||
glb_ate_info->vref = vref;
|
||
iot_printf("vref*****************0x%x\n", &glb_ate_info->vref);
|
||
|
||
iot_printf("doffset_avg:%d dx_avg:%d dy_avg:%d vref:%f\n",doffset_avg,dx_avg,dy_avg,vref);
|
||
|
||
/* ate test,VCM_VCM */
|
||
dc_offset = sadc_ref_voltg_test(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_VCM_VCM, ATE);
|
||
glb_ate_info->dc_offset = dc_offset;
|
||
|
||
/* ch0 chopper 0x28 */
|
||
uint32_t tmp = ANA_PMU_WRAP_RF_READ_REG(CFG_ANA_PMU_REG_CFG10_ADDR);
|
||
REG_FIELD_SET(ICCAL, tmp, 0x10);
|
||
ANA_PMU_WRAP_RF_WRITE_REG(CFG_ANA_PMU_REG_CFG10_ADDR, tmp);
|
||
|
||
/* ate test,single phase CH1_ADC3 */
|
||
iot_printf("CH1_ADC3\n");
|
||
|
||
dv = sadc_ref_voltg_test(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_SING_CH3, ATE);
|
||
iot_printf("%d\n",dv);
|
||
|
||
ch1_adc3_v = dv - dc_offset;
|
||
iot_printf("ch1_adc3_v:%d=%d - %d\n",ch1_adc3_v, dv, dc_offset);
|
||
iot_printf("dc_offset*****************0x%x\n", &glb_ate_info->dc_offset);
|
||
|
||
iot_printf("ch1_adc3_v*****************0x%x\n", glb_ate_info->ch1_adc3_v);
|
||
|
||
/* ch0 chopper 0x28 */
|
||
for(uint16_t j = 0; j < PMU_ICCAL_NUM; j++) {
|
||
tmp = ANA_PMU_WRAP_RF_READ_REG(CFG_ANA_PMU_REG_CFG10_ADDR);
|
||
REG_FIELD_SET(ICCAL, tmp, j);
|
||
ANA_PMU_WRAP_RF_WRITE_REG(CFG_ANA_PMU_REG_CFG10_ADDR, tmp);
|
||
dv = sadc_ref_voltg_test(SADC_PHASE0, SADC_TSW_SEL_SCL_MUX_SING_CH3, ATE);
|
||
ch1_adc3_v = dv - dc_offset;
|
||
glb_ate_info->ch1_adc3_v[j] = ch1_adc3_v;
|
||
iot_printf("ICCAL + 1:%d=%d - %d\n", ch1_adc3_v, dv, dc_offset);
|
||
}
|
||
}
|
||
/* main entry */
|
||
void ate_entry(void)
|
||
{
|
||
uint32_t start_time = 0;
|
||
uint32_t end_time = 0;
|
||
uint64_t time_span = 0;
|
||
|
||
uint32_t ret = ERR_OK;
|
||
uint16_t tx_dc[4] = {0};
|
||
uint16_t rx_dc[PHY_GAIN_STEP_MAX] = {0};
|
||
|
||
start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
|
||
|
||
#if HW_PLATFORM > HW_PLATFORM_SIMU
|
||
#if EDA_SIMU_SUPPORT != 1
|
||
for(volatile uint32_t i = 0; i < 5000; i++);
|
||
/* serial init */
|
||
dbg_uart_init();
|
||
iot_printf("ate_test begin...\n");
|
||
#endif
|
||
#endif
|
||
|
||
ate_init();
|
||
|
||
/* efuse chip-id nad version */
|
||
glb_ate_info->result = 0;
|
||
glb_ate_info->ret_flag = 0;
|
||
glb_ate_info->rsv[0] = 0x5a5a5a5a;
|
||
glb_ate_info->rsv[1] = 0x5a5a5a5a;
|
||
glb_ate_info->rsv[2] = 0x5a5a5a5a;
|
||
glb_ate_info->rsv[3] = 0x5a5a5a5a;
|
||
|
||
/* tx dc calibration */
|
||
ret = tx_dc_calibration(tx_dc);
|
||
if (ret == ERR_OK) {
|
||
os_mem_cpy(glb_ate_info->tx_dc, tx_dc, sizeof(tx_dc));
|
||
} else {
|
||
glb_ate_info->ret_flag |= ERR_BIT(0);
|
||
}
|
||
|
||
/* rx dc calibration */
|
||
ret = rx_dc_calibration(rx_dc);
|
||
if (ret == ERR_OK) {
|
||
os_mem_cpy(glb_ate_info->rx_dc, rx_dc, sizeof(rx_dc));
|
||
} else {
|
||
glb_ate_info->ret_flag |= ERR_BIT(1);
|
||
}
|
||
|
||
/* granite loopback */
|
||
ret = mac_granite_loop_back();
|
||
if (ret != ERR_OK) {
|
||
glb_ate_info->ret_flag |= ERR_BIT(2);
|
||
}
|
||
|
||
/* geode loopback */
|
||
ret = mac_geode_loop_back();
|
||
if (ret != ERR_OK) {
|
||
glb_ate_info->ret_flag |= ERR_BIT(3);
|
||
}
|
||
|
||
/* rx bandwidth filter calibration */
|
||
phy_rx_bw_filter(RX_BW_LIST_BAND0_12M);
|
||
/* reset phy */
|
||
phy_reset(PHY_RST_REASON_WARM);
|
||
phy_rx_bw_filter(RX_BW_LIST_BAND1_5P6M);
|
||
|
||
/* nf test */
|
||
ret = ate_nf_test();
|
||
if (ret != ERR_OK) {
|
||
glb_ate_info->ret_flag |= ERR_BIT(4);
|
||
}
|
||
|
||
meter_test();
|
||
|
||
end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
|
||
time_span = end_time - start_time;
|
||
if (time_span < 0) { // wrap around
|
||
time_span = (0x100000000LL) - start_time + end_time;
|
||
}
|
||
iot_printf("[ATE]total time: %llu us\n", time_span/TICKS_US);
|
||
if (!glb_ate_info->ret_flag) {
|
||
glb_ate_info->result = true;
|
||
iot_printf("ATE test pass!\n");
|
||
} else {
|
||
glb_ate_info->result = 0x55;
|
||
iot_printf("glb_ate_info->ret_flag: %d\n",glb_ate_info->ret_flag);
|
||
iot_printf("ATE test fail!\n");
|
||
}
|
||
}
|
||
|
||
int main(void) {
|
||
|
||
ate_entry();
|
||
|
||
return 0;
|
||
}
|