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kunlun/plc/halphy/hw/phy_bb.c
andy c756587541 初始提交
2024-09-28 14:24:04 +08:00

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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
***************************************************************************/
#include "iot_config.h"
#include "phy_bb.h"
#include "phy_reg.h"
#include "os_types.h"
#include "hw_reg_api.h"
#include "hw_tonemask.h"
#include "plc_fr.h"
#include "ahb.h"
#include "hw_desc.h"
#include "plc_const.h"
#include "iot_io.h"
#include "phy_rxtd_reg.h"
#include "phy_dfe_reg.h"
#include "phy_tx_reg.h"
#include "phy_reg.h"
#include "phy_rx_fd_reg.h"
#include "mac_rx_reg.h"
#include "mac_sys_reg.h"
#include "iot_errno_api.h"
#include "iot_system.h"
#include "granite_reg.h"
#include "phy_int.h"
#include "phy_ana.h"
#include "clk.h"
#include "hw_phy_api.h"
#include "phy_reset.h"
#include "iot_dbglog_api.h"
#include "iot_dbglog.h"
#include "phy_chn.h"
#include "iot_clock.h"
#include "os_utils.h"
#include "phy_nf.h"
#include "phy_txrx_pwr.h"
#if HW_PLATFORM == HW_PLATFORM_SIMU
/* working mode for fw
* 0 - Mission Mode
* 1 - FTM mode
* 2 - MP mode
*/
/*TODO: move to g_phy_ctxt*/
uint32_t g_fw_mode = MM_MODE;
#else /* HW_PLATFORM == HW_PLATFORM_SIMU */
extern uint32_t g_fw_mode;
#endif /* HW_PLATFORM == HW_PLATFORM_SIMU */
/* for JTAG psram version without cpu0 */
#if (RUN_ON_CPU_1 == 1) && (IOT_DTEST_ONLY_SUPPORT == 0)
phy_cpu_share_ctxt_t g_phy_cpu_share_ctxt = {0};
#endif
/* gain table */
agc_gain_tbl_t gain_reg_tbl[] = {
{ 0xA , -12 }, //-12 dB
{ 0x6 , -6 }, //-6 dB
{ 0x2 , 0 }, //0 dB
{ 0x12 , 6 }, //6 dB
{ 0x22 , 12 }, //12 dB
{ 0x32 , 18 }, //18 dB
{ 0x42 , 24 }, //24 dB
};
void phy_reset(PHY_RST_REASON_ID reason)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
phy_reset_pre_protect();
ahb_phy_reset();
phy_reset_post_protect();
#endif
(void)reason;
return;
}
/* phy eb control */
void phy_eb(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
if (en) {
/* WA, phy eb is blank, need use mac eb */
ahb_phy_mac_enable();
} else {
ahb_phy_disable();
}
#else
(void)en;
#endif
}
int16_t phy_ppm_cal_hw_val(PHY_CAL_UNIT_ID cal_unit, \
int16_t ppm_err, uint32_t rate_mode)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
int16_t ppm_cal = 0;
uint32_t frac = 0;
/* calibration calculate */
tmp = PHY_DFE_READ_REG(CFG_BB_PPM_SETTING_ADDR);
ppm_cal = REG_FIELD_GET(SW_RX_PPM,tmp);
/* precision */
(void)rate_mode;
ppm_err = ppm_err << PLC_REG_PPM_SHIFT;
if (cal_unit != PHY_CAL_UNIT_1_1)
{
/* for roundup */
uint32_t sign_num = cal_unit;
while (sign_num) {
tmp = 1 << (sign_num - 1);
frac |= ppm_err & tmp;
sign_num--;
}
if (!frac) {
ppm_cal = ppm_cal + ppm_err / (1 << cal_unit);
}
else {
if (ppm_err > 0) {
ppm_cal = ppm_cal + ppm_err / (1 << cal_unit) + 1;
}
else {
ppm_cal = ppm_cal + ppm_err / (1 << cal_unit) - 1;
}
}
} else {
/* set directly if no need approaching method */
ppm_cal = ppm_err;
}
return ppm_cal;
#else
(void)cal_unit;
(void)ppm_err;
(void)rate_mode;
return 0;
#endif
}
void IRAM_ATTR phy_ppm_set(int16_t ppm_cal, uint8_t flag)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_DFE_READ_REG(CFG_BB_PPM_SETTING_ADDR);
if (flag == BB_PPM_TXRX || flag == BB_PPM_TX_ONLY) {
REG_FIELD_SET(SW_TX_PPM, tmp, ppm_cal);
}
if (flag == BB_PPM_TXRX || flag == BB_PPM_RX_ONLY) {
REG_FIELD_SET(SW_RX_PPM, tmp, ~ppm_cal + 1);
}
PHY_DFE_WRITE_REG(CFG_BB_PPM_SETTING_ADDR,tmp);
#else
(void)ppm_cal;
(void)flag;
#endif
}
int16_t phy_txppm_get()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_DFE_READ_REG(CFG_BB_PPM_SETTING_ADDR);
int16_t txppm = (int16_t)REG_FIELD_GET(SW_TX_PPM, tmp);
return (txppm >> PLC_REG_PPM_SHIFT);
#else
return PLC_MAX_PPM_SUPPORT;
#endif
}
/* ppm calibration */
uint32_t phy_ppm_cal_and_update_hw(PHY_CAL_UNIT_ID cal_unit, \
int16_t ppm_err, uint32_t rate_mode, uint8_t update_flag)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
int16_t ppm_cal = phy_ppm_cal_hw_val(cal_unit, ppm_err, rate_mode);
phy_ppm_set(ppm_cal, update_flag);
iot_printf("ppm_cal:%hd, ppm_err:%hd\r\n",ppm_cal,ppm_err);
#else
(void)cal_unit;
(void)ppm_err;
(void)rate_mode;
(void)update_flag;
#endif
return 0;
}
/* current ppm info */
int16_t phy_ppm_info_get(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
int16_t cur_ppm = 0;
tmp = PHY_RX_FD_READ_REG(CFG_BB_FREQ_ERROR_ADDR);
cur_ppm = REG_FIELD_GET(SW_FREQ_ERROR_PPM,tmp);
if(cur_ppm & 0x200)
{
cur_ppm = 0xFC00 | cur_ppm;
}
return cur_ppm;
#endif
return 0;
}
/* snr calibrate */
uint32_t phy_rx_snr_get(uint32_t start, uint32_t end, int32_t *buf)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
int32_t tmp = 0;
uint32_t i = 0;
uint32_t tone_idx = 0;
uint32_t start_time = 0, end_time = 0;
int64_t time_span = 0;
/* det start and end tone */
phy_rxfd_rate0_det(start,end);
/* select dump mode */
tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
REG_FIELD_SET(SW_SNR_DUMP_MODE,tmp,1);//0:rsi, 1:snr
REG_FIELD_SET(SW_SNR_DUMP_EN,tmp,1);
PHY_RX_FD_WRITE_REG(CFG_BB_SNR_ADDR,tmp);
/* start time after enable */
start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
/* wait until dump done */
do{
tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
tmp = REG_FIELD_GET(SW_SNR_DUMP_DONE,tmp);
}while(!tmp);
/* end time after done */
end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
time_span = end_time - start_time;
if (time_span < 0) { // wrap around
time_span = (0x100000000LL) - start_time + end_time;
}
iot_printf("[SNR][Elapsed Time] %lldns\r\n", time_span*40);
/* cal snr for every tone */
for(tone_idx = start; tone_idx < end; tone_idx++)
{
tmp = SOC_READ_REG(BB_SNR_BASEADDR+tone_idx*4);
iot_printf("[tone id-%d] signal:%d, noise:%d\r\n",tone_idx,(tmp >> 8)&0xff,(tmp&0xff));
tmp = (int32_t)(((((tmp >> 8) & 0xff) - (tmp & 0xff))*3)>>3);
buf[i++] = tmp;
}
#else
(void)start;
(void)end;
(void)buf;
#endif
return 0;
}
/* softbit raw data dump */
uint32_t phy_rx_softbit_get( \
uint32_t start, \
uint32_t end, \
int32_t *buf, \
uint32_t dly_cnt)
{
(void)start;
(void)end;
(void)buf;
(void)dly_cnt;
return 0;
}
uint32_t phy_rx_spur_get( \
uint32_t start, \
uint32_t end, \
uint32_t *buf, \
uint32_t dly_cnt)
{
(void)start;
(void)end;
(void)buf;
(void)dly_cnt;
return 0;
}
/* csi calibrate */
uint32_t phy_rx_csi_get(uint32_t start, uint32_t end, uint32_t *buf)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
uint32_t i = 0;
uint32_t tone_idx = 0;
uint32_t power = 0;
uint32_t start_time = 0, end_time = 0;
int64_t time_span = 0;
#if MAC_RX_TEST_ID == MAC_RX_CSI_SCAN
/* right shift for signal saturation */
phy_gain_shift_set(0,0,0,3);
#endif
/* det start and end tone */
phy_rxfd_rate0_det(start,end);
/* select dump mode */
tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
REG_FIELD_SET(SW_SNR_DUMP_MODE,tmp,0);//0:csi, 1:snr
REG_FIELD_SET(SW_SNR_DUMP_EN,tmp,1);
PHY_RX_FD_WRITE_REG(CFG_BB_SNR_ADDR,tmp);
/* start time after enable */
start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
/* wait until dump done */
do{
tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
tmp = REG_FIELD_GET(SW_SNR_DUMP_DONE,tmp);
}while(!tmp);
/* end time after done */
end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
time_span = end_time - start_time;
if (time_span < 0) { // wrap around
time_span = (0x100000000LL) - start_time + end_time;
}
iot_printf("[CSI][Elapsed Time] %lldns\r\n", time_span*40);
/* cal snr for every tone */
for(tone_idx = start; tone_idx < end; tone_idx++)
{
tmp = SOC_READ_REG(BB_SNR_BASEADDR+tone_idx*4);
power = (tmp >> 8) & 0xff;
if(power & 0x80){
power = 256 - power;
}
power = power * power;
iot_printf("tone%d power:I=%d,",tone_idx, power);
tmp = tmp & 0xff;
if(tmp & 0x80){
tmp = 256 - tmp;
}
power += tmp * tmp;
buf[i++] = power;
iot_printf("Q=%d\r\n",tmp*tmp);
}
#else
(void)start;
(void)end;
(void)buf;
#endif
return 0;
}
/* noise floor cal */
uint32_t phy_rx_noise_floor_get(uint32_t start, uint32_t end, uint32_t *buf)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
uint32_t tone_idx = 0;
uint32_t start_time = 0, end_time = 0;
int64_t time_span = 0;
uint32_t i = 0;
/* right shift for signal saturation */
phy_gain_shift_set(0,0,0,3);
/* det start and end tone */
phy_rxfd_rate0_det(start,end);
/* en noise floor */
tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
REG_FIELD_SET(SW_SNR_DUMP_MODE,tmp,3);//0:csi, 3:noise floor
REG_FIELD_SET(SW_SNR_DUMP_EN,tmp,1);
PHY_RX_FD_WRITE_REG(CFG_BB_SNR_ADDR,tmp);
/* start time after enable */
start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
/* wait until dump done */
do{
tmp = PHY_RX_FD_READ_REG(CFG_BB_SNR_ADDR);
tmp = REG_FIELD_GET(SW_SNR_DUMP_DONE,tmp);
}while(!tmp);
/* end time after done */
end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
time_span = end_time - start_time;
if (time_span < 0) { // wrap around
time_span = (0x100000000LL) - start_time + end_time;
}
iot_printf("[Noise Floor][Elapsed Time] %lldns\r\n", time_span*40);
/* cal noise floor for every tone */
for(tone_idx = start; tone_idx < end; tone_idx++)
{
tmp = SOC_READ_REG(BB_SNR_BASEADDR+tone_idx*4)/3;/* 5dB att */
buf[i++] = tmp;
}
#else
(void)start;
(void)end;
(void)buf;
#endif
return 0;
}
/* noise floor cal new */
uint8_t phy_rx_nf_by_rxtd_get(uint8_t dly_value)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
uint32_t nf_cal_done_flag = 0;
uint8_t nf_value = 0;
uint32_t start_time = 0, end_time = 0;
int64_t time_span = 0;
/* stop systick nf cal */
phy_cal_nf_systick_stop();
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
REG_FIELD_SET(SW_CAL_NOISE_DLY_EXP, tmp, dly_value);//(2^[SW_CAL_NOISE_DLY_EXP])*2.6us
REG_FIELD_SET(SW_CAL_NOISE_START, tmp, 1);//start calculate noise floor
PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);
/* start time before calculate noise floor */
start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
/* wait for calculating complete */
do{
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
nf_cal_done_flag = REG_FIELD_GET(SW_CAL_NOISE_DONE, tmp);
/* calculate time slot */
end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
time_span = end_time - start_time;//unit: 0.04us
/* wrap around */
if (time_span < 0){
time_span = (0x100000000LL) - start_time + end_time;
}
/* time out (unit: us), ntb to us*/
if ((time_span / 25) > 100 * 1000) {
break;
}
}while(nf_cal_done_flag != 1);
nf_value = REG_FIELD_GET(SW_CAL_NOISE_PWR, tmp);
return nf_value;
#else
(void)dly_value;
#endif
return 0;
}
/* get gain value */
uint32_t phy_gain_val_get(uint8_t gain0, uint8_t gain1)
{
uint32_t i = 0;
uint32_t gain_val = 0;
for(i = 0, gain_val = 0; i < sizeof(gain_reg_tbl)/sizeof(agc_gain_tbl_t); i++)
{
if((gain0 & 0xff) == gain_reg_tbl[i].reg_val)
gain_val += gain_reg_tbl[i].rx_gain;
if((gain1 & 0xff) == gain_reg_tbl[i].reg_val)
gain_val += gain_reg_tbl[i].rx_gain;
}
return gain_val;
}
/* snr gain info */
uint32_t phy_rx_snr_gain_get(int32_t *gain, uint32_t *nf)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp = 0;
uint32_t gain_entry = 0;
uint8_t gain_reg0 = 0;
uint8_t gain_reg1 = 0;
/* gain and noise floor */
tmp = PHY_RXTD_READ_REG(CFG_BB_PACKET_INF_1_ADDR);
gain_entry = REG_FIELD_GET(GAIN_TABLE_ENTRY_NF,tmp);
gain_reg0 = (uint8_t)(all_mask_gain_table[gain_entry] & 0xff);
gain_reg1 = (uint8_t)((all_mask_gain_table[gain_entry] >> 8) & 0xff);
*gain = phy_gain_val_get(gain_reg0,gain_reg1);
*nf = REG_FIELD_GET(RSSI_NF,tmp);
#else
(void)gain;
(void)nf;
#endif
return 0;
}
uint32_t phy_get_tx_pb_swcrc_cfg(void)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
uint32_t is_sw_crc;
tmp = PHY_READ_REG(CFG_BB_CRC_CFG_ADDR);
is_sw_crc = REG_FIELD_GET(SW_PLD_CRC_BY_SW, tmp);
return is_sw_crc;
#else
/* simu return sw crc always */
return 1;
#endif
}
void phy_set_tx_pb_swcrc_cfg(uint32_t is_by_sw)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_READ_REG(CFG_BB_CRC_CFG_ADDR);
REG_FIELD_SET(SW_PLD_CRC_BY_SW, tmp, is_by_sw);
PHY_WRITE_REG(CFG_BB_CRC_CFG_ADDR, tmp);
#else
(void)is_by_sw;
#endif
return;
}
uint32_t phy_get_tx_fc_swcrc_cfg(void)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
uint32_t is_sw_crc;
tmp = PHY_READ_REG(CFG_BB_CRC_CFG_ADDR);
is_sw_crc = REG_FIELD_GET(SW_FC_CRC_BY_SW, tmp);
return is_sw_crc;
#else
/* simu return sw crc always */
return 1;
#endif
}
void phy_set_tx_fc_swcrc_cfg(uint32_t is_by_sw)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_READ_REG(CFG_BB_CRC_CFG_ADDR);
REG_FIELD_SET(SW_FC_CRC_BY_SW, tmp, is_by_sw);
PHY_WRITE_REG(CFG_BB_CRC_CFG_ADDR, tmp);
#else
(void)is_by_sw;
#endif
return;
}
/* agc fpga control */
void phy_agc_hw_en(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(!en){
/* AGC bypass mode */
tmp = PHY_DFE_READ_REG(CFG_BB_AGC_SWCFG_EN_ADDR);
REG_FIELD_SET(AGC_BYPASS_MODE, tmp, 0x1);
REG_FIELD_SET(SW_GAIN_CFG_EN, tmp, 0x1);
REG_FIELD_SET(SW_AR1540_EN, tmp, 0x1);
PHY_DFE_WRITE_REG(CFG_BB_AGC_SWCFG_EN_ADDR, tmp);
}
else{
tmp = PHY_DFE_READ_REG(CFG_BB_AGC_SWCFG_EN_ADDR);
REG_FIELD_SET( AGC_BYPASS_MODE, tmp, 0x0 );
REG_FIELD_SET( SW_GAIN_CFG_EN, tmp, 0x0 );
#if HW_PLATFORM > HW_PLATFORM_FPGA
REG_FIELD_SET(SW_AR1540_EN, tmp, 0x0);
#endif
PHY_DFE_WRITE_REG(CFG_BB_AGC_SWCFG_EN_ADDR, tmp);
}
#else
(void)en;
#endif
}
/* tx/rx shift control */
void phy_gain_shift_set(uint8_t tx_dir, uint8_t t_shift, \
uint8_t rx_dir, uint8_t r_shift)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_SW_ADJUST_GAIN_ADDR);
REG_FIELD_SET(SW_TX_GAIN_LEFT_SHIFT, tmp, tx_dir);
REG_FIELD_SET(SW_TX_GAIN_SHIFT_BITS, tmp, t_shift);
REG_FIELD_SET(SW_RX_GAIN_LEFT_SHIFT, tmp, rx_dir);
REG_FIELD_SET(SW_RX_GAIN_SHIFT_BITS, tmp, r_shift);
PHY_DFE_WRITE_REG(CFG_BB_SW_ADJUST_GAIN_ADDR, tmp);
#else
(void)tx_dir;
(void)t_shift;
(void)rx_dir;
(void)r_shift;
#endif
}
/* tx factor control */
void phy_tx_gain_factor_set(uint8_t pwr_scale_factor)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_SW_ADJUST_GAIN_ADDR);
REG_FIELD_SET(SW_TX_PWR_SCALE_FACTOR, tmp, pwr_scale_factor);
PHY_DFE_WRITE_REG(CFG_BB_SW_ADJUST_GAIN_ADDR, tmp);
#else
(void)pwr_scale_factor;
#endif
}
/* tx factor control */
uint8_t phy_tx_gain_factor_get(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_DFE_READ_REG(CFG_BB_SW_ADJUST_GAIN_ADDR);
return REG_FIELD_GET(SW_TX_PWR_SCALE_FACTOR, tmp);
#else
return 0;
#endif
}
/* bb version control */
void phy_version_set(uint32_t mac_typ)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_VERSION_ADDR);
if(mac_typ == PLC_PROTO_TYPE_SG){ /* smart grid */
REG_FIELD_SET(SW_BB_VERSION, tmp, 0);
}
else if (mac_typ == PLC_PROTO_TYPE_SPG){
REG_FIELD_SET(SW_BB_VERSION, tmp, 3); /* southern power grid */
}
else{ /* green phy */
REG_FIELD_SET(SW_BB_VERSION, tmp, 1);
}
PHY_WRITE_REG(CFG_BB_VERSION_ADDR, tmp);
#else
(void)mac_typ;
#endif
}
/* bb agc rcv common parameters */
void phy_agc_rcv_tgt_set(uint8_t tgt_pwr, uint8_t low, uint8_t hi)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ST_RCV_LO_TH_ADDR);
REG_FIELD_SET(SW_ST_RCV_LO_TH, tmp, low );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ST_RCV_LO_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ST_RCV_HI_TH_ADDR);
REG_FIELD_SET(SW_ST_RCV_HI_TH, tmp, hi );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ST_RCV_HI_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ST_RCV_TGT_ADDR);
REG_FIELD_SET(SW_ST_RCV_TGT, tmp, tgt_pwr );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ST_RCV_TGT_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_RCV_LO_TH_ADDR);
REG_FIELD_SET(SW_WK_RCV_LO_TH, tmp, low );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_RCV_LO_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_RCV_HI_TH_ADDR);
REG_FIELD_SET(SW_WK_RCV_HI_TH, tmp, hi );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_RCV_HI_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_RCV_TGT_ADDR);
REG_FIELD_SET(SW_WK_RCV_TGT, tmp, tgt_pwr );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_RCV_TGT_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_DET_LO_TH_ADDR);
REG_FIELD_SET(SW_WK_DET_LO_TH, tmp, low );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_DET_LO_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_DET_HI_TH_ADDR);
REG_FIELD_SET(SW_WK_DET_HI_TH, tmp, hi );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_DET_HI_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_DET_TGT_ADDR);
REG_FIELD_SET(SW_WK_DET_TGT, tmp, tgt_pwr );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_DET_TGT_ADDR, tmp);
#else
(void)tgt_pwr;
(void)low;
(void)hi;
#endif
}
/* get common target power and low, hi threshold */
void phy_agc_rcv_tgt_get(uint8_t *tgt_pwr, uint8_t *low, uint8_t *hi)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ST_RCV_LO_TH_ADDR);
*low = REG_FIELD_GET(SW_ST_RCV_LO_TH, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ST_RCV_HI_TH_ADDR);
*hi = REG_FIELD_GET(SW_ST_RCV_HI_TH, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ST_RCV_TGT_ADDR);
*tgt_pwr = REG_FIELD_GET(SW_ST_RCV_TGT, tmp);
#else
(void *)tgt_pwr;
(void *)low;
(void *)hi;
#endif
}
/* bb agc up/drop threshold */
void phy_agc_rcv_thrd_set(bool_t up_rst_dis, uint8_t up_det, uint8_t up_rcv,\
bool_t drop_rst_dis, uint8_t drop_det, uint8_t drop_rcv)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_RAMUP_TH_ADDR);
REG_FIELD_SET(SW_RAMPUP_RESTART_DIS, tmp, up_rst_dis );
REG_FIELD_SET(SW_RAMPUP_DET_TH, tmp, up_det );
REG_FIELD_SET(SW_RAMPUP_RCV_TH, tmp, up_rcv );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_RAMUP_TH_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_DROP_TH_ADDR);
REG_FIELD_SET(SW_DROP_RESTART_DIS, tmp, drop_rst_dis );
REG_FIELD_SET(SW_DROP_DET_TH, tmp, drop_det );
REG_FIELD_SET(SW_DROP_RCV_TH, tmp, drop_rcv );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_DROP_TH_ADDR, tmp);
#else
(void)up_rst_dis;
(void)up_det;
(void)up_rcv;
(void)drop_rst_dis;
(void)drop_det;
(void)drop_rcv;
#endif
}
void phy_agc_ramup_restart_dis_set(bool_t up_rst_dis)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_RAMUP_TH_ADDR);
REG_FIELD_SET(SW_RAMPUP_RESTART_DIS, tmp, up_rst_dis );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_RAMUP_TH_ADDR, tmp);
#else
(void)up_rst_dis;
#endif
}
void phy_agc_drop_restart_dis_set(bool_t drop_rst_dis)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_DROP_TH_ADDR);
REG_FIELD_SET(SW_DROP_RESTART_DIS, tmp, drop_rst_dis );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_DROP_TH_ADDR, tmp);
#else
(void)drop_rst_dis;
#endif
}
void phy_agc_sat_jug_cnt_set(uint8_t jug_cnt)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_SAT_TH_ADDR);
REG_FIELD_SET(SW_PWR_SAT_JUG_CNT, tmp, jug_cnt);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_SAT_TH_ADDR,tmp);
#else
(void)jug_cnt;
#endif
}
void phy_agc_seg_num_set(uint8_t seg_num)
{
(void)seg_num;
}
void phy_agc_sat_rst_dis_set(bool_t rst_dis)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* full reset */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_SAT_TH_ADDR);
REG_FIELD_SET(SW_SAT_RESTART_DIS,tmp,rst_dis);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_SAT_TH_ADDR,tmp);
#else
(void)rst_dis;
#endif
}
void phy_agc_sat_adj_set(bool_t sat_dis, bool_t adj_dis)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* full */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR);
REG_FIELD_SET(SW_ADJ_REQ_DIS,tmp,adj_dis);
REG_FIELD_SET(SW_SAT_DIS,tmp,sat_dis);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR,tmp);
#else
(void)sat_dis;
(void)adj_dis;
#endif
}
/* bb fc sym offset */
void phy_fc_symb_offset_set(uint8_t symb2, uint8_t symb3, uint8_t symb4, uint8_t symb5, \
uint8_t symb6, uint8_t symb7, uint8_t symb8, uint8_t symb9, \
uint8_t symb10, uint8_t symb11, uint8_t symb12)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_FC_OFFSET0_ADDR);
REG_FIELD_SET(SW_FC_SYMB2_OFFSET, tmp, symb2 );
REG_FIELD_SET(SW_FC_SYMB3_OFFSET, tmp, symb3 );
REG_FIELD_SET(SW_FC_SYMB4_OFFSET, tmp, symb4 );
REG_FIELD_SET(SW_FC_SYMB5_OFFSET, tmp, symb5 );
PHY_WRITE_REG(CFG_BB_FC_OFFSET0_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_OFFSET1_ADDR);
REG_FIELD_SET(SW_FC_SYMB6_OFFSET, tmp, symb6 );
REG_FIELD_SET(SW_FC_SYMB7_OFFSET, tmp, symb7 );
REG_FIELD_SET(SW_FC_SYMB8_OFFSET, tmp, symb8 );
REG_FIELD_SET(SW_FC_SYMB9_OFFSET, tmp, symb9 );
PHY_WRITE_REG(CFG_BB_FC_OFFSET1_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_OFFSET2_ADDR);
REG_FIELD_SET(SW_FC_SYMB10_OFFSET, tmp, symb10 );
REG_FIELD_SET(SW_FC_SYMB11_OFFSET, tmp, symb11 );
REG_FIELD_SET(SW_FC_SYMB12_OFFSET, tmp, symb12 );
PHY_WRITE_REG(CFG_BB_FC_OFFSET2_ADDR, tmp);
#else
(void)symb2;(void)symb3;(void)symb4;(void)symb5;
(void)symb6;(void)symb7;(void)symb8;(void)symb9;
(void)symb10;(void)symb11;(void)symb12;
#endif
}
/* bb gain value set */
void phy_gain_val_set(uint8_t serial, uint32_t data)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(serial == 0){
tmp = PHY_DFE_READ_REG(CFG_GAIN_SERIAL_CFG0_ADDR);
REG_FIELD_SET(SW_GAIN_CFG0_DATA,tmp,data);
PHY_DFE_WRITE_REG(CFG_GAIN_SERIAL_CFG0_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_GAIN_SERIAL_CFG0_START_ADDR);
REG_FIELD_SET(SW_GAIN_CFG0_START,tmp,1);
PHY_DFE_WRITE_REG(CFG_GAIN_SERIAL_CFG0_START_ADDR, tmp);
}
else if(serial == 1){
tmp = PHY_DFE_READ_REG(CFG_GAIN_SERIAL_CFG1_ADDR);
REG_FIELD_SET(SW_GAIN_CFG1_DATA,tmp,data);
PHY_DFE_WRITE_REG(CFG_GAIN_SERIAL_CFG1_ADDR, tmp);
tmp = PHY_DFE_READ_REG(CFG_GAIN_SERIAL_CFG1_START_ADDR);
REG_FIELD_SET(SW_GAIN_CFG1_START,tmp,1);
PHY_DFE_WRITE_REG(CFG_GAIN_SERIAL_CFG1_START_ADDR, tmp);
}
#else
(void)serial;
(void)data;
#endif
}
/* bb tx rms set */
void IRAM_ATTR phy_tx_rms_set(uint32_t rate_id, \
uint32_t hw_band_id, uint16_t integer, uint8_t frac)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(rate_id == 0) {
if (hw_band_id == HW_FULL_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR);
REG_FIELD_SET(SW_RATE0_BAND0_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_RATE0_BAND0_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR,tmp);
} else if (hw_band_id == HW_LOW_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND1_ADDR);
REG_FIELD_SET(SW_RATE0_BAND1_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_RATE0_BAND1_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND1_ADDR,tmp);
} else if (hw_band_id == HW_HIGH_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND2_ADDR);
REG_FIELD_SET(SW_RATE0_BAND2_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_RATE0_BAND2_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND2_ADDR,tmp);
}
} else if(rate_id == 1) {
if (hw_band_id == HW_FULL_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND0_ADDR);
REG_FIELD_SET(SW_RATE1_BAND0_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_RATE1_BAND0_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND0_ADDR,tmp);
} else if (hw_band_id == HW_LOW_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND1_ADDR);
REG_FIELD_SET(SW_RATE1_BAND1_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_RATE1_BAND1_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND1_ADDR,tmp);
} else if (hw_band_id == HW_HIGH_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND2_ADDR);
REG_FIELD_SET(SW_RATE1_BAND2_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_RATE1_BAND2_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND2_ADDR,tmp);
}
} else if(rate_id == 2) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR);
REG_FIELD_SET(SW_SHORT_PREAM_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR,tmp);
}
#else
(void)rate_id;
(void)hw_band_id;
(void)integer;
(void)frac;
#endif
}
/* bb tx rms get */
void IRAM_ATTR phy_tx_rms_get(uint32_t rate_id, \
uint32_t hw_band_id, uint16_t *integer, uint8_t *frac)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(rate_id == 0) {
if (hw_band_id == HW_FULL_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR);
*integer = REG_FIELD_GET(SW_RATE0_BAND0_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_RATE0_BAND0_DB_UP_AMP_PARA_FRAC,tmp);
} else if (hw_band_id == HW_LOW_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND1_ADDR);
*integer = REG_FIELD_GET(SW_RATE0_BAND1_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_RATE0_BAND1_DB_UP_AMP_PARA_FRAC,tmp);
} else if (hw_band_id == HW_HIGH_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND2_ADDR);
*integer = REG_FIELD_GET(SW_RATE0_BAND2_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_RATE0_BAND2_DB_UP_AMP_PARA_FRAC,tmp);
}
} else if(rate_id == 1) {
if (hw_band_id == HW_FULL_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND0_ADDR);
*integer = REG_FIELD_GET(SW_RATE1_BAND0_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_RATE1_BAND0_DB_UP_AMP_PARA_FRAC,tmp);
} else if (hw_band_id == HW_LOW_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND1_ADDR);
*integer = REG_FIELD_GET(SW_RATE1_BAND1_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_RATE1_BAND1_DB_UP_AMP_PARA_FRAC,tmp);
} else if (hw_band_id == HW_HIGH_BAND) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND2_ADDR);
*integer = REG_FIELD_GET(SW_RATE1_BAND2_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_RATE1_BAND2_DB_UP_AMP_PARA_FRAC,tmp);
}
} else if(rate_id == 2) {
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR);
*integer = REG_FIELD_GET(SW_SHORT_PREAM_DB_UP_AMP_PARA_INT,tmp);
*frac = REG_FIELD_GET(SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC,tmp);
}
#else
(void)rate_id;
(void)hw_band_id;
(void)integer;
(void)frac;
#endif
}
/* bb tx short rms set */
void phy_tx_short_rms_set( uint16_t integer, uint8_t frac)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR);
REG_FIELD_SET(SW_SHORT_PREAM_DB_UP_AMP_PARA_INT,tmp,integer);
REG_FIELD_SET(SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC,tmp,frac);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR,tmp);
#else
(void)integer;
(void)frac;
#endif
}
/* 16QAM backoff rms set */
void phy_tx_16qam_backoff_rms_set( uint16_t backoff)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_ADDR);
REG_FIELD_SET(SW_PWR_BACKOFF_16QAM, tmp, backoff);
PHY_TX_WRITE_REG(CFG_BB_DB_AMP_CTRL_ADDR,tmp);
#else
(void)backoff;
#endif
}
/* bb pkt ratio set */
void phy_pkt_ratio_set(uint8_t step_1k, uint8_t ratio_1k, \
uint8_t step_384, uint8_t ratio_384)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_PKT_RATIO_ADDR);
REG_FIELD_SET(SW_AC_STEP_1K, tmp, step_1k );
REG_FIELD_SET(SW_PKT_DET_RATIO_1K, tmp, ratio_1k );
REG_FIELD_SET(SW_AC_STEP_384, tmp, step_384 );
REG_FIELD_SET(SW_PKT_DET_RATIO_384, tmp, ratio_384 );
PHY_RXTD_WRITE_REG(CFG_BB_PKT_RATIO_ADDR, tmp);
#else
(void)step_1k;(void)ratio_1k;
(void)step_384;(void)ratio_384;
#endif
}
/* bb valid tone number set */
void phy_vld_tone_num_set(uint32_t rate_id, uint32_t band_id, uint32_t vld_tone_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
if(rate_id == 0)
{
if (band_id == HW_FULL_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B0_VLD_TONE_ADDR);
REG_FIELD_SET(SW_RATE0_BAND0_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_R0_B0_VLD_TONE_ADDR, tmp);
}
else if (band_id == HW_LOW_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B1_VLD_TONE_ADDR);
REG_FIELD_SET(SW_RATE0_BAND1_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_R0_B1_VLD_TONE_ADDR, tmp);
}
else if (band_id == HW_HIGH_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B2_VLD_TONE_ADDR);
REG_FIELD_SET(SW_RATE0_BAND2_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_R0_B2_VLD_TONE_ADDR, tmp);
}
}
else if(rate_id == 1){
if (band_id == HW_FULL_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B0_VLD_TONE_ADDR);
REG_FIELD_SET(SW_RATE1_BAND0_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_R1_B0_VLD_TONE_ADDR, tmp);
}
else if (band_id == HW_LOW_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B1_VLD_TONE_ADDR);
REG_FIELD_SET(SW_RATE1_BAND1_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_R1_B1_VLD_TONE_ADDR, tmp);
}
else if (band_id == HW_HIGH_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B2_VLD_TONE_ADDR);
REG_FIELD_SET(SW_RATE1_BAND2_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_R1_B2_VLD_TONE_ADDR, tmp);
}
}
#else
(void)rate_id;
(void)band_id;
(void)vld_tone_num;
#endif
}
/* bb valid tone number set */
uint32_t phy_vld_tone_num_get(uint32_t rate_id, uint32_t band_id)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
if(rate_id == 0)
{
if (band_id == HW_FULL_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B0_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_RATE0_BAND0_VLD_TONE_NUM, tmp);
}
else if (band_id == HW_LOW_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B1_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_RATE0_BAND1_VLD_TONE_NUM, tmp);
}
else if (band_id == HW_HIGH_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B2_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_RATE0_BAND2_VLD_TONE_NUM, tmp);
}
}
else if(rate_id == 1){
if (band_id == HW_FULL_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B0_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_RATE1_BAND0_VLD_TONE_NUM, tmp);
}
else if (band_id == HW_LOW_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B1_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_RATE1_BAND1_VLD_TONE_NUM, tmp);
}
else if (band_id == HW_HIGH_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B2_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_RATE1_BAND2_VLD_TONE_NUM, tmp);
}
}
#else
(void)rate_id;
(void)band_id;
#endif
return 0;
}
/* bb short valid tone number set */
void phy_short_vld_tone_num_set(uint32_t vld_tone_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_SHORT_PREAM_VLD_TONE_ADDR);
REG_FIELD_SET(SW_SHORT_PREAM_VLD_TONE_NUM, tmp, vld_tone_num );
PHY_WRITE_REG(CFG_BB_SHORT_PREAM_VLD_TONE_ADDR, tmp);
#else
(void)vld_tone_num;
#endif
}
/* bb short valid tone number get */
uint32_t phy_short_vld_tone_num_get(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_SHORT_PREAM_VLD_TONE_ADDR);
return REG_FIELD_GET(SW_SHORT_PREAM_VLD_TONE_NUM, tmp);
#endif
return 0;
}
/* pld GI1 set */
void phy_pld_gi1_set(uint16_t gi1)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_PLD_GI0_ADDR);
REG_FIELD_SET(SW_PLD_GI1, tmp, gi1);
PHY_WRITE_REG(CFG_BB_PLD_GI0_ADDR, tmp);
#else
(void)gi1;
#endif
}
/* bb common init*/
void phy_common_init(uint32_t mac_typ)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(mac_typ == PLC_PROTO_TYPE_SG || mac_typ == PLC_PROTO_TYPE_SPG)
{
if(mac_typ == PLC_PROTO_TYPE_SPG){
tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
REG_FIELD_SET(SW_TX_PRE_AMP,tmp, 13);
REG_FIELD_SET(SW_PRE_REF_PHASE, tmp, 2);
REG_FIELD_SET(SW_TX_PRE_MODE, tmp, 0);
PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
REG_FIELD_SET(SW_TX_PLD_MODE, tmp, 0x0 );
REG_FIELD_SET(SW_PLD_REF_PHASE, tmp, 0x2 );
REG_FIELD_SET(SW_CI_HBS_DIR, tmp, 0x1 );
PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_GI_ADDR);
REG_FIELD_SET(SW_FC_GI0, tmp, 0x1ca );
REG_FIELD_SET(SW_FC_GI1, tmp, 0x1ca );
REG_FIELD_SET(SW_FC_GI0_RANGE, tmp, 0x8 );
PHY_WRITE_REG(CFG_BB_FC_GI_ADDR, tmp);
/* bb turbo ctrl */
tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
REG_FIELD_SET(SW_SCRAMBLE_RESET_MODE,tmp,1);
REG_FIELD_SET(SW_SCRAMBLE_MODE,tmp,1);
PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR,tmp);
tmp = PHY_TX_READ_REG(CFG_BB_TX_TURBO_SET_ADDR);
REG_FIELD_SET(SW_SCRAMBLE_RESET_MODE, tmp, 1);
REG_FIELD_SET(SW_SCRAMBLE_MODE,tmp,1);
PHY_TX_WRITE_REG(CFG_BB_TX_TURBO_SET_ADDR,tmp);
}
else{
tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
REG_FIELD_SET(SW_TX_PRE_AMP,tmp, 13);
REG_FIELD_SET(SW_PRE_REF_PHASE, tmp, 0);
REG_FIELD_SET(SW_TX_PRE_MODE, tmp, 0);
PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
REG_FIELD_SET(SW_TX_PLD_MODE, tmp, 0x0 );
REG_FIELD_SET(SW_PLD_REF_PHASE, tmp, 0x0 );
REG_FIELD_SET(SW_CI_HBS_DIR, tmp, 0x0 );
PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_GI_ADDR);
REG_FIELD_SET(SW_FC_GI0, tmp, 0x1ca );
REG_FIELD_SET(SW_FC_GI1, tmp, 0x1ca );
REG_FIELD_SET(SW_FC_GI0_RANGE, tmp, 0x4 );
PHY_WRITE_REG(CFG_BB_FC_GI_ADDR, tmp);
tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
REG_FIELD_SET(SW_SCRAMBLE_PB_EN,tmp,1);
REG_FIELD_SET(SW_SCRAMBLE_RESET_MODE,tmp,1);
REG_FIELD_SET(SW_SCRAMBLE_MODE,tmp,0);
PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR,tmp);
/* bb turbo ctrl */
tmp = PHY_TX_READ_REG(CFG_BB_TX_TURBO_SET_ADDR);
REG_FIELD_SET(SW_SCRAMBLE_RESET_MODE,tmp,1);
REG_FIELD_SET(SW_SCRAMBLE_MODE,tmp,0);
PHY_TX_WRITE_REG(CFG_BB_TX_TURBO_SET_ADDR,tmp);
}
tmp = PHY_READ_REG(CFG_BB_CRC_CFG_ADDR);
REG_FIELD_SET(SW_PLD_CRC_BY_SW, tmp, 0x0 );
REG_FIELD_SET(SW_FC_CRC_BY_SW, tmp, 0x0 );
REG_FIELD_SET(SW_FC_CRC_MODE, tmp, 0x0 );
REG_FIELD_SET(SW_PLD_CRC_MODE, tmp, 0x0 );
REG_FIELD_SET(SW_FC_CRC_INITIAL, tmp, 0x0 );
REG_FIELD_SET(SW_PLD_CRC_INITIAL, tmp, 0x0 );
REG_FIELD_SET(SW_FC_CRC_INV, tmp, 0x0 );
REG_FIELD_SET(SW_PLD_CRC_INV, tmp, 0x0 );
PHY_WRITE_REG(CFG_BB_CRC_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_CRC_REM_ADDR);
REG_FIELD_SET(SW_FC_CRC_REMAIN, tmp, 0x0 );
PHY_WRITE_REG(CFG_BB_FC_CRC_REM_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_CRC_REM_ADDR);
REG_FIELD_SET(SW_PLD_CRC_REMAIN, tmp, 0x0 );
PHY_WRITE_REG(CFG_BB_PLD_CRC_REM_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_GI0_ADDR);
REG_FIELD_SET(SW_PLD_GI0, tmp, 0x1ca );
REG_FIELD_SET(SW_PLD_GI0_RANGE, tmp, 0x2 );
REG_FIELD_SET(SW_PLD_GI1, tmp, 0x108 );
REG_FIELD_SET(SW_PLD_GI1_RANGE, tmp, 0x8 );
PHY_WRITE_REG(CFG_BB_PLD_GI0_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_GI1_ADDR);
REG_FIELD_SET(SW_PLD_GI2, tmp, 0x108 );
PHY_WRITE_REG(CFG_BB_PLD_GI1_ADDR, tmp);
/* fix bug */
tmp = PHY_TX_READ_REG(CFG_BB_TX_NSG_PRE_CAL_ADDR);
REG_FIELD_SET(SW_MINUS_VALUE,tmp,0);
REG_FIELD_SET(SW_FORBID_ONCE_NSG_ROBO,tmp,1);
PHY_TX_WRITE_REG(CFG_BB_TX_NSG_PRE_CAL_ADDR,tmp);
/* set preamble number */
tmp = PHY_TX_READ_REG(CFG_BB_TX_NSG_PREAM_NUM0_ADDR);
REG_FIELD_SET(SW_NSG_BMCS_BAND0_PREAM_NUM,tmp,13);
REG_FIELD_SET(SW_NSG_BMCS_BAND1_PREAM_NUM,tmp,13);
REG_FIELD_SET(SW_NSG_BMCS_BAND2_PREAM_NUM,tmp,13);
PHY_TX_WRITE_REG(CFG_BB_TX_NSG_PREAM_NUM0_ADDR,tmp);
/* set pream num */
tmp = PHY_TX_READ_REG(CFG_BB_TX_NSG_PREAM_NUM1_ADDR);
REG_FIELD_SET(SW_NSG_EMCS_BAND0_PREAM_NUM,tmp,13);
REG_FIELD_SET(SW_NSG_EMCS_BAND1_PREAM_NUM,tmp,13);
REG_FIELD_SET(SW_NSG_EMCS_BAND2_PREAM_NUM,tmp,13);
PHY_TX_WRITE_REG(CFG_BB_TX_NSG_PREAM_NUM1_ADDR,tmp);
/* add more agc intergation time to enhance anti-noise */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
}
else if(mac_typ == PLC_PROTO_TYPE_GP)
{/*************************GP***************************/
tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
REG_FIELD_SET(SW_TX_PRE_NUM,tmp,10);
REG_FIELD_SET(SW_TX_PRE_MODE,tmp,1);
REG_FIELD_SET(SW_PRE_REF_PHASE, tmp,1);
PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
REG_FIELD_SET(SW_TX_PLD_MODE, tmp, 0x1 );
REG_FIELD_SET(SW_PLD_REF_PHASE, tmp, 0x1 );
REG_FIELD_SET(SW_CI_HBS_DIR, tmp, 0x1 );
PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_CRC_CFG_ADDR);
REG_FIELD_SET(SW_PLD_CRC_BY_SW, tmp, 0x0 );
REG_FIELD_SET(SW_FC_CRC_MODE, tmp, 0x0 );
REG_FIELD_SET(SW_PLD_CRC_MODE, tmp, 0x1 );
REG_FIELD_SET(SW_FC_CRC_INITIAL, tmp, 0x1 );
REG_FIELD_SET(SW_PLD_CRC_INITIAL, tmp, 0x1 );
REG_FIELD_SET(SW_FC_CRC_INV, tmp, 0x1 );
REG_FIELD_SET(SW_PLD_CRC_INV, tmp, 0x1 );
PHY_WRITE_REG(CFG_BB_CRC_CFG_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_CRC_REM_ADDR);
REG_FIELD_SET(SW_FC_CRC_REMAIN, tmp, 0x800fe3 );
PHY_WRITE_REG(CFG_BB_FC_CRC_REM_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_CRC_REM_ADDR);
REG_FIELD_SET(SW_PLD_CRC_REMAIN, tmp, 0xc704dd7b );
PHY_WRITE_REG(CFG_BB_PLD_CRC_REM_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_FC_GI_ADDR);
REG_FIELD_SET(SW_FC_GI0, tmp, 0x55e );
REG_FIELD_SET(SW_FC_GI0_RANGE, tmp, 0x1 );
REG_FIELD_SET(SW_FC_GI1, tmp, 0x55e );
PHY_WRITE_REG(CFG_BB_FC_GI_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_GI0_ADDR);
REG_FIELD_SET(SW_PLD_GI0, tmp, 0x237 );
REG_FIELD_SET(SW_PLD_GI0_RANGE, tmp, 0x2 );
REG_FIELD_SET(SW_PLD_GI1, tmp, 0x237 );
REG_FIELD_SET(SW_PLD_GI1_RANGE, tmp, 0x8 );
PHY_WRITE_REG(CFG_BB_PLD_GI0_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PLD_GI1_ADDR);
REG_FIELD_SET(SW_PLD_GI2, tmp, 0x237 );
PHY_WRITE_REG(CFG_BB_PLD_GI1_ADDR, tmp);
tmp = PHY_TX_READ_REG(CFG_BB_TX_TURBO_SET_ADDR);
/* TODO: this parameter configuration is invalid,
* GP to be verified
*/
REG_FIELD_SET(SW_TX_SCRAMBLE_BASED_PPDU,tmp,1);
PHY_TX_WRITE_REG(CFG_BB_TX_TURBO_SET_ADDR,tmp);
#if CHIP_BRINGUP_DEBUG == 1
tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
REG_FIELD_SET(SW_SCRAMBLE_PB_EN,tmp,0);
REG_FIELD_SET(SW_SCRAMBLE_RESET_MODE,tmp,0);
REG_FIELD_SET(SW_SCRAMBLE_MODE,tmp,0);
PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR,tmp);
#endif
/* add more agc intergation time to enhance anti-noise */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_SET_VLD,tmp,1);
REG_FIELD_SET(SW_AGC_ACC_STEP,tmp,1);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
/* add more agc intergation time to enhance anti-noise */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,2);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
}
/* modify to flat noise */
tmp = PHY_RX_FD_READ_REG(CFG_BB_WIENER_FILTER0_ADDR);
REG_FIELD_SET(SW_WIENER_FILTER_EN,tmp,1);
REG_FIELD_SET(SW_FILTER0_RANGE,tmp,4);
PHY_RX_FD_WRITE_REG(CFG_BB_WIENER_FILTER0_ADDR,tmp);
tmp = PHY_RX_FD_READ_REG(CFG_BB_WIENER_FILTER1_ADDR);
REG_FIELD_SET(SW_FILTER1_RANGE,tmp,4);
PHY_RX_FD_WRITE_REG(CFG_BB_WIENER_FILTER1_ADDR,tmp);
tmp = PHY_RX_FD_READ_REG(CFG_BB_WIENER_FILTER2_ADDR);
REG_FIELD_SET(SW_FILTER2_RANGE,tmp,4);
PHY_RX_FD_WRITE_REG(CFG_BB_WIENER_FILTER2_ADDR,tmp);
tmp = PHY_RX_FD_READ_REG(CFG_BB_WIENER_FILTER3_ADDR);
REG_FIELD_SET(SW_FILTER3_RANGE,tmp,4);
PHY_RX_FD_WRITE_REG(CFG_BB_WIENER_FILTER3_ADDR,tmp);
#else
(void)mac_typ;
#endif
}
/* bb mix flag set */
void phy_mix_flag_set(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
PHY_RXTD_WRITE_REG(CFG_BB_MIX_FLAG_ADDR,en);
#else
(void)en;
#endif
}
void phy_pkt_time_out_disable(bool_t disable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_PKT_TIME_OUT_ADDR);
REG_FIELD_SET(SW_PKT_DET_TIME_OUT_DISABLE, tmp, disable);
PHY_RXTD_WRITE_REG(CFG_BB_PKT_TIME_OUT_ADDR,tmp);
#else
(void)disable;
#endif
}
/* bb phy rxtd common init */
void phy_rxtd_common_init(uint32_t mac_typ)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
if(mac_typ == PLC_PROTO_TYPE_SG || \
mac_typ == PLC_PROTO_TYPE_SPG)
{
tmp = PHY_RXTD_READ_REG(CFG_BB_STOP_FFT_ENGINE_ADDR);
REG_FIELD_SET(SW_THRESHOLD_STOP_FFT_3K, tmp, 0x660 );
REG_FIELD_SET(SW_THRESHOLD_STOP_FFT_384, tmp, 0xff );
PHY_RXTD_WRITE_REG(CFG_BB_STOP_FFT_ENGINE_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_DLY_ADDR);
REG_FIELD_SET(SW_GAIN_DLY, tmp, 300 );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_DLY_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LOOP_ADDR);
REG_FIELD_SET(SW_GAIN_LOOP, tmp, 0x4 );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_LOOP_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_SAT_TH_ADDR);
REG_FIELD_SET(SW_SAT_ATTEN_DB,tmp,0xd8);
REG_FIELD_SET(SW_PWR_SAT_DLY_LEN,tmp,2);
REG_FIELD_SET(SW_PWR_SAT_TH,tmp,360);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_SAT_TH_ADDR,tmp);
phy_agc_sat_jug_cnt_set(64);
/* MIX flag */
phy_mix_flag_set(false);
/* increase to receive more preamble within cifs */
tmp = PHY_RXTD_READ_REG(CFG_BB_PKT_TIME_OUT_ADDR);
REG_FIELD_SET(SW_PKT_DET_TIME_OUT,tmp,45000);
PHY_RXTD_WRITE_REG(CFG_BB_PKT_TIME_OUT_ADDR,tmp);
/* not reset when drop */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_DROP_TH_ADDR);
REG_FIELD_SET(SW_DROP_RESTART_DIS, tmp, 1 );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_DROP_TH_ADDR, tmp);
/* not reset when up */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_RAMUP_TH_ADDR);
REG_FIELD_SET(SW_RAMPUP_RESTART_DIS, tmp, 1 );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_RAMUP_TH_ADDR, tmp);
/* full */
phy_agc_sat_rst_dis_set(1);
}
else if (mac_typ == PLC_PROTO_TYPE_GP)
{
tmp = PHY_RXTD_READ_REG(CFG_BB_STOP_FFT_ENGINE_ADDR);
REG_FIELD_SET(SW_THRESHOLD_STOP_FFT_3K, tmp, 0x660 );
REG_FIELD_SET(SW_THRESHOLD_STOP_FFT_384, tmp, 0xff );
PHY_RXTD_WRITE_REG(CFG_BB_STOP_FFT_ENGINE_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_DLY_ADDR);
REG_FIELD_SET(SW_GAIN_DLY, tmp, 210 );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_DLY_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LOOP_ADDR);
REG_FIELD_SET(SW_GAIN_LOOP, tmp, 0x4 );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_LOOP_ADDR, tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_SAT_TH_ADDR);
REG_FIELD_SET(SW_PWR_SAT_TH,tmp,0x1e0);
REG_FIELD_SET(SW_SAT_ATTEN_DB,tmp,0xd8);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_SAT_TH_ADDR,tmp);
phy_agc_sat_jug_cnt_set(16);
tmp = PHY_RXTD_READ_REG(CFG_BB_PKT_TIME_OUT_384_ADDR);
REG_FIELD_SET(SW_PKT_DET_TIME_OUT_384,tmp,4000);
PHY_RXTD_WRITE_REG(CFG_BB_PKT_TIME_OUT_384_ADDR,tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_ADC_TIME_OUT_ADDR);
REG_FIELD_SET(SW_ADC_PWR_FALL_TIME_OUT,tmp,150000);
PHY_RXTD_WRITE_REG(CFG_BB_ADC_TIME_OUT_ADDR,tmp);
/* MIX flag */
phy_mix_flag_set(false);
}
tmp = PHY_RXTD_READ_REG(CFG_BB_MINUS_PRE_TIME_OUT_384_ADDR);
REG_FIELD_SET(SW_FIND_MINUS_PREAM_TIME_OUT_384,tmp,4000);
PHY_RXTD_WRITE_REG(CFG_BB_MINUS_PRE_TIME_OUT_384_ADDR,tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_MINUS_PRE_TIME_OUT_3K_ADDR);
REG_FIELD_SET(SW_FIND_MINUS_PREAM_TIME_OUT_3K,tmp,50000);/* Must big for hisi */
PHY_RXTD_WRITE_REG(CFG_BB_MINUS_PRE_TIME_OUT_3K_ADDR,tmp);
tmp = PHY_RXTD_READ_REG(CFG_BB_MINU_SYMBO_CNTR_ADDR);
REG_FIELD_SET(SW_MINU_SYMB_CNTR_SG, tmp, 1800 );
PHY_RXTD_WRITE_REG(CFG_BB_MINU_SYMBO_CNTR_ADDR, tmp);
/* enable reset by full */
phy_agc_sat_adj_set(0, 0);
#else
(void)mac_typ;
#endif
}
/* true turbo en */
void phy_turbo_dec_en(bool_t en)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
REG_FIELD_SET(SW_TURBO_DEC_CRC_EN,tmp,en);
PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR,tmp);
#else
(void)en;
#endif
}
/* true turbo scramble pb en */
void phy_turbo_scrb_en(bool_t en)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
REG_FIELD_SET(SW_SCRAMBLE_PB_EN,tmp,en);
PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR,tmp);
#else
(void)en;
#endif
}
/* agc gain level */
void phy_agc_gain_lvl_set(bool_t en, int8_t max, int8_t min, int8_t ini)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR);
REG_FIELD_SET(SW_MAX_GAIN, tmp, max );
REG_FIELD_SET(SW_MIN_GAIN, tmp, min );
REG_FIELD_SET(SW_INI_GAIN, tmp, ini );
REG_FIELD_SET(SW_FIX_GAIN_EN, tmp, en );
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR, tmp);
#else
(void)en;
(void)max;
(void)min;
(void)ini;
#endif
}
/* phy dfe common init */
void phy_dfe_common_init(void)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_DFE_READ_REG(CFG_BB_GAIN_ADJ_TIME_ADDR);
REG_FIELD_SET(SW_GAIN_ADJ_TIME,tmp,172);
PHY_DFE_WRITE_REG(CFG_BB_GAIN_ADJ_TIME_ADDR,tmp);
#if HW_PLATFORM == HW_PLATFORM_FPGA
PHY_DFE_WRITE_REG(CFG_BB_ADA_FORMAT_CFG_ADDR,0x0);
#endif
/* enable freq ppm bias */
tmp = PHY_DFE_READ_REG(CFG_BB_PPM_FIFO_SETTING_ADDR);
REG_FIELD_SET(SW_EN_RX_FREQ_PPM,tmp,0);
PHY_DFE_WRITE_REG(CFG_BB_PPM_FIFO_SETTING_ADDR,tmp);
#endif
}
/* new sg support */
void phy_new_sg_en(bool_t en)
{
#if HW_PLATFORM != HW_PLATFORM_SIMUs
uint32_t tmp;
tmp = PHY_READ_REG(CFG_BB_PB_ROBO_ADDR);
if(en){
REG_FIELD_SET(SW_IS_NSG_PB_ROBO,tmp,1);
REG_FIELD_SET(SW_MN_INVERT,tmp,1);
}
else{
REG_FIELD_SET(SW_IS_NSG_PB_ROBO,tmp,0);
REG_FIELD_SET(SW_MN_INVERT,tmp,0);
}
PHY_WRITE_REG(CFG_BB_PB_ROBO_ADDR,tmp);
#else
(void)en;
#endif
}
void phy_rate_band_set(uint32_t rate_id, uint32_t band_id, uint32_t fc_sym, \
uint32_t start_tone, uint32_t end_tone)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
if(rate_id == 0)
{
if (band_id == HW_FULL_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B0_TONE_ADDR);
REG_FIELD_SET(SW_RATE0_BAND0_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_RATE0_BAND0_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_RATE0_BAND0_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_R0_B0_TONE_ADDR, tmp);
}
else if (band_id == HW_LOW_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B1_TONE_ADDR);
REG_FIELD_SET(SW_RATE0_BAND1_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_RATE0_BAND1_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_RATE0_BAND1_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_R0_B1_TONE_ADDR, tmp);
}
else if (band_id == HW_HIGH_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R0_B2_TONE_ADDR);
REG_FIELD_SET(SW_RATE0_BAND2_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_RATE0_BAND2_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_RATE0_BAND2_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_R0_B2_TONE_ADDR, tmp);
}
}
else if(rate_id == 1){
if (band_id == HW_FULL_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B0_TONE_ADDR);
REG_FIELD_SET(SW_RATE1_BAND0_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_RATE1_BAND0_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_RATE1_BAND0_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_R1_B0_TONE_ADDR, tmp);
}
else if (band_id == HW_LOW_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B1_TONE_ADDR);
REG_FIELD_SET(SW_RATE1_BAND1_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_RATE1_BAND1_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_RATE1_BAND1_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_R1_B1_TONE_ADDR, tmp);
}
else if (band_id == HW_HIGH_BAND)
{
tmp = PHY_READ_REG(CFG_BB_R1_B2_TONE_ADDR);
REG_FIELD_SET(SW_RATE1_BAND2_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_RATE1_BAND2_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_RATE1_BAND2_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_R1_B2_TONE_ADDR, tmp);
}
}
#else
(void)rate_id;
(void)band_id;
(void)fc_sym;
(void)start_tone;
(void)end_tone;
#endif
return;
}
void phy_short_band_set(uint32_t fc_sym, uint32_t start_tone, uint32_t end_tone)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_SHORT_PREAM_TONE_ADDR);
REG_FIELD_SET(SW_SHORT_PREAM_FC_NUM, tmp, fc_sym);
REG_FIELD_SET(SW_SHORT_PREAM_END_TONE, tmp, end_tone);
REG_FIELD_SET(SW_SHORT_PREAM_START_TONE, tmp, start_tone);
PHY_WRITE_REG(CFG_BB_SHORT_PREAM_TONE_ADDR, tmp);
#else
(void)fc_sym;
(void)start_tone;
(void)end_tone;
#endif
return;
}
/* bb pkt statistics */
void phy_sts_get(iot_phy_sts_info_t *pkt_sts)
{
uint32_t tmp = 0;
pkt_sts->fc_crc_ok_cnt = PHY_READ_REG(CFG_BB_FC_CRC_OK_CNTR_ADDR);
pkt_sts->fc_crc_fail_cnt = PHY_READ_REG(CFG_BB_FC_CRC_ERROR_CNTR_ADDR);
pkt_sts->pld_crc_ok_cnt = PHY_READ_REG(CFG_BB_PLD_CRC_OK_CNTR_ADDR);
pkt_sts->pld_crc_fail_cnt = PHY_READ_REG(CFG_BB_PLD_CRC_ERROR_CNTR_ADDR);
PHY_WRITE_REG(CFG_BB_FC_PLD_CNTR_CLR_ADDR,0xF);
pkt_sts->sync_ok_cnt = PHY_RXTD_READ_REG(CFG_BB_RX_TD_PKT_CNT_ADDR) + \
PHY_RXTD_READ_REG(CFG_BB_RX_TD_PKT_LS_CNT_ADDR);
PHY_RXTD_WRITE_REG(CFG_BB_RX_TD_PKT_CNT_RST_ADDR,0x1);
uint32_t mac_tmp = RGF_MAC_READ_REG(CFG_TX_DBG_CNT_ADDR);
pkt_sts->mac_tx_ok_cnt = REG_FIELD_GET(DBG_TX_CNT, mac_tmp);
pkt_sts->mac_tx_abort_cnt = REG_FIELD_GET(PHY_TX_ABORT_DBG_CNT, mac_tmp);
tmp = RGF_MAC_READ_REG(CFG_TX_DBG_CTRL_ADDR);
REG_FIELD_SET(CFG_TX_DBG_CNT_CLR,tmp,0x1);
RGF_MAC_WRITE_REG(CFG_TX_DBG_CTRL_ADDR,tmp);
}
/* bb wk to st parameter */
void phy_wk_to_st_set(uint32_t thd)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_WK_TO_ST_TH_ADDR);
REG_FIELD_SET(SW_WK_TO_ST_TH, tmp, thd);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_WK_TO_ST_TH_ADDR, tmp);
#else
(void)thd;
#endif
}
/* rxfd rate0 */
void phy_rxfd_rate0_det(uint32_t start, uint32_t end)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_RATE0_DET_BAND_ADDR);
REG_FIELD_SET(SW_RATE0_DET_END_TONE,tmp,end);
REG_FIELD_SET(SW_RATE0_DET_START_TONE,tmp,start);
PHY_RX_FD_WRITE_REG(CFG_BB_RATE0_DET_BAND_ADDR,tmp);
#else
(void)start;
(void)end;
#endif
}
/* rxfd rate1 */
void phy_rxfd_rate1_det(uint32_t start, uint32_t end)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_RATE1_DET_BAND_ADDR);
REG_FIELD_SET(SW_RATE1_DET_END_TONE,tmp,end);
REG_FIELD_SET(SW_RATE1_DET_START_TONE,tmp,start);
PHY_RX_FD_WRITE_REG(CFG_BB_RATE1_DET_BAND_ADDR,tmp);
#else
(void)start;
(void)end;
#endif
}
/* rxfd pkt detect thrd */
void phy_rxfd_pkt_det_thd_set(uint8_t thr0, uint8_t thr1)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_PKT_DET_ADDR);
REG_FIELD_SET(SW_SYMB_DET_THR1, tmp, thr1);
REG_FIELD_SET(SW_SYMB_DET_THR0, tmp, thr0);
PHY_RX_FD_WRITE_REG(CFG_BB_PKT_DET_ADDR,tmp);
#else
(void)thr0;
(void)thr1;
#endif
}
/* rxfd pkt detect thrd get */
void phy_rxfd_pkt_det_thd_get(uint8_t *thr0, uint8_t *thr1)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_PKT_DET_ADDR);
*thr0 = REG_FIELD_GET(SW_SYMB_DET_THR0, tmp);
*thr1 = REG_FIELD_GET(SW_SYMB_DET_THR1, tmp);
#else
(void)thr0;
(void)thr1;
#endif
}
/* rxfd pkt detect thrd */
void phy_rxfd_frame_sync_set(uint8_t sync_thr)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_FRAME_SYNC_ADDR);
REG_FIELD_SET(SW_FRAME_SYNC_THR, tmp, sync_thr);
PHY_RX_FD_WRITE_REG(CFG_BB_FRAME_SYNC_ADDR,tmp);
#else
(void)sync_thr;
#endif
}
/* rxfd rate offset */
void phy_rxfd_rate_offset_set(uint16_t offset)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
tmp = PHY_RX_FD_READ_REG(CFG_BB_RATE_OFFET_ADDR);
REG_FIELD_SET(SW_CSI_RATE1_OFFSET, tmp, offset);
PHY_RX_FD_WRITE_REG(CFG_BB_RATE_OFFET_ADDR, tmp);
#else
(void)offset;
#endif
}
/* freq shift self comp */
void phy_freq_shift_self_comp(bool_t fd_en, bool_t td_en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* AGC bypass mode */
tmp = PHY_RX_FD_READ_REG(CFG_BB_FREQ_ERROR_ADDR);
REG_FIELD_SET(SW_FD_COMP_EN, tmp, fd_en);
REG_FIELD_SET(SW_TD_COMP_EN, tmp, td_en);
PHY_RX_FD_WRITE_REG(CFG_BB_FREQ_ERROR_ADDR, tmp);
#else
(void)fd_en;
(void)td_en;
#endif
}
/* tx rate mode */
void phy_tx_rate_mode_ovr_set(bool_t en, uint32_t rate_mode)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_1_ADDR);
REG_FIELD_SET(SW_TX_RATE_MODE_OVR_EN,tmp,en);
REG_FIELD_SET(SW_TX_RATE_MODE_OVR,tmp,rate_mode);
PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_1_ADDR,tmp);
#else
(void)en;
(void)rate_mode;
#endif
}
uint8_t phy_tx_rate_mode_ovr_get(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_1_ADDR);
if (REG_FIELD_GET(SW_TX_RATE_MODE_OVR_EN, tmp)) {
return REG_FIELD_GET(SW_TX_RATE_MODE_OVR, tmp);
} else {
return IOT_SUPPORT_RATE_SR;
}
#else
return IOT_SUPPORT_RATE_SR;
#endif
}
/* rx rate mode */
void phy_rx_rate_mode_ovr_set(bool_t en, uint32_t rate_mode)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_1_ADDR);
REG_FIELD_SET(SW_RX_RATE_MODE_OVR_EN,tmp,en);
REG_FIELD_SET(SW_RX_RATE_MODE_OVR,tmp,rate_mode);
PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_1_ADDR,tmp);
#else
(void)en;
(void)rate_mode;
#endif
}
/* gain table mode */
void phy_gain_table_ovr_set(bool_t en, uint8_t tbl)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_1_ADDR);
REG_FIELD_SET(SW_GAIN_TABLE_OVR_EN,tmp,en);
REG_FIELD_SET(SW_GAIN_TABLE_OVR,tmp,tbl);
PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_1_ADDR,tmp);
#else
(void)en;
(void)tbl;
#endif
}
/* fix dfe txrx mode */
void phy_txrx_ovr_set(bool_t en, uint32_t mode)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_0_ADDR);
REG_FIELD_SET(SW_MAC_TXRX_OVR_EN,tmp,en);
REG_FIELD_SET(SW_MAC_TXRX_OVR,tmp,mode);
PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_0_ADDR,tmp);
#else
(void)en;
(void)mode;
#endif
}
/* fix dac data by over */
void phy_dac_data_ovr_set(bool_t en, uint32_t data)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_0_ADDR);
REG_FIELD_SET(SW_DAC_DATA_OVR_EN,tmp,en);
REG_FIELD_SET(SW_DAC_DATA_OVR,tmp,data);
PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_0_ADDR,tmp);
#else
(void)en;
(void)data;
#endif
}
/* dc comp */
void phy_dc_comp_gain_set(uint16_t gain0, uint16_t gain1, \
uint16_t gain2, uint16_t gain3)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP0_ADDR);
REG_FIELD_SET(SW_DC_COMP_GAIN0,tmp,gain0);
REG_FIELD_SET(SW_DC_COMP_GAIN1,tmp,gain1);
PHY_DFE_WRITE_REG(CFG_BB_DC_COMP0_ADDR,tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP1_ADDR);
REG_FIELD_SET(SW_DC_COMP_GAIN2,tmp,gain2);
REG_FIELD_SET(SW_DC_COMP_GAIN3,tmp,gain3);
PHY_DFE_WRITE_REG(CFG_BB_DC_COMP1_ADDR,tmp);
#else
(void)gain0;
(void)gain1;
(void)gain2;
(void)gain3;
#endif
}
/* lic flag */
void phy_lic_flag_set(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_LIC_FLAG_CFG_ADDR);
REG_FIELD_SET(SW_LIC_FLAG_INT_EN,tmp,en);
PHY_DFE_WRITE_REG(CFG_BB_LIC_FLAG_CFG_ADDR,tmp);
#else
(void)en;
#endif
}
/* lic flag */
void phy_lic_flag_th_cnt_set(uint8_t cnt)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_LIC_FLAG_CFG_ADDR);
REG_FIELD_SET(SW_LIC_FLAG_CNT_TH,tmp,cnt);
PHY_DFE_WRITE_REG(CFG_BB_LIC_FLAG_CFG_ADDR,tmp);
#else
(void)cnt;
#endif
}
/* DPSK control */
void phy_dpsk_en(uint8_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(!en){
tmp = PHY_READ_REG(CFG_BB_DPSK_CTRL_ADDR);
REG_FIELD_SET(SW_DPSK_IS_FORBIDDEN, tmp, 1);
REG_FIELD_SET(SW_IS_DPSK, tmp, 0);
PHY_WRITE_REG(CFG_BB_DPSK_CTRL_ADDR, tmp);
}
else{
tmp = PHY_READ_REG(CFG_BB_DPSK_CTRL_ADDR);
REG_FIELD_SET(SW_DPSK_IS_FORBIDDEN, tmp, 0);
REG_FIELD_SET(SW_IS_DPSK, tmp, 1);
PHY_WRITE_REG(CFG_BB_DPSK_CTRL_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PB_ROBO_ADDR);
REG_FIELD_SET(SW_IS_NSG_PB_ROBO,tmp,0);
PHY_WRITE_REG(CFG_BB_PB_ROBO_ADDR,tmp);
}
#else
(void)en;
#endif
}
/* turbo dec inter */
void phy_turbo_dec_inter_set(uint8_t iter_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* bb turbo ctrl */
tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
REG_FIELD_SET(SW_TURBO_DEC_PB_MAX_ITER,tmp,iter_num);
REG_FIELD_SET(SW_TURBO_DEC_FC_MAX_ITER,tmp,iter_num);
PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR,tmp);
#else
(void)iter_num;
#endif
}
/* multi rate common init */
void phy_qr_common_init(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
phy_agc_rcv_thrd_set(1,0xf,0xf,1,0xf,0xf);
tmp = PHY_RXTD_READ_REG(CFG_BB_MINUS_PRE_TIME_OUT_3K_ADDR);
REG_FIELD_SET(SW_FIND_MINUS_PREAM_TIME_OUT_3K,tmp,62000);
PHY_RXTD_WRITE_REG(CFG_BB_MINUS_PRE_TIME_OUT_3K_ADDR,tmp);
#endif
}
void enable_sw_access_tmi_buf(uint32_t enable) {
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
/* enable MAC */
tmp = PHY_READ_REG(CFG_BB_SW_ACCESS_BUF_ADDR);
REG_FIELD_SET(SW_ACCESS_TMI_BUF_EN, tmp, enable);
PHY_WRITE_REG(CFG_BB_SW_ACCESS_BUF_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
void enable_sw_access_gain_buf(uint32_t enable) {
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
/* enable MAC */
tmp = PHY_READ_REG(CFG_BB_SW_ACCESS_BUF_ADDR);
REG_FIELD_SET(SW_ACCESS_AGC_GAIN_BUF_EN, tmp, enable);
PHY_WRITE_REG(CFG_BB_SW_ACCESS_BUF_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
void enable_sw_access_csi_buf(uint32_t enable) {
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
/* enable MAC */
tmp = PHY_READ_REG(CFG_BB_SW_ACCESS_BUF_ADDR);
REG_FIELD_SET(SW_ACCESS_CSI_BUF_EN, tmp, enable);
PHY_WRITE_REG(CFG_BB_SW_ACCESS_BUF_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
void enable_sw_access_loopback(uint32_t enable) {
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp;
/* enable loopback */
tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
REG_FIELD_SET(SW_LOOPBACK_EN, tmp, enable);
PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
void phy_agc_gain_adj_dis(uint32_t msk)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_ON_CFG_MASK_ADDR);
REG_FIELD_SET(SW_RX_ON_CFG_DATA_MASK, tmp, msk);
PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_ON_CFG_MASK_ADDR, tmp);
#else
(void)msk;
#endif
}
/* tone0/1 control */
void IRAM_ATTR phy_dfe_tone_cfg(bool_t tone_en, uint32_t tone0_num,
uint32_t tone1_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_TX_TONE_0_CFG_ADDR);
REG_FIELD_SET( SW_TONE_CFG_EN, tmp, tone_en );
REG_FIELD_SET( SW_TONE_0_CFG_NUM, tmp, tone0_num );
REG_FIELD_SET( SW_TONE_1_CFG_NUM, tmp, tone1_num );
PHY_DFE_WRITE_REG(CFG_BB_TX_TONE_0_CFG_ADDR, tmp);
#else
(void)tone_en;
(void)tone0_num;
(void)tone1_num;
#endif
}
/* tone0/1 att control */
void phy_dfe_tone_att_cfg(uint32_t dc_offset, uint32_t tone0_atten, \
uint32_t tone1_atten)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_TX_TONE_1_CFG_ADDR);
REG_FIELD_SET( SW_TONE_DC_OFFSET, tmp, dc_offset );
REG_FIELD_SET( SW_TONE_0_ATTEN, tmp, tone0_atten );
REG_FIELD_SET( SW_TONE_1_ATTEN, tmp, tone1_atten );
PHY_DFE_WRITE_REG(CFG_BB_TX_TONE_1_CFG_ADDR, tmp);
#else
(void)dc_offset;
(void)tone0_atten;
(void)tone1_atten;
#endif
}
void phy_anf_top_option_set(uint8_t option_val)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_CFG_ADDR);
REG_FIELD_SET(SW_ANF_OPTION, tmp, option_val);
PHY_DFE_WRITE_REG(CFG_BB_ANF_CFG_ADDR, tmp);
#else
(void)option_val;
#endif
}
void phy_anf_option_set(PHY_ANF_MODE_ID mode, \
uint32_t data_shift_num, \
uint8_t anf_id, \
uint16_t anf_alpha)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
if(mode == PHY_ANF_MODE_BYPASS)
{
if(anf_id == 1)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_OPTION1, tmp, PHY_ANF_OPT_BYPASS );
PHY_DFE_WRITE_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR, tmp);
}
else if(anf_id == 2)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_OPTION2, tmp, PHY_ANF_OPT_BYPASS );
PHY_DFE_WRITE_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR, tmp);
}
else {
/* NF 1 bypass */
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_OPTION1, tmp, PHY_ANF_OPT_BYPASS );
PHY_DFE_WRITE_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR, tmp);
/* NF 2 bypass */
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_OPTION2, tmp, PHY_ANF_OPT_BYPASS );
PHY_DFE_WRITE_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR, tmp);
/* NF top bypass */
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_CFG_ADDR);
REG_FIELD_SET(SW_ANF_OPTION, tmp, PHY_ANF_MODE_BYPASS );
PHY_DFE_WRITE_REG(CFG_BB_ANF_CFG_ADDR, tmp);
}
}
else if(mode == PHY_ANF_MODE_FIX)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_CFG_ADDR);
REG_FIELD_SET(SW_ANF_OPTION, tmp, 4 + (data_shift_num - 1));
PHY_DFE_WRITE_REG(CFG_BB_ANF_CFG_ADDR, tmp);
if(anf_id == 1)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_ALPHA1, tmp, anf_alpha);
REG_FIELD_SET(SW_ANF_OPTION1, tmp, PHY_ANF_OPT_NOTCH_OUT);
PHY_DFE_WRITE_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR, tmp);
}
else if(anf_id == 2)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_ALPHA2, tmp, anf_alpha);
REG_FIELD_SET(SW_ANF_OPTION2, tmp, PHY_ANF_OPT_NOTCH_OUT);
PHY_DFE_WRITE_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR, tmp);
}
}
else if(mode == PHY_ANF_MODE_ADAPT)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_CFG_ADDR);
REG_FIELD_SET(SW_ANF_OPTION, tmp, 4 + (data_shift_num - 1));
PHY_DFE_WRITE_REG(CFG_BB_ANF_CFG_ADDR, tmp);
if(anf_id == 1)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_OPTION1, tmp, PHY_ANF_OPT_ADAPT);
PHY_DFE_WRITE_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR, tmp);
}
else if(anf_id == 2)
{
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_OPTION2, tmp, PHY_ANF_OPT_ADAPT);
PHY_DFE_WRITE_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR, tmp);
}
}
#else
(void)mode;
(void)data_shift_num;
(void)anf_id;
(void)anf_alpha;
#endif
}
void phy_anf_sel_set(uint8_t sel1)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_BETA_SEL1, tmp, sel1);
PHY_DFE_WRITE_REG(CFG_BB_ANF_1_ALPHA_BETA_ADDR, tmp);
#else
(void)sel1;
#endif
}
void phy_anf2_sel_set(uint8_t sel2)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR);
REG_FIELD_SET(SW_ANF_BETA_SEL2, tmp, sel2);
PHY_DFE_WRITE_REG(CFG_BB_ANF_2_ALPHA_BETA_ADDR, tmp);
#else
(void)sel2;
#endif
}
void phy_fnf_option_set(PHY_FNF_MODE_ID mode, uint8_t fnf_id,
uint16_t fnf_alpha)
{
(void)mode;
(void)fnf_id;
(void)fnf_alpha;
}
void phy_fnf_sel_set(uint8_t fnf_id, uint8_t beta)
{
(void)fnf_id;
(void)beta;
}
void phy_dc_blk_alpha_step3_set(uint8_t step3)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* dc block hp */
tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STEP_ADDR);
REG_FIELD_SET(SW_DC_BLK_ALPHA_STEP3, tmp, step3);
PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STEP_ADDR,tmp);
#else
(void)step3;
#endif
}
void phy_dfe_dc_comp_set(uint8_t gain_idx, uint16_t dac_comp)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
switch(gain_idx)
{
case 0:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP0_ADDR);
REG_FIELD_SET(SW_DC_COMP_GAIN0,tmp,dac_comp);
PHY_DFE_WRITE_REG(CFG_BB_DC_COMP0_ADDR,tmp);
break;
case 1:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP0_ADDR);
REG_FIELD_SET(SW_DC_COMP_GAIN1,tmp,dac_comp);
PHY_DFE_WRITE_REG(CFG_BB_DC_COMP0_ADDR,tmp);
break;
case 2:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP1_ADDR);
REG_FIELD_SET(SW_DC_COMP_GAIN2,tmp,dac_comp);
PHY_DFE_WRITE_REG(CFG_BB_DC_COMP1_ADDR,tmp);
break;
case 3:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP1_ADDR);
REG_FIELD_SET(SW_DC_COMP_GAIN3,tmp,dac_comp);
PHY_DFE_WRITE_REG(CFG_BB_DC_COMP1_ADDR,tmp);
break;
default:
break;
}
#else
(void)gain_idx;
(void)dac_comp;
#endif
}
uint16_t phy_dfe_dc_comp_get(uint8_t gain_idx)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
uint16_t dc_cali = 0;
switch(gain_idx)
{
case 0:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP0_ADDR);
dc_cali = REG_FIELD_GET(SW_DC_COMP_GAIN0,tmp);
break;
case 1:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP0_ADDR);
dc_cali = REG_FIELD_GET(SW_DC_COMP_GAIN1,tmp);
break;
case 2:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP1_ADDR);
dc_cali = REG_FIELD_GET(SW_DC_COMP_GAIN2,tmp);
break;
case 3:
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP1_ADDR);
dc_cali = REG_FIELD_GET(SW_DC_COMP_GAIN3,tmp);
break;
default:
break;
}
return dc_cali;
#else
(void)gain_idx;
return 0;
#endif
}
void phy_ctrl_tx_always_en(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = RGF_MAC_READ_REG(CFG_PHY_CTRL_ADDR);
REG_FIELD_SET(CFG_PHY_ALWAYS_TX, tmp, en);
RGF_MAC_WRITE_REG(CFG_PHY_CTRL_ADDR, tmp);
#else
(void)en;
#endif
}
/* phy init entry and must get clk after eb */
void phy_param_init(uint32_t mac_typ)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t proto_band_id = phy_band_id_get();
/* check mac support type */
if (mac_typ > PLC_PROTO_TYPE_SPG)
iot_printf("phy_param_init:mac type error!/r/n");
/* bb version */
phy_version_set(mac_typ);
/* agc control in fpga from sw */
#ifdef IOT_SUPPORT_AGC
phy_agc_hw_en(true);
#else
phy_agc_hw_en(false);
#endif
/* ad/da bits shift */
phy_gain_shift_set(0, 0, 0, 0);
if (mac_typ == PLC_PROTO_TYPE_SG || mac_typ == PLC_PROTO_TYPE_SPG)
{
/* phy common init */
phy_common_init(mac_typ);
phy_rxtd_common_init(mac_typ);
/* fc symbol offset */
/*
* nw fc symb offset have three case:
* 1. band0/1 use nw fc symb offset
* 2. band2 use gw fc symb offset
* 3. mutiband use nw multiband fc symb offset
*/
if (mac_typ == PLC_PROTO_TYPE_SPG) {
if (proto_band_id == IOT_SUPPORT_TONE_MULTI_BAND021) {
phy_fc_symb_offset_set(0x40, 0x20, 0x60, 0x90, \
0x50, 0x30, 0xF0, 0x18, 0xb8, 0x88, 0x28);
} else if (proto_band_id == IOT_SUPPORT_TONE_32_120) {
phy_fc_symb_offset_set(0xc0, 0xa0, 0x60, 0x90, \
0x50, 0x30, 0xf0, 0x18, 0xb8, 0x88, 0x28);
} else {
phy_fc_symb_offset_set(0x40, 0x20, 0x60, 0x10, \
0x50, 0x30, 0x70, 0x0, 0x0, 0x0, 0x0);
}
} else {
phy_fc_symb_offset_set(0xc0, 0xa0, 0x60, 0x90, \
0x50, 0x30, 0xf0, 0x18, 0xb8, 0x88, 0x28);
}
/* gain default value */
if (g_fw_mode == MM_MODE) {
phy_gain_val_set(0, 0);
phy_gain_val_set(1, 0);
}
/* agc target power and threshold */
phy_rx_tgt_pwr_set(PHY_AGC_RCV_TGT_PWR_SG);
phy_agc_rcv_tgt_set(PHY_AGC_RCV_TGT_PWR_SG, 3, 3);
phy_agc_rcv_thrd_set(1,0xf,0xf,1,0xf,0xf);
/* ana tx/rx */
phy_ana_dfe_init();
/* support for new sg */
if (mac_typ == PLC_PROTO_TYPE_SPG) {
/* pkt detect */
phy_wk_to_st_set(125);
phy_pkt_ratio_set(0, 0x40, 0, 0x40);
phy_turbo_scrb_en(false);
}
else {
/* pkt detect */
phy_wk_to_st_set(125);
phy_pkt_ratio_set(0, 0x40, 0, 0x40);
}
}
else/*GP*/
{
/* phy common init */
phy_common_init(PLC_PROTO_TYPE_GP);
phy_rxtd_common_init(PLC_PROTO_TYPE_GP);
/* pkt detect */
phy_wk_to_st_set(90);
phy_pkt_ratio_set(0, 0x40, 0, 0x40);
/* fc symbol offset */
phy_fc_symb_offset_set(0x40, 0x0, 0x0, 0x0, \
0x0, 0x0, 0x0, 0x0, \
0x0, 0x0, 0x0);
/* gain default value */
if (!g_fw_mode)
{
phy_gain_val_set(0, 2);
phy_gain_val_set(1, 2);
}
/* agc target power and threshold */
phy_rx_tgt_pwr_set(PHY_AGC_RCV_TGT_PWR_GP);
phy_agc_rcv_tgt_set(PHY_AGC_RCV_TGT_PWR_GP, 6, 6);
phy_agc_rcv_thrd_set(0, 6, 12, 0, 6, 12);
/* ana tx/rx */
phy_ana_dfe_init();
phy_turbo_scrb_en(false);
//phy_dc_comp_gain_set(43, 27, 18, 14);
/* rxfd offset set for gp csi dump */
phy_rxfd_rate_offset_set(0);
}
/* turbo cfg */
phy_turbo_dec_en(true);
/* agc gain level -12dB~60dB */
phy_agc_gain_lvl_set(false, 60, 0xE8, 0x0);
/* ahb bb dac scale sel by default 3 */
//bb_dac_scale_set(4);
/* phy dfe common init */
phy_dfe_common_init();
#ifdef IOT_SUPPORT_FS_SELF_COMP
phy_freq_shift_self_comp(false, true);
#endif
/* fix rx rate mode */
//phy_rx_rate_mode_ovr_set(true,IOT_RATE_MODE_RX);
/* dpsk mode */
phy_dpsk_en(false);
/* max tuebo iter num */
phy_turbo_dec_inter_set(10);
/* CPU switch to 25M */
clk_core_freq_slip_25m_set();
/* disable force tx/rx to avoid mac hang */
phy_txrx_ovr_set(0,0);
/* CPU switch to 150M */
clk_core_freq_slip_150m_set();
/* enable temp over stress */
phy_lic_flag_set(true);
phy_lic_flag_th_cnt_set(20);
/* 16qam backoff */
phy_tx_16qam_backoff_rms_set(9);
/* init power */
phy_pwr_adjust_set(0);
return;
#else
/* SIMU */
(void)mac_typ;
#endif
}
//rawdata mode bb set pb size and turbo rate
uint32_t phy_rawdata_mode_bb_set_ps_tr(uint8_t enable, \
uint8_t pb_size, uint8_t turbo_rate)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_READ_REG(CFG_BB_CONFIG_FC_PARSE_1_ADDR);
REG_FIELD_SET(SW_CONFIG_PB_SIZE_EN, tmp, enable);
REG_FIELD_SET(SW_CONFIG_PB_SIZE, tmp, pb_size); //pb size
REG_FIELD_SET(SW_CONFIG_TURBO_RATE_EN, tmp, enable);
REG_FIELD_SET(SW_CONFIG_TURBO_RATE, tmp, turbo_rate); //turbo_tate
PHY_WRITE_REG(CFG_BB_CONFIG_FC_PARSE_1_ADDR, tmp);
#else
(void)enable;
(void)pb_size;
(void)turbo_rate;
#endif
return 0;
}
/* set bb tmi when mac is in rawdata mode */
uint32_t phy_rawdata_bb_set_tmi(uint32_t proto, uint8_t tmi, \
uint8_t ext_tmi)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint8_t pb_sz =0;
uint8_t turbo_rate = 0;
uint32_t pb_size = 0;
phy_get_pb_size(proto, tmi, ext_tmi, &pb_size);
switch(pb_size){
case PB_SIZE_520:
{
pb_sz = HW_DESC_PB_SIZE_520;
break;
}
case PB_SIZE_264:
{
pb_sz = HW_DESC_PB_SIZE_264;
break;
}
case PB_SIZE_136:
{
pb_sz = HW_DESC_PB_SIZE_136;
break;
}
case PB_SIZE_72:
{
pb_sz = HW_DESC_PB_SIZE_72;
break;
}
default:
IOT_ASSERT(0);
}
if((tmi == 15) && (ext_tmi == 1 || ext_tmi == 2))
{
turbo_rate = 1; // 16/18
}
else
{
turbo_rate = 0; // 1/2
}
phy_rawdata_mode_bb_set_ps_tr(1, pb_sz, turbo_rate);
#else
(void)proto;
(void)tmi;
(void)ext_tmi;
#endif
return 0;
}
void phy_adc_mon_sel_set(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADC MON */
tmp = PHY_DFE_READ_REG(CFG_BB_ADA_FORMAT_CFG_ADDR);
REG_FIELD_SET(SW_MON_ADC_SEL, tmp, en);
PHY_DFE_WRITE_REG(CFG_BB_ADA_FORMAT_CFG_ADDR, tmp);
#else
(void)en;
#endif
}
void IRAM_ATTR_CCO phy_set_rx_abort_rx_phase_force_from_isr(uint32_t rxabort_enable,
uint32_t rx_phase_enable, uint8_t hw_phase)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp;
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
/* rx abort config */
if (rxabort_enable) {
REG_FIELD_SET(CFG_PHY_RX_ABORT, tmp, 0);
}
REG_FIELD_SET(CFG_PHY_RX_ABORT_FORCE_EN, tmp, !!rxabort_enable);
/* rx phase config */
REG_FIELD_SET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp, !!rx_phase_enable);
REG_FIELD_SET(CFG_PHY_RX_PHASE_SEL, tmp, hw_phase);
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
#else
(void)rxabort_enable;
(void)rx_phase_enable;
(void)hw_phase;
#endif
return;
}
uint32_t phy_sg_bmcs_pream_num_get(uint32_t bandid)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_NSG_PREAM_NUM0_ADDR);
if (bandid == 0) {
return REG_FIELD_GET(SW_NSG_BMCS_BAND0_PREAM_NUM, tmp);
} else if (bandid == 1) {
return REG_FIELD_GET(SW_NSG_BMCS_BAND1_PREAM_NUM, tmp);
} else if (bandid == 2) {
return REG_FIELD_GET(SW_NSG_BMCS_BAND2_PREAM_NUM, tmp);
} else {
return 0;
}
#else
(void)bandid;
return 0;
#endif
}
uint32_t phy_sg_emcs_pream_num_get(uint32_t bandid)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_NSG_PREAM_NUM1_ADDR);
if (bandid == 0) {
return REG_FIELD_GET(SW_NSG_EMCS_BAND0_PREAM_NUM, tmp);
} else if (bandid == 1) {
return REG_FIELD_GET(SW_NSG_EMCS_BAND1_PREAM_NUM, tmp);
} else if (bandid == 2) {
return REG_FIELD_GET(SW_NSG_EMCS_BAND2_PREAM_NUM, tmp);
} else {
return 0;
}
#else
(void)bandid;
return 0;
#endif
}
bool_t phy_env_pre_check( \
uint32_t mac_proto, \
uint32_t band_id, \
uint32_t mask_id)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
/* check current clk */
IOT_ASSERT(clk_core_freq_get() == 75000000);
/* check mac_proto */
IOT_ASSERT(mac_proto <= PLC_PROTO_TYPE_RAWDATA);
#else
(void)mac_proto;
#endif
(void)band_id;
(void)mask_id;
return ERR_OK;
}
void phy_agc_step_set(uint8_t step_ls, uint8_t step_hs)
{
uint32_t tmp = 0;
/*
* different acc step
* 192/ 384/ 768/ 1536/ 3072/ 6144/
*/
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp, step_ls);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp, step_hs);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR, tmp);
}
void phy_dc_block_set(uint8_t set_val)
{
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, set_val);
PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);
}
int16_t phy_get_cal_ppm_in_pib()
{
return g_phy_ctxt.dep.phy_cal_ppm_in_oem;
}
void phy_set_soft_shift0(uint32_t value)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_RX_FD_READ_REG(CFG_BB_SOFT_BIT_GEN_ADDR);
REG_FIELD_SET(SW_SOFT_BIT_SHIFT0, tmp, value);
PHY_RX_FD_WRITE_REG(CFG_BB_SOFT_BIT_GEN_ADDR, tmp);
#else
(void)value;
#endif
}
void phy_set_fix_gain_sat_adj_dis(bool_t en, int8_t max,
int8_t min, int8_t ini, bool_t sat_dis, bool_t adj_dis)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR);
REG_FIELD_SET(SW_MAX_GAIN, tmp, max);
REG_FIELD_SET(SW_MIN_GAIN, tmp, min);
REG_FIELD_SET(SW_INI_GAIN, tmp, ini);
REG_FIELD_SET(SW_FIX_GAIN_EN, tmp, en);
REG_FIELD_SET(SW_ADJ_REQ_DIS, tmp, adj_dis);
REG_FIELD_SET(SW_SAT_DIS, tmp, sat_dis);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR, tmp);
#else
(void)en;
(void)max;
(void)min;
(void)ini;
(void)sat_dis;
(void)adj_dis;
#endif
}
void phy_set_g_mt_mode_sel(uint32_t mode)
{
g_phy_cpu_share_ctxt.g_mt_mode_sel = mode;
}
uint32_t phy_get_g_mt_mode_sel(void)
{
return g_phy_cpu_share_ctxt.g_mt_mode_sel;
}
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