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kunlun/plc/halphy/hw2/phy_ana.c
andy c756587541 初始提交
2024-09-28 14:24:04 +08:00

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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "ada_reg.h"
#include "phy_ana.h"
#include "ahb.h"
#include "hw_reg_api.h"
#include "phy_bb.h"
#include "phy_chn.h"
#include "phy_rxtd_reg.h"
#include "phy_rx_fd_reg.h"
#include "phy_dfe_reg.h"
#include "iot_io.h"
#include "hw_phy_api.h"
#include "phy_reg.h"
#include "phy_ana_reg.h"
#include "phy_agc.h"
#include "phy_ana.h"
#include "phy_ana_hw.h"
#if HW_PLATFORM > HW_PLATFORM_FPGA
#include "granite_reg.h"
#endif
extern uint32_t all_mask_gain_table[];
/* ada reg clk enable */
void enable_ada(uint32_t enable)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
if (enable) {
ahb_ada_enable();
} else {
ahb_ada_disable();
}
#else
(void)enable;
#endif
return;
}
/* ada rst */
void warm_rst_ada()
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
ahb_ada_reset();
#endif
return;
}
/* ada power on enable */
void phy_ada_enable(uint32_t enable)
{
if (enable) {
enable = 0x1;
}
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADA power on */
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADA_POWER_ON, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
#endif
return;
}
void phy_ada_clk_ratio_cfg(uint8_t data) {
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADA power on */
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADA_CLK_RATIO, tmp, data);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)data;
#endif
}
/***************************************DAC******************************************/
/* dac buf size conf */
void phy_dac_buf_size_cfg(uint32_t size)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* dac buf size */
tmp = ADA_READ_REG(CFG_DAC_CFG0_ADDR);
REG_FIELD_SET(DAC_BUF_SIZE, tmp, size);
ADA_WRITE_REG(CFG_DAC_CFG0_ADDR, tmp);
#else
(void)size;
#endif
return;
}
/* dac mux conf, 0-DA_B come from phy and DA_A come from tone, 1 reverse */
void phy_dac_mux_cfg(DA_B_PATH_CFG path)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* DAC mux */
tmp = ADA_READ_REG(CFG_DAC_CFG1_ADDR);
REG_FIELD_SET(DAC_MUX, tmp, path);
ADA_WRITE_REG(CFG_DAC_CFG1_ADDR, tmp);
#else
(void)path;
#endif
return;
}
/* dac clk inv en conf */
void phy_dac_clk_inv_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* DAC clk inv */
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(DAC_CLK_INV, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* dac enable conf */
void phy_dac_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* DAC en */
tmp = ADA_READ_REG(CFG_DAC_CFG0_ADDR);
REG_FIELD_SET(SOC_DAC_EN, tmp, enable);
ADA_WRITE_REG(CFG_DAC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* dac mux conf */
void phy_dac_tone_mode_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_DAC_CFG1_ADDR);
REG_FIELD_SET(TONE_MODE, tmp, enable);
ADA_WRITE_REG(CFG_DAC_CFG1_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* dac tone num conf */
void phy_dac_tone_num_cfg(uint32_t tone_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_DAC_CFG1_ADDR);
REG_FIELD_SET(TONE_NUMBER, tmp, tone_num);
ADA_WRITE_REG(CFG_DAC_CFG1_ADDR, tmp);
#else
(void)tone_num;
#endif
return;
}
/***************************************ADC******************************************/
/* adc enable conf */
void phy_adc_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADC en */
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(SOC_ADC_EN, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc mode conf */
void phy_adc_mode_cfg(ADC_MODE_CFG mode)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* ADC mode select */
if(mode == ADC_MODE_FORCE)
{
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_FORCE_MODE, tmp, true);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_AUTO_MODE, tmp, false);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
}
else
{
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_AUTO_MODE, tmp, true);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
}
#else
(void)mode;
#endif
return;
}
/* adc buf size conf */
void phy_adc_buf_size_cfg(uint32_t buf_size)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* buf size */
tmp = ADA_READ_REG(CFG_ADC_CFG1_ADDR);
REG_FIELD_SET(ADC_BUF_SIZE, tmp, buf_size);
ADA_WRITE_REG(CFG_ADC_CFG1_ADDR, tmp);
#else
(void)buf_size;
#endif
return;
}
/* adc sample size conf */
void phy_adc_sample_size_cfg(uint32_t sample_size)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* sample size */
tmp = ADA_READ_REG(CFG_ADC_CFG3_ADDR);
REG_FIELD_SET(ADC_SAMPLE_SIZE, tmp, sample_size);
ADA_WRITE_REG(CFG_ADC_CFG3_ADDR, tmp);
#else
(void)sample_size;
#endif
return;
}
/* adc threshhold conf */
void phy_adc_thrd_cfg(uint32_t thrd)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_THR_VAL, tmp, thrd);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
#else
(void)thrd;
#endif
return;
}
/* adc clk inv conf */
void phy_adc_clk_inv_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
REG_FIELD_SET(ADC_CLK_INV, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc dmsb inv conf */
void phy_adc_dmsb_inv_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADC_DMSB_INV, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc sample done status */
bool_t phy_adc_is_sample_done()
{
bool_t is_done = 0;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
//sample done;
is_done = (tmp & ADC_SAMPLE_DONE_MASK)?1:0;
#endif
return is_done;
}
/* adc trig en */
void phy_adc_trig_en_cfg(uint32_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
REG_FIELD_SET(ADC_TRIG, tmp, enable);
ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
#else
(void)enable;
#endif
return;
}
/* adc trig addr */
uint32_t phy_adc_trig_addr_get()
{
uint32_t trig_offset = 0;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
trig_offset = REG_FIELD_GET(ADC_TRIG_ADDR, ADA_READ_REG(CFG_ADC_STS0_ADDR));
#endif
return trig_offset;
}
/* get ada power */
uint32_t phy_ada_get_power_on()
{
uint32_t tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
return REG_FIELD_GET(ADA_POWER_ON, tmp);
}
/*************************************************************************************/
/* DAC cfg */
void phy_ada_tx_cfg(DaTxPara_t *tp)
{
/*clk enable*/
enable_ada(true);
//warm_rst_ada();
/* DAC buf size */
phy_dac_buf_size_cfg(tp->buf_size);
/* DAC mux */
phy_dac_mux_cfg(tp->path);
/* DAC clk inv */
phy_dac_clk_inv_cfg(tp->inv_en);
/* dac mux conf */
phy_dac_tone_mode_en_cfg(tp->tone_mode_en);
/* dac tone num conf */
phy_dac_tone_num_cfg(tp->tone_num);
/* DAC en */
phy_dac_en_cfg(false);//mode from phy
}
/* ADC cfg */
void phy_ada_rx_cfg(DaRxPara_t *rp)
{
/*clk enable*/
enable_ada(true);
/* adc mode select */
phy_adc_mode_cfg(rp->mode);
/* ADC buf size conf */
phy_adc_buf_size_cfg(rp->buf_size);
/* ADC sample size conf */
phy_adc_sample_size_cfg(rp->sample_size);
/* ADC threshhold conf */
phy_adc_thrd_cfg(rp->thrd);
/* ADC clk inv conf */
phy_adc_clk_inv_cfg(rp->clk_inv_en);
/* ADC dmsb inv conf */
phy_adc_dmsb_inv_cfg(rp->dmsb_inv_en);
/* ADC en */
//phy_adc_en_cfg(true);
/* valid data from bit[0:9] */
phy_agc_adc_data_set(1,4);
}
void phy_ana_tx_set(bool_t tx_en, bool_t dac_en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_TX_EN, tmp, tx_en);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, dac_en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)tx_en;
(void)dac_en;
#endif
}
void phy_ana_rx_set(bool_t rx_en, bool_t adc_en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_RX_FE_EN, tmp, rx_en);
REG_FIELD_SET(SW_ADC_EN, tmp, adc_en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)rx_en;
(void)adc_en;
#endif
}
void phy_ana_sadc_enable(bool_t enable)//KL2 sadc in soc.
{
}
/* bb ana tx/rx */
void phy_ana_dfe_init(void)
{
}
void phy_ana_set_filter_init(uint32_t band_id)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
(void)band_id;
uint32_t wdata = 0;
uint32_t tmp = 0;
uint32_t end_tone = 0;
/* get end tone */
tmp = PHY_READ_REG(CFG_BB_R0_B0_TONE_ADDR);
end_tone = REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp);
tmp = PHY_READ_REG(CFG_BB_R1_B0_TONE_ADDR);
if (end_tone < REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp)) {
end_tone = REG_FIELD_GET(SW_RATE0_BAND0_END_TONE, tmp);
}
/* TODO: set mutiband filter */
if (end_tone <= 120) {
wdata = 100;
} else if (end_tone <= 230) {
wdata = (g_phy_ctxt.dep.band_8m_cap_set > 0) ?
g_phy_ctxt.dep.band_8m_cap_set : 55;
} else if (end_tone <= 370) {
wdata = 36; /* rx safe with 12M */
} else if (end_tone <= 500) {
wdata = (g_phy_ctxt.dep.band_15m_cap_set > 0) ?
g_phy_ctxt.dep.band_15m_cap_set : 33;
} else if (end_tone <= 743) {
wdata = (g_phy_ctxt.dep.band_20m_cap_set > 0) ?
g_phy_ctxt.dep.band_20m_cap_set : 21;
} else if (end_tone <= 1000) {
wdata = 17;
} else {
wdata = 8;
}
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
REG_FIELD_SET(SW_RX_FE_SELC_PGF_BQ, tmp, wdata);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
iot_printf("%s bandwidth filter set value: %d.\n", \
__FUNCTION__, wdata);
#else
(void)band_id;
#endif
}
void phy_ana_init(uint32_t band_id)
{
#if HW_PLATFORM == HW_PLATFORM_FPGA
DaTxPara_t tp = {0};
DaRxPara_t rp = {0};
/* ada soft reset */
warm_rst_ada();
/* turn ada on */
phy_ada_enable(true);
/* DAC cfg */
tp.buf_size = 100;
tp.inv_en = true;
tp.path = DA_B_PATH_TONE;
phy_ada_tx_cfg(&tp);
/* ADC cfg */
rp.buf_size = MAC_RX_BUF_SIZE;
rp.sample_size = MAC_RX_SAMPLE_SIZE;
rp.mode = ADC_MODE_FORCE;
rp.thrd = 500;
rp.clk_inv_en = false;
rp.dmsb_inv_en = true;
phy_ada_rx_cfg(&rp);
(void)band_id;
#elif HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
/* sw control tx rx */
phy_ana_hw_en_bitmap(0);
phy_ana_set_filter_init(band_id);
/* fix tx gain */
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR);
REG_FIELD_SET(SW_TX_GPGA, tmp, 3);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_GAIN_ADDR, tmp);
/* en adc and rx, disable dac and tx */
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_EN, tmp, 1);
REG_FIELD_SET(SW_ADC_RESET_N, tmp, 1);
REG_FIELD_SET(SW_RX_FE_EN, tmp, 1);
REG_FIELD_SET(SW_ENLIC_RX, tmp, 1);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, 0);
REG_FIELD_SET(SW_TX_EN, tmp, 0);
REG_FIELD_SET(SW_ENLIC_TX, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
/* hw control tx rx */
phy_ana_hw_en_bitmap(~0);
#else
(void)band_id;
#endif
}
void phy_sadc_pt_init()//KL2: sadc in soc
{
/* not support for kunlun2 */
}
void phy_ana_i2c_write(uint32_t reg_id, uint32_t wdata, uint32_t mask)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp;
switch(reg_id)
{
case CFG_ANA_TOP_REG_ADDR:
if (wdata == 0x8101) {
/* en adc and rx, disable dac and tx */
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_RESET_N, tmp, 1);
REG_FIELD_SET(SW_ADC_EN, tmp, 1);
REG_FIELD_SET(SW_RX_FE_EN, tmp, 1);
REG_FIELD_SET(SW_ENLIC_RX, tmp, 1);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, 0);
REG_FIELD_SET(SW_TX_EN, tmp, 0);
REG_FIELD_SET(SW_ENLIC_TX, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
} else if (wdata == 0x20202) {
/*en analog tx*/
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_RESET_N, tmp, 0);
REG_FIELD_SET(SW_ADC_EN, tmp, 0);
REG_FIELD_SET(SW_RX_FE_EN, tmp, 0);
REG_FIELD_SET(SW_ENLIC_RX, tmp, 0);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, 1);
REG_FIELD_SET(SW_TX_EN, tmp, 1);
REG_FIELD_SET(SW_ENLIC_TX, tmp, 1);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
} else if (wdata == 0x28303) {
/*en tx rx adc dac*/
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_EN, tmp, 1);
REG_FIELD_SET(SW_RX_FE_EN, tmp, 1);
REG_FIELD_SET(SW_ENLIC_RX, tmp, 1);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, 1);
REG_FIELD_SET(SW_TX_EN, tmp, 1);
REG_FIELD_SET(SW_ENLIC_TX, tmp, 1);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
} else if (wdata == 0) {
/* en adc and rx, disable dac and tx */
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_EN, tmp, 0);
REG_FIELD_SET(SW_RX_FE_EN, tmp, 0);
REG_FIELD_SET(SW_ENLIC_RX, tmp, 0);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, 0);
REG_FIELD_SET(SW_TX_EN, tmp, 0);
REG_FIELD_SET(SW_ENLIC_TX, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
}
break;
case CFG_ANA_TX_REG_ADDR:
if(mask == TX_GPGA_MASK) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR);
REG_FIELD_SET(SW_TX_GPGA, tmp, wdata >> TX_GPGA_OFFSET);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_GAIN_ADDR, tmp);
}
break;
case CFG_ANA_BIAS_REG_1_ADDR:
if(wdata == 0xffffffff) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC1_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT1, tmp, ~0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC1_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR1_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT1, tmp, ~0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR1_ADDR, tmp);
}
break;
case CFG_ANA_BIAS_REG_0_ADDR:
if(mask == BIAS_ADJ_IR25U_BIT0_MASK) {
if(wdata == 0) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR0_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT0, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR0_ADDR, tmp);
} else if(wdata == BIAS_ADJ_IR25U_BIT0_MASK) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR0_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT0, tmp, SW_BG_IR25U_ADJ_BIT0_MASK);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR0_ADDR, tmp);
}
} else if(mask == BIAS_ADJ_IR25U_BIT1_MASK) {
if(wdata == 0) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR1_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT1, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR1_ADDR, tmp);
} else if(wdata == BIAS_ADJ_IR25U_BIT1_MASK) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR1_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT1, tmp, SW_BG_IR25U_ADJ_BIT1_MASK);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR1_ADDR, tmp);
}
} else if(mask == BIAS_ADJ_IC25U_BIT0_MASK) {
if(wdata == 0) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC0_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT0, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC0_ADDR, tmp);
} else if(wdata == BIAS_ADJ_IC25U_BIT0_MASK) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC0_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT0, tmp, SW_BG_IC25U_ADJ_BIT0_MASK);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC0_ADDR, tmp);
}
}else if(mask == BIAS_ADJ_IC25U_BIT1_MASK) {
if(wdata == 0) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC1_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT1, tmp, 0);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC1_ADDR, tmp);
} else if(wdata == BIAS_ADJ_IC25U_BIT0_MASK) {
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC1_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT1, tmp, SW_BG_IR25U_ADJ_BIT1_MASK);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC1_ADDR, tmp);
}
}
break;
case CFG_ANA_RX_REG_0_ADDR:
if(mask == RX_SELC_MASK) {
phy_ana_rx_fe_selc_hpf(wdata >> RX_SELC_OFFSET);
}
break;
default:
break;
}
#else
(void)reg_id;
#endif
}
void phy_ana_i2c_read(uint32_t reg_id, uint32_t *rdata, uint8_t *rodata)
{
(void)reg_id;
(void)rdata;
(void)rodata;
}
void phy_ana_tx_comp_set(bool_t tx_en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_CFG_0_ADDR);
REG_FIELD_SET(SW_TX_COMPEN, tmp, tx_en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_CFG_0_ADDR, tmp);
#else
(void)tx_en;
#endif
}
uint32_t phy_ana_tx_pgacomp_read()
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_CFG_0_ADDR);
return REG_FIELD_GET(SW_TX_PGACOMP, tmp);
#else
return 0;
#endif
}
void phy_ana_tx_gpga_set(uint32_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR);
REG_FIELD_SET(SW_TX_GPGA, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_pgfloop_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
REG_FIELD_SET(SW_RX_FE_PGFLOOPEN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_fe_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_RX_FE_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_fe_gpga_offset(uint32_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_PGAOFFSET, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_fe_gpga(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_GPGA, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_bq_qvalue(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_BQ_QVALUE, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_fe_gbq(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_GBQ, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_fe_gpgf_offset(uint32_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_PGFOFFSET, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_fe_gpgf(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_GPGF, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_fe_hpfenord2_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_HPFENORD2, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_fe_byphpf_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_FE_BYPHPF, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_fe_pwdpgf_offset_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
REG_FIELD_SET(SW_RX_FE_PWDPGFOFFSET, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_fe_pwdpga_offset_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
REG_FIELD_SET(SW_RX_FE_PWDPGAOFFSET, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_glna(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_GAIN_ADDR);
REG_FIELD_SET(SW_RX_GLNA, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_GAIN_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_pga_gain_set(uint32_t val)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR);
REG_FIELD_SET(SW_TX_GPGA, tmp, val);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TX_GAIN_ADDR, tmp);
#else
(void)val;
#endif
}
uint32_t phy_ana_pga_gain_get(void)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
return (uint32_t)REG_FIELD_GET(SW_TX_GPGA,
PHY_ANA_READ_REG(CFG_BB_ANA_TX_GAIN_ADDR));
#else
return 3;
#endif
}
void phy_ana_tx_en(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_TX_EN, tmp, en);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_en(bool_t en)
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_RX_FE_EN, tmp, en);
REG_FIELD_SET(SW_ADC_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_enlic_en(uint8_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp =0 ;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ENLIC_RX, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ENLIC_TX, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_dbg_print()
{
#if HW_PLATFORM == HW_PLATFORM_SILICON
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TX_CFG_0_ADDR);
iot_printf("Analog rx0:0x%x, ", tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
iot_printf("tx6:0x%x, ", tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
iot_printf("top10:0x%x\n", tmp);
#endif
}
void phy_ana_top_tx_en(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_TX_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_top_rx_en(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_RX_FE_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_top_adc_en(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_top_dac_en(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_TX_DAC_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_top_enlic_rx_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ENLIC_RX, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_top_enlic_tx_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ENLIC_TX, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_top_reset_n_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_RESET_N, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_rx_fe_selc_hpf(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
REG_FIELD_SET(SW_RX_FE_SELC_HPF, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_rx_fe_selc_pgf_bq(uint8_t data)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RX_CFG_0_ADDR);
REG_FIELD_SET(SW_RX_FE_SELC_PGF_BQ, tmp, data);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RX_CFG_0_ADDR, tmp);
#else
(void)data;
#endif
}
void phy_ana_adc_set(bool_t en)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR);
REG_FIELD_SET(SW_ADC_EN, tmp, en);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_ADDR, tmp);
#else
(void)en;
#endif
}
void phy_ana_bias_ic0_cfg(uint32_t value)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC0_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT0, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC0_ADDR, tmp);
#else
(void)value;
#endif
}
void phy_ana_bias_ic1_cfg(uint32_t value)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IC1_ADDR);
REG_FIELD_SET(SW_BG_IC25U_ADJ_BIT1, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IC1_ADDR, tmp);
#else
(void)value;
#endif
}
void phy_ana_bias_ir0_cfg(uint32_t value)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR0_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT0, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR0_ADDR, tmp);
#else
(void)value;
#endif
}
void phy_ana_bias_ir1_cfg(uint32_t value)
{
#if HW_PLATFORM > HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_BIAS_IR1_ADDR);
REG_FIELD_SET(SW_BG_IR25U_ADJ_BIT1, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_BIAS_IR1_ADDR, tmp);
#else
(void)value;
#endif
}
void phy_ana_hw_en_bitmap(uint32_t value)
{
uint32_t tmp;
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TOP_HWEN_ADDR);
REG_FIELD_SET(SW_TOP_HW_EN, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TOP_HWEN_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_RXGAIN_HWEN_ADDR);
REG_FIELD_SET(SW_RXGAIN_HW_EN, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_RXGAIN_HWEN_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_TXGAIN_HWEN_ADDR);
REG_FIELD_SET(SW_TXGAIN_HW_EN, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_TXGAIN_HWEN_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_EXT0_HWEN_ADDR);
REG_FIELD_SET(SW_EXT0_HW_EN, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_EXT0_HWEN_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_EXT1_HWEN_ADDR);
REG_FIELD_SET(SW_EXT1_HW_EN, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_EXT1_HWEN_ADDR, tmp);
tmp = PHY_ANA_READ_REG(CFG_BB_ANA_EXT2_HWEN_ADDR);
REG_FIELD_SET(SW_EXT2_HW_EN, tmp, value);
PHY_ANA_WRITE_REG(CFG_BB_ANA_EXT2_HWEN_ADDR, tmp);
}
void phy_ana_filter_set(uint8_t val)
{
/* TODO: update as soon as possible */
}
/* get the gain table */
void phy_pgf_bq_pga_gain_get(uint16_t gain_idx, \
volatile uint8_t *pgf, \
volatile uint8_t *bq, \
volatile uint8_t *pga, \
volatile uint8_t *lna, \
volatile uint8_t *byphpf, \
volatile uint8_t *enord2, \
volatile uint8_t *bq_qvalue)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
IOT_ASSERT(gain_idx < 170);
tmp = all_mask_gain_table[gain_idx];
*pgf = REG_FIELD_GET(SW_RX_FE_GPGF, tmp);
*bq = REG_FIELD_GET(SW_RX_FE_GBQ, tmp );
*pga = REG_FIELD_GET(SW_RX_FE_GPGA, tmp);
*lna = REG_FIELD_GET(SW_RX_GLNA , tmp);
*byphpf = REG_FIELD_GET(SW_RX_FE_BYPHPF, tmp);
*enord2 = REG_FIELD_GET(SW_RX_FE_HPFENORD2, tmp);
*bq_qvalue = REG_FIELD_GET(SW_RX_BQ_QVALUE, tmp);
#else
(void)gain_idx;
(void)pgf;
(void)bq;
(void)pga;
(void)lna;
(void)byphpf;
(void)enord2;
(void)bq_qvalue;
#endif
}
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