279 lines
		
	
	
		
			9.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			279 lines
		
	
	
		
			9.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /****************************************************************************
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| 
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| Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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| 
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| This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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| be copied by any method or incorporated into another program without
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| the express written consent of Aerospace C.Power. This Information or any portion
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| thereof remains the property of Aerospace C.Power. The Information contained herein
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| is believed to be accurate and Aerospace C.Power assumes no responsibility or
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| liability for its use in any way and conveys no license or title under
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| any patent or copyright and makes no representation or warranty that this
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| Information is free from patent or copyright infringement.
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| 
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| ****************************************************************************/
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| #ifndef IOT_SYSTEM_H
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| #define IOT_SYSTEM_H
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| 
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| #include "iot_system_api.h"
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| 
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| #ifdef __cplusplus
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| extern "C" {
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| #endif
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| 
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| /*************************** chip id type *************************************/
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| #define IOT_CHIP_ID_UNKNOWN 0
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| #define IOT_CHIP_ID_HT_WQ   1
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| #define IOT_CHIP_ID_MT      2
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| #define IOT_CHIP_ID_FLX     3
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| #define IOT_CHIP_ID_QJ      4
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| #define IOT_CHIP_ID_SPE     5
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| #define IOT_CHIP_ID_GX      6
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| #define IOT_CHIP_ID_DT      7
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| #define IOT_CHIP_ID_YP      8
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| #define IOT_CHIP_ID_WTZ     9
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| #define IOT_CHIP_ID_TCE     10
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| 
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| /*************************** kunlun1 chip id **********************************/
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| /* HZ k48 */
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| #define CHIP_ID_HZ_K48V1A     0x0003 //HZ3011
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| #define CHIP_ID_HZ_K48V2A     0x0103 //HZ3011
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| #define CHIP_ID_HZ_K48V3A     0x0203 //HZ3011
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| /* HZ k68 */
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| #define CHIP_ID_HZ_K68V1A     0x0001 //HZ3001
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| #define CHIP_ID_HZ_K68V2A     0x0101 //HZ3001
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| #define CHIP_ID_HZ_K68V3A     0x0201 //HZ3001
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| /* WQ k48 */
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| #define CHIP_ID_WQ_K48V3A     0x0213 //WQ3011
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| #define CHIP_ID_WQ_K48V3A2    0x0223 //WQ3012
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| #define CHIP_ID_WQ_K48V3A3    0x0233 //WQ3013
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| #define CHIP_ID_WQ_K48V2A     0x0113 //WQ3011
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| #define CHIP_ID_WQ_K48V2A2    0x0123 //WQ3012
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| /* WQ k68 */
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| #define CHIP_ID_WQ_K68V3A     0x0211 //WQ3001
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| #define CHIP_ID_WQ_K68V3A2    0x0221 //WQ3001
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| /* MT k68 */
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| #define CHIP_ID_MT_K68V1B     0x0009 //MT8201
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| #define CHIP_ID_MT_K68V1BB    0x0005 //MT8201
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| #define CHIP_ID_MT_K68V2B     0x0109 //MT8201
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| #define CHIP_ID_MT_K68V2BB    0x0105 //MT8201
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| #define CHIP_ID_MT_K68V3B     0x0209 //MT8201
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| #define CHIP_ID_MT_K68V3BB    0x0205 //MT8201
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| #define CHIP_ID_MT_K68V3A     0x020d //MT8201
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| /*
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|  * FLX6610/FLX6611 regarded as HTZD chip from now on.
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|  */
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| #define CHIP_ID_FLX_K68       0x0301 //FLX6610
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| #define CHIP_ID_FLX_K48       0x0303 //FLX6611
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| 
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| /*************************** kunlun2 chip id **********************************/
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| // AI package
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| #define CHIP_ID_WQ5007_REVA   0x0011 //Kunlun2's K3D revA
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| #define CHIP_ID_WQ5007_REVB   0x0012 //Kunlun2 K3D revB
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| #define CHIP_ID_WQ5106_REVB   0x0052 //Kunlun2 AUDIO revB
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| #define CHIP_ID_TQAI01_REVB   0x0092 //Kunlun2 TQAI01 revB
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| #define CHIP_ID_ASK1001_REVB  0x00d2 //Kunlun2 ask1001 revB
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| // plc package
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| #define CHIP_ID_WQ3021_REVA   0x0811 //Kunlun2's PLC revA
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| #define CHIP_ID_WQ3021_REVB   0x0812 //Kunlun2's PLC revB
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| #define CHIP_ID_WQ3021_REVC   0x0912 //Kunlun2's PLC revC
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| #define CHIP_ID_WQ3021_REVD   0x0892 //Kunlun2's PLC revD
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| 
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| /*************************** kunlun3 chip id **********************************/
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| /*  | chid_id[15:12]    | chip_id[11:8] | chip_id[7:4]  | chip_id[3:0]  |
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|  *  | project[3:0]      | wafer[3:0]    | mark[3:0]     | sip[3:0]      |
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|  * sip[3:3]->rf-in, sip[2:2]->pa-in, sip[1:1]->psram-in, sip[0:0]->flash-in
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|  */
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| /* WQ3031_V1A, k48, QFN6*6, internal pa */
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| #define CHIP_ID_WQ3031_V1A    0x1005    //WQ3031
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| /* HZ3201_V1A, k76, QFN9*9, internal psram */
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| #define CHIP_ID_HZ3201_V1A    0x1003    //HZ3201
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| /* HZ3211_V1A, k76, QFN9*9 */
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| #define CHIP_ID_HZ3211_V1A    0x1001    //HZ3211
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| /* HZ3201, RF, k76, QFN9*9 */
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| #define CHIP_ID_HZ3201_RF_V1A 0x100B    //HZ3201RF
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| /* HZ3211, RF, k76, QFN9*9 */
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| #define CHIP_ID_HZ3211_RF_V1A 0x100D    //HZ3211RF
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| /* QJ5580D_V1A, k76, QFN9*9 */
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| #define CHIP_ID_QJ5580D_V1A   0x1013    //QJ5580D
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| /* QJ5582D_V1A, k76, QFN9*9 */
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| #define CHIP_ID_QJ5582D_V1A   0x1011    //QJ5582D
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| /* FLX6711, k76, QFN9*9 */
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| #define CHIP_ID_FLX6711_V1A   0x1021    //FLX6711
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| /* FLX6710, k76, QFN9*9 */
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| #define CHIP_ID_FLX6710_V1A   0x1023    //FLX6710
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| /* SPE7303, k76, QFN9*9 */
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| #define CHIP_ID_SPE7303_V1A   0x1033    //SPE7303
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| /* SPE7301, k76, QFN9*9 */
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| #define CHIP_ID_SPE7301_V1A   0x1031    //SPE7301
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| /* GX2001, k76, QFN9*9 */
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| #define CHIP_ID_GX2001_V1A    0x1043    //GX2001
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| /* GX2011, k76, QFN9*9 */
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| #define CHIP_ID_GX2011_V1A    0x1041    //GX2011
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| /* HZ5202, k76, QFN9*9 */
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| #define CHIP_ID_HZ5202_V1A    0x1057    //HZ5202
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| /* DT0530, k76, QFN9*9 */
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| #define CHIP_ID_DT0530_V1A    0x1063    //DT0530
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| /* DT0531, k76, QFN9*9 */
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| #define CHIP_ID_DT0531_V1A    0x1061    //DT0531
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| /* YP8801, k76, QFN9*9 */
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| #define CHIP_ID_YP8801_V1A    0x1073    //YP8801
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| /* YP8811, k76, QFN9*9 */
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| #define CHIP_ID_YP8811_V1A    0x1071    //YP8811
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| /* WTZ31C, k76, QFN9*9 */
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| #define CHIP_ID_WTZ31C_V1A    0x1083    //WTZ31C
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| /* WTZ31S, k76, QFN9*9 */
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| #define CHIP_ID_WTZ31S_V1A    0x1081    //WTZ31S
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| /* TCE3202, k76, QFN9*9 */
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| #define CHIP_ID_TCE3202_V1A   0x1093    //TCE3202
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| /* TCE3201, k76, QFN9*9 */
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| #define CHIP_ID_TCE3201_V1A   0x1091    //TCE3201
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| 
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| /* control transfer instuction */
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| #define RISCV32_INST_SET_JAL        0x6f
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| #define RISCV32_INST_SET_JALR       0x67
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| #define RISCV32_INST_SET_LUI        0x37
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| #define RISCV32_INST_SET_AUIPC      0x17
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| #define RISCV32_INST_SET_C_JR       0x4
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| #define RISCV32_INST_SET_C_JR_OP    0x2
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| #define RISCV32_INST_SET_C_JALR     0x4
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| #define RISCV32_INST_SET_C_JALR_OP  0x2
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| 
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| /* firmware run mode */
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| #define MM_MODE                 0
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| #define FTM_MODE                1
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| #define MP_MODE                 2
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| 
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| /* cpu status flag */
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| #define CPU_FLAG_RUNNING        1
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| #define CPU_FLAG_INVALID        2
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| 
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| /* chip reset reason */
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| #define PWR_RESET_FLAG        0x0
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| #define SOFT_RESET_FLAG       0xA5
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| #define WDT_RESET_FLAG        0x5A
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| /* watchdog flag: msb=1;  power on flag: msb=0; */
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| #define RST_REASON_WDG_FLAG         (0x80000000)
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| #define RST_REASON_SOFT_TYPE_GET(r) ((uint8_t)((r) & 0xFF))
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| #define RST_REASON_IS_WDG_TYPE(r)   \
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|     ((((r) & RST_REASON_WDG_FLAG) == RST_REASON_WDG_FLAG) ? 1 : 0)
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| 
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| // global address mapping
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| extern uint32_t _start;         // start address
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| extern uint32_t _etext;         // text end address
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| extern uint32_t _data;          // data start address
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| extern uint32_t _sp;            // data end address
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| extern uint32_t _iram_start;    // iram start address
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| extern uint32_t _iram_end;      // iram end address
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| extern uint32_t _flash_end;     // flash end address
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| 
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| // trap saved registers
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| typedef struct {
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|     uint32_t ra;
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|     uint32_t sp;
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|     uint32_t gp;
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|     uint32_t tp;
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|     uint32_t t0_2[3];
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|     uint32_t t6;
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|     uint32_t s1;
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|     uint32_t a0_7[8];
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|     uint32_t s2_11[10];
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|     uint32_t t3_4[2];
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|     uint32_t t5;
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|     uint32_t fp;
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| } saved_registers;
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| 
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| typedef struct {
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|     unsigned char  file[32];
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|     uint32_t line;
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| }assert_failed_info;
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| 
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| typedef struct {
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|     uint32_t count;
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|     uint32_t crash:1,
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|         assert_failed:1,
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|         flags:6,
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|         resv:24;
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|     uint32_t mepc;
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|     uint32_t mcause;
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|     saved_registers *trap_frame;
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|     assert_failed_info assert_info;
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| }cpu_state;
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| 
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| typedef struct _exception_cb {
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|     void (* handler)(uintptr_t mcause, uintptr_t epc, saved_registers *reg);
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|     int32_t (* full_dump)();
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| } exception_cb_t;
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| 
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| extern cpu_state g_cpu1_state;
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| 
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| void iot_iram_cache_legal_check();
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| 
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| uint32_t iot_chip_id_check();
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| 
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| uint8_t iot_sys_reset_ctrl();
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| 
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| uint32_t iot_cpu1_count_get();
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| uint32_t iot_cpu1_crash_get();
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| void iot_cpu1_crash_dump();
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| 
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| /**
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|  * @brief   iot_chip_get_xor_value() - get chip xor value.
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|  * @return  xor value, see - IOT_XOR_VALUE_XXX.
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|  */
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| uint8_t iot_chip_get_xor_value();
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| 
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| /**
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|  * @brief iot_chip_get_mac_addr - get mac address in chip.
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|  * @param mac: pointer of mac address buffer.
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|  * @return 0: succeed, 0xffffffff: failed.
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|  */
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| uint32_t iot_chip_get_mac_addr(uint8_t *mac);
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| 
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| /**
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|  * @brief iot_chip_get_chip_info: get internal chip id information.
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|  * @return chip id;
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|  */
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| uint32_t iot_chip_get_chip_info();
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| 
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| /**
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|  * @brief iot_chip_get_chip_subid_info: get internal chip sub id information.
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|  * @return chip sub id, 0 : invalid;
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|  */
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| uint32_t iot_chip_get_chip_subid_info();
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| 
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| /**
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|  * @brief iot_chip_efuse_check: get internal chip efuse check information.
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|  * @return chip efuse check result.
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|  *  0x00: check succeed; other: the corresponding item fails to be verified.
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|  *      bit 0: chip id check result;
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|  *      bit 1: mac address check result;
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|  *      bit 2: ate calibration check result;
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|  *      bit 3: sadc meter check result.
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|  */
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| uint8_t iot_chip_efuse_check();
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| 
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| /**
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|  * @brief iot_chip_check_lic: check license status.
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|  * @return 1->internal pa, 0->external pa.
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|  */
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| uint8_t iot_chip_check_lic();
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| 
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| /**
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|  * @brief iot_system_get_fw_boot_param - get firmware boot parameter.
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|  * @param param: pointer of parameter that sbl load firmware.
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|  * @return none.
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|  */
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| void iot_system_get_fw_boot_param(void *param);
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| 
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| /**
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|  * @brief iot_system_get_rst_flag_reg - get rest flag in register set by hardware.
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|  * @return reset flag.
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|  */
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| uint32_t iot_system_get_rst_flag_reg();
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| #ifdef __cplusplus
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| }
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| #endif
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| 
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| #endif //IOT_SYSTEM_H
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