452 lines
13 KiB
C
Executable File
452 lines
13 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "iot_config.h"
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#include "os_types.h"
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#include "hw_reg_api.h"
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#include "iot_mem.h"
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#include "iot_io_api.h"
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/* plc public api includes */
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#include "plc_fr.h"
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#include "plc_const.h"
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#include "iot_bitops.h"
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/* driver includes */
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#include "iot_system.h"
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#include "iot_irq.h"
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#include "iot_gpio_api.h"
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#include "iot_board_api.h"
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#include "iot_errno_api.h"
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#include "pin_rf.h"
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#include "mpdu_header.h"
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#include "mac_sys_reg.h"
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#include "plc_protocol.h"
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#include "mac_raw_reg.h"
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#include "mac_rawdata_hw.h"
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#include "phy_reg.h"
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#include "phy_bb.h"
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#include "phy_phase.h"
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#include "phy_isr.h"
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#include "phy_txrx_pwr.h"
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#include "ahb.h"
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#include "os_timer_api.h"
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#include "phy_overstress.h"
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#include "hw_phy_api.h"
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iot_plc_over_stress_cb_t mac_ovr_stress_isr_cb = NULL;
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/* MAC callback func register */
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void register_over_stress_cb(iot_plc_over_stress_cb_t cb)
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{
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mac_ovr_stress_isr_cb = cb;
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}
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bool_t phy_overstress_is_on(void)
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{
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bool_t overstress_is_on = false;
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint8_t over_stress_gpio = 0;
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uint32_t irq_type_reg = 0;
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uint32_t reg_int = 0;
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/* lic with geode in and other geode out */
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if(iot_chip_check_lic()) {/* internal PA */
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/* clr intr*/
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reg_int = PHY_READ_REG(CFG_BB_INT_CLR_1_ADDR);
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reg_int |=PHY_LIC_OVR_STRESS;
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PHY_WRITE_REG(CFG_BB_INT_CLR_1_ADDR, reg_int);
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/* check intr src */
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irq_type_reg = PHY_READ_REG(CFG_BB_INT_RAW_1_ADDR);
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if(irq_type_reg & PHY_LIC_OVR_STRESS){
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return true;
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} else {
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return false;
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}
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} else {/* external PA */
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over_stress_gpio = iot_board_get_gpio(GPIO_GEODE_OVT);
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if(iot_gpio_value_get(over_stress_gpio)) {
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return false;
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} else {
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return true;
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}
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}
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#endif
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return overstress_is_on;
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}
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/* TODO: use macro distinguish WARID, as WAR_BUGID_244 in iot_config.h */
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uint32_t IRAM_ATTR phy_get_hw_interrupt_type(void)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t irq_type_reg = 0;
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uint32_t irq_type = 0;
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/* get int 1 mask */
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irq_type_reg = PHY_READ_REG(CFG_BB_INT_MASK_1_ADDR);
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if(irq_type_reg & PHY_LIC_OVR_STRESS){
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irq_type |= INTR_TYPE_PHY_LIC_OVR_STRESS;
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}
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/* get int 2 mask */
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irq_type_reg = PHY_READ_REG(CFG_BB_INT_MASK_2_ADDR);
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if (irq_type_reg & PHY_RECV_FD_FC_OK) {
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irq_type |= INTR_TYPE_PHY_FD_FC_OK;
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}
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irq_type_reg = PHY_READ_REG(CFG_BB_INT_MASK_2_ADDR);
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if (irq_type_reg & PHY_FD_TX_ABORT) {
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irq_type |= INTR_TYPE_PHY_FD_TX_ABORT;
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}
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#if MAC_TIMESTAMPING
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if (irq_type_reg & PHY_RECV_FD_PLD_OK) {
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irq_type |= INTR_TYPE_PHY_FD_PLD_OK;
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}
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if (irq_type_reg & PHY_RECV_FD_PLD_FAIL) {
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irq_type |= INTR_TYPE_PHY_FD_PLD_FAIL;
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}
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#endif
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#if (ENA_HW_SYNC_PPM_WAR)
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if (irq_type_reg & PHY_TX_FD_INSERT_PREAM_DONE) {
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irq_type |= INTR_TYPE_PHY_INSERT_PREAM_DONE;
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}
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#endif
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return irq_type;
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#else
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return 0;
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#endif
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}
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void IRAM_ATTR phy_disable_hw_interrupt(uint32_t irq_type)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t reg_int = 0;
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/* disable int 1 */
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if (irq_type & INTR_TYPE_PHY_LIC_OVR_STRESS) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_1_ADDR);
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reg_int &= (~PHY_LIC_OVR_STRESS);
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PHY_WRITE_REG(CFG_BB_INT_EN_1_ADDR, reg_int);
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}
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if (irq_type & INTR_TYPE_PHY_FD_FC_OK) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int &= (~PHY_RECV_FD_FC_OK);
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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if (irq_type & INTR_TYPE_PHY_FD_TX_ABORT) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int &= (~PHY_FD_TX_ABORT);
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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/* disable int 2 */
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#if MAC_TIMESTAMPING
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if (irq_type & (INTR_TYPE_PHY_FD_PLD_OK | INTR_TYPE_PHY_FD_PLD_FAIL)) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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if (irq_type & INTR_TYPE_PHY_FD_PLD_OK) {
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reg_int &= (~PHY_RECV_FD_PLD_OK);
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}
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if (irq_type & INTR_TYPE_PHY_FD_PLD_FAIL) {
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reg_int &= (~PHY_RECV_FD_PLD_FAIL);
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}
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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#endif
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#if (ENA_HW_SYNC_PPM_WAR)
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if (irq_type & INTR_TYPE_PHY_INSERT_PREAM_DONE) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int &= (~PHY_TX_FD_INSERT_PREAM_DONE);
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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#endif
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#else
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(void)irq_type;
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#endif
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return;
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}
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void IRAM_ATTR phy_clear_hw_interrupt(uint32_t irq_type)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t reg_int = 0;
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/* clear int 1 */
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if (irq_type & INTR_TYPE_PHY_LIC_OVR_STRESS) {
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reg_int = PHY_READ_REG(CFG_BB_INT_CLR_1_ADDR);
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reg_int |=PHY_LIC_OVR_STRESS;
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PHY_WRITE_REG(CFG_BB_INT_CLR_1_ADDR, reg_int);
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}
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if (irq_type & INTR_TYPE_PHY_FD_FC_OK) {
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reg_int = PHY_READ_REG(CFG_BB_INT_CLR_2_ADDR);
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reg_int |=PHY_RECV_FD_FC_OK;
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PHY_WRITE_REG(CFG_BB_INT_CLR_2_ADDR, reg_int);
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}
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if (irq_type & INTR_TYPE_PHY_FD_TX_ABORT) {
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reg_int = PHY_READ_REG(CFG_BB_INT_CLR_2_ADDR);
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reg_int |=PHY_FD_TX_ABORT;
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PHY_WRITE_REG(CFG_BB_INT_CLR_2_ADDR, reg_int);
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}
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/* clear int 2 */
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#if MAC_TIMESTAMPING
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if (irq_type & (INTR_TYPE_PHY_FD_PLD_OK | INTR_TYPE_PHY_FD_PLD_FAIL)) {
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reg_int = PHY_READ_REG(CFG_BB_INT_CLR_2_ADDR);
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if (irq_type & INTR_TYPE_PHY_FD_PLD_OK) {
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reg_int |=PHY_RECV_FD_PLD_OK;
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}
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if (irq_type & INTR_TYPE_PHY_FD_PLD_FAIL) {
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reg_int |= PHY_RECV_FD_PLD_FAIL;
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}
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PHY_WRITE_REG(CFG_BB_INT_CLR_2_ADDR, reg_int);
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}
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#endif
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#if (ENA_HW_SYNC_PPM_WAR)
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if (irq_type & INTR_TYPE_PHY_INSERT_PREAM_DONE) {
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reg_int = PHY_READ_REG(CFG_BB_INT_CLR_2_ADDR);
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reg_int |=PHY_TX_FD_INSERT_PREAM_DONE;
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PHY_WRITE_REG(CFG_BB_INT_CLR_2_ADDR, reg_int);
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}
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#endif
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#else
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(void)irq_type;
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#endif
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}
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void IRAM_ATTR phy_enable_hw_interrupt(uint32_t irq_type)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t reg_int = 0;
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/* enable int 1 */
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if (irq_type & INTR_TYPE_PHY_LIC_OVR_STRESS) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_1_ADDR);
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reg_int |=PHY_LIC_OVR_STRESS;
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PHY_WRITE_REG(CFG_BB_INT_EN_1_ADDR, reg_int);
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}
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if (irq_type & INTR_TYPE_PHY_FD_FC_OK) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int |=PHY_RECV_FD_FC_OK;
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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if (irq_type & INTR_TYPE_PHY_FD_TX_ABORT) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int |=PHY_FD_TX_ABORT;
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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/* enable int 2 */
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#if MAC_TIMESTAMPING
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if (irq_type & (INTR_TYPE_PHY_FD_PLD_OK | INTR_TYPE_PHY_FD_PLD_FAIL)) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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if (irq_type & INTR_TYPE_PHY_FD_PLD_OK) {
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reg_int |=PHY_RECV_FD_PLD_OK;
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}
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if (irq_type & INTR_TYPE_PHY_FD_PLD_FAIL) {
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reg_int |= PHY_RECV_FD_PLD_FAIL;
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}
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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#endif
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#if (ENA_HW_SYNC_PPM_WAR)
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if (irq_type & INTR_TYPE_PHY_INSERT_PREAM_DONE) {
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int |= PHY_TX_FD_INSERT_PREAM_DONE;
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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}
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#endif
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#else
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(void)irq_type;
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#endif
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return;
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}
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uint32_t IRAM_ATTR phy_interrupt_handler(uint32_t vector, iot_addrword_t data)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t isr_flag = 0;
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isr_flag = phy_get_hw_interrupt_type();
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/* clear cpu0 int */
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phy_clear_hw_interrupt(isr_flag);
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/* disable interrupt mask */
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phy_disable_hw_interrupt(isr_flag);
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#if MAC_TIMESTAMPING
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/* PLD ok or fail interrupt */
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if(isr_flag & INTR_TYPE_PHY_FD_PLD_OK \
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|| isr_flag & INTR_TYPE_PHY_FD_PLD_FAIL) {
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g_phy_cpu_share_ctxt.phy_pld_int_ntb = \
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RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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}
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#endif
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if (isr_flag & INTR_TYPE_PHY_FD_FC_OK) {
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g_phy_ctxt.dep.reg_phase = phy_get_mac_rx_phase();
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}
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#if DEG_TX_ABORT
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if (isr_flag & INTR_TYPE_PHY_FD_TX_ABORT) {
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phy_dbg_get_tx_abort_lock_value();
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}
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#endif
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/* turn down gain */
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if (isr_flag & INTR_TYPE_PHY_LIC_OVR_STRESS) {
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/* update cnt */
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phy_add_overstress_cnt();
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/* turn down power */
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if (!g_phy_ctxt.indep.ovs_ctxt.ovr_stress) {
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/* update global flag */
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g_phy_ctxt.indep.ovs_ctxt.ovr_stress = 1;
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}
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/* mac callback */
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if (mac_ovr_stress_isr_cb != NULL) {
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mac_ovr_stress_isr_cb(NULL, 1);
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}
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}
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if (isr_flag & INTR_TYPE_PHY_LIC_OVR_STRESS){
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/* disable over stress interrupt */
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isr_flag &= ~INTR_TYPE_PHY_LIC_OVR_STRESS;
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phy_enable_hw_interrupt(isr_flag);
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}
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else{
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phy_enable_hw_interrupt(isr_flag);
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}
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#if (ENA_HW_SYNC_PPM_WAR)
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/* kl2 tx ppm war */
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if (isr_flag & INTR_TYPE_PHY_INSERT_PREAM_DONE) {
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uint32_t proto = PHY_PROTO_TYPE_GET();
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rx_fc_msg_t msg;
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uint32_t bb_fc[4] = {0};
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bb_fc[0] = RGF_RAW_READ_REG(CFG_TX_FC_DATA0_ADDR);
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bb_fc[1] = RGF_RAW_READ_REG(CFG_TX_FC_DATA1_ADDR);
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bb_fc[2] = RGF_RAW_READ_REG(CFG_TX_FC_DATA2_ADDR);
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bb_fc[3] = RGF_RAW_READ_REG(CFG_TX_FC_DATA3_ADDR);
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phy_ppm_status_ctxt_t *ppm_ctxt = phy_multi_sync_get_ppm_status();
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mac_get_rx_frm_msg_from_fc(proto, bb_fc, &msg);
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phy_multi_sync_apply_bb_ppm(ppm_ctxt, msg.nid, BB_PPM_TX_ONLY);
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}
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#endif
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#else
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(void)vector;
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(void)data;
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#endif
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return ERR_OK;
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}
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static void phy_isr_clean(void)
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{
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/* disable all interrupt and clean up any pending interrupt */
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PHY_WRITE_REG(CFG_BB_INT_EN_0_ADDR, 0);
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PHY_WRITE_REG(CFG_BB_INT_EN_1_ADDR, 0);
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, 0);
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//INT_EN_3 map to cpu1
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/* clean up all pending interrupt */
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PHY_WRITE_REG(CFG_BB_INT_CLR_0_ADDR, BB_INT_CLR_0_MASK);
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PHY_WRITE_REG(CFG_BB_INT_CLR_1_ADDR, BB_INT_CLR_1_MASK);
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PHY_WRITE_REG(CFG_BB_INT_CLR_2_ADDR, BB_INT_CLR_2_MASK);
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}
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void phy_isr_clean_cpu1(void)
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{
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/* disable all interrupt and clean up any pending interrupt */
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PHY_WRITE_REG(CFG_BB_INT_EN_3_ADDR, 0);
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/* clean up all pending interrupt */
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PHY_WRITE_REG(CFG_BB_INT_CLR_3_ADDR, BB_INT_CLR_3_MASK);
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}
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void phy_isr_init()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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iot_irq_t phy_fd_fc_err_irqhdl;
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iot_irq_t phy_lic_ovr_stress_irqhdl;
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/* reset phy interrupt reg */
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phy_isr_clean();
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/* kl2 just have internal PA */
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phy_lic_ovr_stress_irqhdl = \
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iot_interrupt_create(IRQ_NUM_PHY_LIC_OVR_STRESS, HAL_INTR_PRI_0,
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0, phy_interrupt_handler);
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iot_interrupt_attach(phy_lic_ovr_stress_irqhdl);
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iot_interrupt_unmask(phy_lic_ovr_stress_irqhdl);
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phy_fd_fc_err_irqhdl = \
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iot_interrupt_create(HAL_VECTOR_PHY_2, HAL_INTR_PRI_6,
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0, phy_interrupt_handler);
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iot_interrupt_attach(phy_fd_fc_err_irqhdl);
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iot_interrupt_unmask(phy_fd_fc_err_irqhdl);
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#endif
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return;
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}
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void phy_isr_start()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t reg_int;
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/* bind phy int 1 */
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/* internal PA */
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_1_ADDR);
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reg_int |= PHY_LIC_OVR_STRESS;
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PHY_WRITE_REG(CFG_BB_INT_EN_1_ADDR, reg_int);
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/* bind phy int 2 */
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reg_int = PHY_READ_REG(CFG_BB_INT_EN_2_ADDR);
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reg_int |= PHY_RECV_FD_FC_OK;
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reg_int |= PHY_FD_TX_ABORT;
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#if MAC_TIMESTAMPING
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reg_int |= PHY_RECV_FD_PLD_OK;
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reg_int |= PHY_RECV_FD_PLD_FAIL;
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#endif
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#if (ENA_HW_SYNC_PPM_WAR)
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reg_int |= PHY_TX_FD_INSERT_PREAM_DONE;
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#endif
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, reg_int);
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#endif
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return;
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}
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void phy_isr_start_cpu1(void)
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|
{
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/* currently we don't have cpu1 for kl3 */
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return;
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|
}
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