210 lines
6.2 KiB
C
Executable File
210 lines
6.2 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "chip_reg_base.h"
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#include "hw_reg_api.h"
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#include "iot_bitops.h"
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#include "os_lock.h"
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#include "iot_config.h"
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#include "sram.h"
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#include "os_mem.h"
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#include "smc.h"
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#if HW_PLATFORM > HW_PLATFORM_SIMU
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#include "dbg_io.h"
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#endif
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#include "iot_io.h"
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#include "ahb.h"
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#include "sec_glb.h"
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#define CLK 48 //16 //48
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#define PSRAM_ACCSEE_WAY 0 //0:cache 1:software
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extern void sfc_bus_share_en();
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void smc_rst() {
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/* warm reset sfc, set 1 and then clear */
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ahb_cache_disable();
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ahb_enable(AHB_EMC_HCLK_EB);
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ahb_reset(AHB_EMC_HCLK_EB);
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ahb_enable(AHB_EMC_EB);
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ahb_reset(AHB_EMC_EB);
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if(PSRAM_ACCSEE_WAY == 0){
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sram_qspi_enter();
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hal_smc_qspi_quad_cfg(CLK);
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ahb_cache_enable();
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//ahb_cache_reset();
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ahb_cachex_space_ena(0);
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ahb_cachex_space_ena(1);
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ahb_cachex_space_ena(2);
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ahb_cachex_space_ena(3);
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}
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}
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void smc_main() {
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uint32_t loop = 0x10000;
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uint8_t rdata[0x40] = {0};
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uint8_t wdata[0x40] = {1,2,3,4,5,6,7,8,9,0x11,0x22,0x33,0x44};
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int i = 0, j = 0, k = 0;
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int offset = 0;
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int len = sizeof(wdata);
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for(i = 0; i < len; i++) {
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wdata[i] = 0x5a;
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}
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dbg_uart_init();
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iot_printf("..........test..........\r\n");
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/* rst sfc */
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smc_rst();
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if(PSRAM_ACCSEE_WAY == 0)
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{
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int i,j;
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//int i;
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uint32_t wdat[50];
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uint32_t rdat[50];
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uint32_t rdat2[50];
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for (j=0;j<100;j++)
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{
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for (i=0;i<50;i++)
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{
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wdat[i]=0x12345678+i+j;
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*((volatile uint32_t*)(0x18000000+i*4)) = wdat[i];
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*((volatile uint32_t*)(0x28000000+i*4)) = wdat[i];
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}
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ahb_cachex_flush(1,0x18000000, 0x100);
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ahb_cachex_clear(0);
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ahb_cachex_flush(3,0x28000000, 0x100);
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ahb_cachex_clear(2);
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for (i=0;i<50;i++)
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{
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rdat[i]=((volatile uint32_t)*((volatile uint32_t*)(0x10000000+i*4)));
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rdat2[i]=((volatile uint32_t)*((volatile uint32_t*)(0x20000000+i*4)));
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if((wdat[i] != rdat[i]) || (wdat[i] != rdat2[i]))
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{
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iot_printf("ERROR addr 0x%x, WR:0x%x, RD 0x%X\r\n",(0x10000000+i*4), wdat[i],rdat[i]);
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iot_printf("ERROR addr 0x%x, WR:0x%x, RD 0x%X\r\n",(0x20000000+i*4), wdat[i],rdat2[i]);
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}
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}
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}
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iot_printf("finnished\n\r");
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}else{
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/* init sfc and sram */
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sfc_bus_share_en();
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sram_qspi_init();
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hal_smc_spi_cfg(CLK);
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do {
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if(sram_qspi_is_busy() != HAL_SRAM_OK){
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iot_printf("SRAM IS Busy Now!\r\n");
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}else{
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/* spi mode */
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sram_qspi_exit();
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iot_printf("spi write & read \n");
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wdata[10] = 0xaa;
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sram_qspi_write(wdata,0x1000,sizeof(wdata));
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while(sram_qspi_is_busy());
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os_mem_set(rdata,0,sizeof(rdata));
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sram_qspi_read(rdata,0x1000,sizeof(rdata));
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iot_printf("wdata[10]:%x, rdata[10]:%x\n", wdata[10], rdata[10]);
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if (wdata[10] != rdata[10]) {
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iot_printf("ERROR!! qspi write, qspi read not match\n");
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//return;
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}
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/* qpi mode */
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iot_printf("qpi write & read \n");
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sram_qspi_enter();
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hal_smc_qspi_quad_cfg(CLK);
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wdata[10] = 0xbb;
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sram_qspi_quad_write(wdata,0x2000,sizeof(wdata));
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while(sram_qspi_is_busy());
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os_mem_set(rdata,0,sizeof(rdata));
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sram_qspi_quad_read(rdata,0x2000,sizeof(rdata));
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iot_printf("wdata[10]:%x, rdata[10]:%x\n", wdata[10], rdata[10]);
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if (wdata[10] != rdata[10]) {
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iot_printf(" quad write, quad read not match\n");
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return;
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}
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/* write read test */
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iot_printf(" write read loop test \n");
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offset = 0;
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j = 0;
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for (j = 0; j < 10; j++) {
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iot_printf("\r\n------loop %d offset %x------\r\n", j, offset);
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for(i = 0; i < len; i++) {
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wdata[i] = 0x5a+1+j;
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}
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sram_qspi_quad_write(wdata, 0x1000+offset,sizeof(wdata));
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while(sram_qspi_is_busy());
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os_mem_set(rdata,0,sizeof(rdata));
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sram_qspi_quad_read(rdata, 0x1000 +offset, sizeof(rdata));
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for(i=0; i<len; i++) {
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/*
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iot_printf("addr: %08x %02x - %02x\r\n",
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i+0x13000000, wdata[i], rdata[i]);
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*/
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/*
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if(wdata[i] != rdata[i]) {
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iot_printf("not equal %d\r\n", i);
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return ;
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}
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*/
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if (i % 4 == 0 ) {
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iot_printf("\r\naddr: %08x: ", offset+i);
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}
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iot_printf("%02x ", rdata[i]);
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}
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k = 0;
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for(k=0;k<1000;k++);
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offset += 0x40;
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}
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sram_qspi_exit();
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return;
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}
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while(sram_qspi_is_busy());
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loop = 0x10000;
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while(loop--);
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} while (false);
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}
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return;
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}
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#ifdef __GNUC__
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int main(void) {
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smc_main();
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return 0;
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}
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#endif // __GCC__
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