889 lines
28 KiB
C
889 lines
28 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "chip_reg_base.h"
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#include "chip_irq_vector.h"
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#include "hw_reg_api.h"
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#include "mac_desc_engine.h"
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#include "mac_hwq_mgr.h"
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#include "mac_crc.h"
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#include "mac_reset.h"
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#include "mpdu_header.h"
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#include "mac_reset.h"
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#include "mac_cmn_hw.h"
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#include "mac_hwq_reg.h"
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#include "mac_sys_reg.h"
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#include "mac_rx_reg.h"
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#include "mac_tmr_reg.h"
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#include "mac_avln.h"
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#include "mac_key_hw.h"
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#include "mac_key.h"
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#include "phy_pm.h"
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#include "hw_tx.h"
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#include "tx_entry.h"
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#include "iot_io.h"
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#include "os_mem.h"
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#include "intc_reg.h"
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#include "phy_int.h"
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#include "mac_raw_reg.h"
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#include "phy_reg.h"
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#include "phy_status.h"
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#include "mac_int.h"
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#include "phy_rxtd_reg.h"
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#include "phy_dfe_reg.h"
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#include "granite_reg.h"
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#include "phy_ana_glb.h"
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#include "mac_hwq_reg.h"
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#include "phy_ana.h"
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#include "phy_txrx_pwr.h"
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#include "phy_tmap.h"
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#include "phy_ana_reg.h"
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#include "clk.h"
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#include "phy_agc.h"
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#include "gp_timer.h"
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#include "gpio_mtx.h"
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#include "iot_system.h"
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extern tonemap_table_entry gp_tonemap_table[];
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#define HW_TX_ALLOC_MEM_BYTE 0x1000
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static uint8_t HW_TX_ALLOC_POOL[HW_TX_ALLOC_MEM_BYTE] = {0};
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uint32_t mac_tx_mpdu_test(void *pdev, volatile tx_mpdu_start *mpdu) {
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(void)pdev;
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uint32_t tmp = 0;
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uint32_t band_id;
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uint32_t pb_size = 0;
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uint32_t tmi = 0, ext_tmi = 0;
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uint32_t pb_mod = 0, tx_pwr = 0;
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uint32_t rate_mode = glb_cfg.rate_mode;
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uint8_t fd_pwr_int = 0, fd_pwr_frac = 0, td_pwr = 0, ana_pwr = 0;
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#if (SUPPORT_SMART_GRID)
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#if SUPPORT_IEEE_1901
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volatile i1901_frame_control_t *i1901_fc =
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(i1901_frame_control_t*)(&(mpdu->fc0));
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uint32_t i1901_tmi = 0, i1901_tmi_ext = 0;
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#else
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volatile frame_control_t *sg_fc =
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(frame_control_t*)(&(mpdu->fc0));
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#endif
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#endif
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#if (SUPPORT_SOUTHERN_POWER_GRID)
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volatile spg_frame_control_t *spg_fc =
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(spg_frame_control_t*)(&(mpdu->fc0));
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#endif
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#if (SUPPORT_GREEN_PHY)
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volatile hpav_frame_control *hpav_fc =
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(hpav_frame_control*)(&(mpdu->fc0));
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#endif
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band_id = phy_band_id_get();
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/* TODO: use mac global API */
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mpdu->desc_type = DESC_TYPE_TX_MPDU_START;
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mpdu->proto_type = glb_cfg.m_type;
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mpdu->tx_port = HW_DESC_TX_PORT_PLC;
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mpdu->tx_phase = glb_cfg.phase;
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if (1 == g_phy_cpu_share_ctxt.pt_mode_entry) {
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tx_pwr = PHY_FULL_PWR_DBUV - PHY_MP_PWR_REDUCE;
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} else {
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tx_pwr = PHY_FULL_PWR_DBUV;
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}
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if (0) {
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// reg ctl tx power
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phy_set_tx_pwr_limit(tx_pwr);
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} else {
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// sack tx power ctl
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phy_tx_resp_pwr_ctl_en(true, true, true, true);
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phy_force_ana_td_power(false);
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// desc ctl tx power
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phy_tx_pwr_ctl_en(true, true, true);
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phy_tx_pwr_to_fd_td_ana_value(0, \
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band_id, \
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tx_pwr, \
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&fd_pwr_int, \
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&fd_pwr_frac, \
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&td_pwr, \
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&ana_pwr);
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mpdu->tx_power = fd_pwr_int;
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mpdu->tx_power_frac = fd_pwr_frac;
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mpdu->td_tx_power = td_pwr;
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mpdu->ana_tx_power = ana_pwr;
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phy_set_tx_resp_pwr(fd_pwr_int, fd_pwr_frac, td_pwr, ana_pwr);
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iot_printf("[ptr_dbg] set tx_pwr:%d, td_pwr:%d, ana_pwr:%d, "
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"fd_frac:%d, fd_int:%d\n", \
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tx_pwr, td_pwr, ana_pwr, fd_pwr_frac, fd_pwr_int);
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}
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if(glb_cfg.ack_en == true)
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mpdu->need_ack = 1;
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mpdu->ppdu_mode = glb_cfg.ppdu_mode;
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mpdu->next = 0;
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/* clear the mpdu_end */
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if (mpdu->tx_status) {
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phy_tx_done_clr(mpdu);
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//TODO:update
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mpdu->tx_status->tx_ok = 0;
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}
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/* tmi info */
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tmi = glb_cfg.tmi;
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if(glb_cfg.m_type == PLC_PROTO_TYPE_SG)
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{
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if (tmi >= 15) {
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/* if use ext_tmi */
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tmi = 15;
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ext_tmi = glb_cfg.tmi - 15;
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}
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} else if (glb_cfg.m_type == PLC_PROTO_TYPE_SPG) {
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IOT_ASSERT(tmi <= 10 || tmi >= 16 );
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if (tmi > 10) {
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/* if use ext_tmi */
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tmi = 13;
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ext_tmi = glb_cfg.tmi - 15;
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}
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}
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/* only contains the pb's size */
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phy_get_pb_size(glb_cfg.m_type, tmi, ext_tmi, &pb_size);
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mpdu->pb_num = glb_cfg.pb_num;
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mpdu->total_bytes = pb_size*glb_cfg.pb_num;
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/* start/end time, ignore in GP's case */
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//mpdu->start_time = 0;
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//mpdu->end_time = 0;
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/* TODO: amplitude table select */
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mpdu->tx_tone_amp = 0;
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/* band info */
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#if MAC_MULTI_BAND_SUPPORT == 1
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mpdu->sg_bandsel = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR)%3;
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#else
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mpdu->sg_bandsel = 0;
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#endif
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mpdu->sym_num_ppb = phy_get_sym_per_pb( \
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glb_cfg.m_type, mpdu->sg_bandsel, tmi, ext_tmi,
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phy_get_pss_id(glb_cfg.m_type, tmi, ext_tmi));
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if(mpdu->sym_num_ppb * glb_cfg.pb_num >= 512){
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iot_printf("[TMI-%d][PB-%d][error]:symbol size %d bigger than 512.", \
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ext_tmi+tmi,glb_cfg.pb_num,mpdu->sym_num_ppb * glb_cfg.pb_num);
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return ERR_INVAL;
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}
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#if (SUPPORT_GREEN_PHY)
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if (glb_cfg.m_type == PLC_PROTO_TYPE_GP) {
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if (glb_cfg.tmi >= 4) {
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mpdu->tx_fl = (uint32_t)(hpav_cal_fl_tmap( \
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glb_cfg.mpdu_cnt - 1, glb_cfg.pb_num, \
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glb_cfg.turbo_rate, glb_cfg.gi, \
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phy_symb_bits_get((uint32_t *)PHY_TMAP_TEST_ADDR)) * 1.28 - 20);
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} else {
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mpdu->tx_fl = (uint32_t)(hpav_cal_fl_robo( \
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glb_cfg.tmi, glb_cfg.mpdu_cnt, glb_cfg.pb_num) * 1.28 - 160);
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}
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} else {
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mpdu->tx_fl = (uint32_t)phy_get_fl_per_pb( \
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glb_cfg.m_type, mpdu->sg_bandsel, tmi, ext_tmi) * glb_cfg.pb_num;
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}
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#else
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mpdu->tx_fl = (uint32_t)phy_get_fl_per_pb( \
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glb_cfg.m_type, mpdu->sg_bandsel, tmi, ext_tmi) * glb_cfg.pb_num;
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#endif
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#if (SUPPORT_SMART_GRID)
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if(glb_cfg.m_type == PLC_PROTO_TYPE_SG)
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{
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if(glb_cfg.p_type == FC_DELIM_BEACON)
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{
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#if SUPPORT_IEEE_1901
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i1901_fc->delimiter_type = FC_DELIM_BEACON; /*beacon*/
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i1901_fc->vf.bcn.time_stamp = 0;
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i1901_fc->vf.bcn.stei = glb_cfg.src_tei;
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phy_tmi_sg_to_i1901(tmi, ext_tmi, &i1901_tmi, &i1901_tmi_ext);
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i1901_fc->vf.bcn.tmi = i1901_tmi;
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i1901_fc->vf.bcn.phase_num = 0;
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i1901_fc->vf.bcn.pss = phy_get_pss_id(PLC_PROTO_TYPE_SG,
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i1901_tmi, i1901_tmi_ext);
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i1901_fc->vf.bcn.version = 0;
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#else
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sg_fc->delimiter_type = FC_DELIM_BEACON; /*beacon*/
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sg_fc->vf.bcn.time_stamp = 0;
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sg_fc->vf.bcn.src_tei = glb_cfg.src_tei;
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sg_fc->vf.bcn.tmi = tmi;
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sg_fc->vf.bcn.sym_num = 0;
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sg_fc->vf.bcn.phase_num = 0;
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sg_fc->vf.bcn.version = 0;
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#endif
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}
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else if(glb_cfg.p_type == FC_DELIM_SOF)
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{
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#if SUPPORT_IEEE_1901
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i1901_fc->delimiter_type = FC_DELIM_SOF; /*sof*/
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i1901_fc->vf.sof.stei = glb_cfg.src_tei;
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i1901_fc->vf.sof.dtei = glb_cfg.dst_tei;
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i1901_fc->vf.sof.lid = 0;
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i1901_fc->vf.sof.pb_num = glb_cfg.pb_num;
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i1901_fc->vf.sof.frame_len = 0;
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i1901_fc->vf.sof.bcast = (0xFFF == i1901_fc->vf.sof.dtei) ? 1 : 0;
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i1901_fc->vf.sof.encry = 3;
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phy_tmi_sg_to_i1901(tmi, ext_tmi, &i1901_tmi, &i1901_tmi_ext);
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i1901_fc->vf.sof.tmi = i1901_tmi;
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i1901_fc->vf.sof.tmi_ext = i1901_tmi_ext;
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i1901_fc->vf.sof.pss = phy_get_pss_id(PLC_PROTO_TYPE_SG,
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i1901_tmi, i1901_tmi_ext);
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i1901_fc->vf.sof.version = 0;
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#else
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sg_fc->delimiter_type = FC_DELIM_SOF; /*sof*/
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sg_fc->vf.sof.src_tei = glb_cfg.src_tei;
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sg_fc->vf.sof.dst_tei = glb_cfg.dst_tei;
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sg_fc->vf.sof.lid = 0;
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sg_fc->vf.sof.frame_len = 0;
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sg_fc->vf.sof.pb_num = glb_cfg.pb_num;
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sg_fc->vf.sof.sym_num = 0;
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sg_fc->vf.sof.bcast = 0;
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sg_fc->vf.sof.tmi = tmi;
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sg_fc->vf.sof.tmi_ext = ext_tmi;
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sg_fc->vf.sof.version = 0;
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#endif
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}
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else if(glb_cfg.p_type == FC_DELIM_SOUND)
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{
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#if SUPPORT_IEEE_1901
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/* for ieee1901, RTS/CTS = SG SOUND */
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i1901_fc->delimiter_type = I1901_RTS_CTS;
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i1901_fc->vf.rts_cts.stei = glb_cfg.src_tei;
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i1901_fc->vf.rts_cts.dtei = glb_cfg.dst_tei;
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i1901_fc->vf.rts_cts.lid = 0;
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i1901_fc->vf.rts_cts.mnbf = 1; //TODO:
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i1901_fc->vf.rts_cts.rtsf = 1; //TODO:
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i1901_fc->vf.rts_cts.encry = 3;
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i1901_fc->vf.rts_cts.dur = 0xFFF; //TODO:
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i1901_fc->vf.rts_cts.version = 0;
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#else
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sg_fc->delimiter_type = FC_DELIM_SOUND; /*sound*/
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sg_fc->vf.sof.src_tei = glb_cfg.src_tei;
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sg_fc->vf.sof.dst_tei = glb_cfg.dst_tei;
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sg_fc->vf.sof.lid = 0;
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sg_fc->vf.sof.frame_len = 0;
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sg_fc->vf.sof.pb_num = glb_cfg.pb_num;
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sg_fc->vf.sof.sym_num = 0;
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sg_fc->vf.sof.bcast = 0;
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sg_fc->vf.sof.tmi = tmi;
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sg_fc->vf.sof.tmi_ext = ext_tmi;
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sg_fc->vf.sof.version = 0;
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#endif
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}
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#if SUPPORT_IEEE_1901
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i1901_fc->network_type = 0;
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i1901_fc->nid = glb_cfg.nid;
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#else
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sg_fc->network_type = 0;
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sg_fc->nid = glb_cfg.nid;
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IOT_ASSERT(sg_fc->vf.sof.pb_num <= 4);
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#endif
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} else
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#endif
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#if (SUPPORT_SOUTHERN_POWER_GRID)
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if (glb_cfg.m_type == PLC_PROTO_TYPE_SPG)
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{
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if(glb_cfg.p_type == FC_DELIM_BEACON)
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{
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spg_fc->delimiter_type = FC_DELIM_BEACON; /*beacon*/
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spg_fc->vf.bcn.time_stamp = 0;
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spg_fc->vf.bcn.src_tei = glb_cfg.src_tei;
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spg_fc->vf.bcn.tmi = tmi;
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spg_fc->vf.bcn.sym_num = 0;
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spg_fc->vf.bcn.phase_num = 0;
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spg_fc->vf.bcn.version = 0;
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}
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else if(glb_cfg.p_type == FC_DELIM_SOF)
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{
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spg_fc->delimiter_type = FC_DELIM_SOF; /*sof*/
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spg_fc->vf.sof.src_tei = glb_cfg.src_tei;
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spg_fc->vf.sof.dst_tei = glb_cfg.dst_tei;
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spg_fc->vf.sof.lid = 0;
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spg_fc->vf.sof.frm_len = 0;
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spg_fc->vf.sof.pb_num = glb_cfg.pb_num;
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spg_fc->vf.sof.sym_num = 0;
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spg_fc->vf.sof.tmi = tmi;
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spg_fc->vf.sof.tmi_ext = ext_tmi;
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spg_fc->vf.sof.version = 0;
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}
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spg_fc->access_ind = 1;
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spg_fc->snid = glb_cfg.nid;
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} else
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#endif
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#if (SUPPORT_GREEN_PHY)
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{
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/* AV FC */
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if(glb_cfg.p_type == DT_AV_BEACON)
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{
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hpav_fc->delimiter_type = DT_AV_BEACON;
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}
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else if(glb_cfg.p_type == DT_AV_SOF)
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{
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hpav_fc->delimiter_type = DT_AV_SOF;
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hpav_fc->vf_av.sof.src_tei = glb_cfg.src_tei;
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hpav_fc->vf_av.sof.dst_tei = glb_cfg.dst_tei;
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hpav_fc->vf_av.sof.lid = 0;
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hpav_fc->vf_av.sof.eks = 0xf;
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if(gp_tonemap_table[tmi].pb_size == 520)
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hpav_fc->vf_av.sof.pbsz = 0;
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else if(gp_tonemap_table[tmi].pb_size == 136)
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hpav_fc->vf_av.sof.pbsz = 1;
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else
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IOT_ASSERT(0);
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hpav_fc->vf_av.sof.numsym = 3;
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hpav_fc->vf_av.sof.tmi_av = glb_cfg.tmi;
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if (glb_cfg.tmi >= 4) {
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hpav_fc->vf_av.sof.fl_av = \
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hpav_cal_fl_tmap(glb_cfg.mpdu_cnt-1, glb_cfg.pb_num, \
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glb_cfg.turbo_rate, glb_cfg.gi, \
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phy_symb_bits_get((uint32_t *)PHY_TMAP_TEST_ADDR));
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} else {
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hpav_fc->vf_av.sof.fl_av = \
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hpav_cal_fl_robo(glb_cfg.tmi, glb_cfg.mpdu_cnt, glb_cfg.pb_num);
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}
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}
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else if(glb_cfg.p_type == DT_AV_RTS_CTS)
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{
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hpav_fc->delimiter_type = DT_AV_RTS_CTS;
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hpav_fc->vf_av.rtscts.src_tei = glb_cfg.src_tei;
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hpav_fc->vf_av.rtscts.dst_tei = glb_cfg.dst_tei;
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hpav_fc->vf_av.rtscts.lid = 0;
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hpav_fc->vf_av.rtscts.rtsf = 1;
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hpav_fc->vf_av.rtscts.dur = 300;
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}
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else if(glb_cfg.p_type == DT_AV_SOUND)
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{
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hpav_fc->delimiter_type = DT_AV_SOUND;
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hpav_fc->vf_av.sound.stei = glb_cfg.src_tei;
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hpav_fc->vf_av.sound.dtei = glb_cfg.dst_tei;
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hpav_fc->vf_av.sound.lid = 0;
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if(tmi == 0 || tmi == 1)
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{
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hpav_fc->vf_av.sound.pbsz = 0;
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phy_pld_gi1_set(GI_HS_ROBO);
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}
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else if(tmi == 2)
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{
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hpav_fc->vf_av.sound.pbsz = 1;
|
|
phy_pld_gi1_set(GI_MINI_ROBO);
|
|
}
|
|
hpav_fc->vf_av.sound.req_tm = 1;
|
|
hpav_fc->vf_av.sound.fl_av = 0;
|
|
hpav_fc->vf_av.sound.src = 0xFD;//as part of Initial Channel Estimation
|
|
}
|
|
hpav_fc->access = 1;
|
|
hpav_fc->snid = glb_cfg.nid;
|
|
}
|
|
#endif
|
|
{ /* for MACRO format */ }
|
|
|
|
/* hw id */
|
|
mpdu->swq_id = 0;
|
|
/* hw retry cnt */
|
|
mpdu->hw_retry_cnt = 0;
|
|
|
|
/* set the crc hdr len, GP is 4 for bcn */
|
|
if(glb_cfg.m_type == PLC_PROTO_TYPE_SG)
|
|
{
|
|
if(glb_cfg.p_type == FC_DELIM_BEACON)
|
|
{
|
|
mpdu->pb_hdr_crc_len = 3;
|
|
}
|
|
else if((glb_cfg.p_type == FC_DELIM_SOF)||(glb_cfg.p_type == FC_DELIM_SOUND))
|
|
{
|
|
mpdu->pb_hdr_crc_len = 4;
|
|
}
|
|
}
|
|
else if(glb_cfg.m_type == PLC_PROTO_TYPE_SPG)
|
|
{
|
|
if(glb_cfg.p_type == FC_DELIM_BEACON)
|
|
{
|
|
mpdu->pb_hdr_crc_len = 3;
|
|
}
|
|
else if((glb_cfg.p_type == FC_DELIM_SOF)||(glb_cfg.p_type == FC_DELIM_SOUND))
|
|
{
|
|
/* communicate with hs */
|
|
mpdu->pb_hdr_crc_len = 8;
|
|
}
|
|
}
|
|
else{
|
|
if(glb_cfg.p_type == DT_AV_BEACON)
|
|
{
|
|
mpdu->pb_hdr_crc_len = 4;
|
|
}
|
|
else if(glb_cfg.p_type == DT_AV_SOF)
|
|
{
|
|
mpdu->pb_hdr_crc_len = 8;
|
|
}
|
|
}
|
|
|
|
/* pb modulation and rate */
|
|
phy_get_pb_mod(glb_cfg.m_type,tmi, ext_tmi, &pb_mod);
|
|
mpdu->tx_pld_module_mode = pb_mod;
|
|
|
|
#if MAC_RATE_RANDOM_SUPPORT == 1
|
|
mpdu->tx_rate_mode = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR)%2;
|
|
(void)rate_mode;
|
|
#else
|
|
mpdu->tx_rate_mode = (rate_mode == 2)?1:rate_mode;
|
|
#endif
|
|
/* QR optimize */
|
|
if(rate_mode == IOT_SUPPORT_RATE_QR){
|
|
phy_qr_common_init();
|
|
}
|
|
else if(rate_mode == IOT_SUPPORT_RATE_XR){
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_CTRL_ADDR);
|
|
REG_FIELD_SET(CFG_MULTI_RATE_BASE_SPEED, tmp, 1);
|
|
RGF_MAC_WRITE_REG(CFG_PHY_CTRL_ADDR,tmp);
|
|
}
|
|
|
|
/* update cnt */
|
|
band_cnt[mpdu->tx_rate_mode][mpdu->sg_bandsel] += 1;
|
|
|
|
/* set hwq0's ptr list */
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_PTR_ADDR, (uint32_t)mpdu);
|
|
/* read NTB and fill in the start and end time
|
|
* by max time span value
|
|
*/
|
|
tmp = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_START_ADDR, tmp);
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_END_ADDR, (tmp + (0xffffffff >> 1) - 1));
|
|
|
|
#if IOT_DTEST_ONLY_SUPPORT == 1
|
|
/* update the beacon content */
|
|
uint32_t i = 0, j = 0;
|
|
if(glb_cfg.p_type == FC_DELIM_BEACON) {
|
|
tx_pb_start *current_pb_ptr = (tx_pb_start *)mpdu->pb_list;
|
|
hp_beacon_payload_fixed_header *pb_addr =
|
|
(hp_beacon_payload_fixed_header *)(current_pb_ptr->pb_buf_addr);
|
|
pb_addr->nid = PHY_TXRX_NID_VAL;
|
|
pb_addr->hm = 0;
|
|
pb_addr->stei = 1;
|
|
|
|
/* pb crc */
|
|
pb_addr->bmi.opad[0] = \
|
|
iot_getcrc32((uint8_t *)(pb_addr->bmi.opad), \
|
|
sizeof(pb_addr->bmi.opad) - 4);
|
|
/* init pb_buf with 4 pb */
|
|
for (i = 1; i < sizeof(pb_addr->bmi.opad)/4 - 1; i++)
|
|
{
|
|
pb_addr->bmi.opad[i] = pb_addr->bmi.opad[0]+i;
|
|
}
|
|
} else {
|
|
tx_pb_start *current_pb_ptr = (tx_pb_start *)mpdu->pb_list;
|
|
uint32_t *pb_other_buf = (uint32_t *)(current_pb_ptr->pb_buf_addr);
|
|
uint8_t pb_idx = (MAC_PB_NUM_ID > 4) ? 4 : MAC_PB_NUM_ID;
|
|
for (j = 0; j < pb_idx; j++)
|
|
{
|
|
for (i = 1; i < pb_size >> 2; i++)
|
|
{
|
|
pb_other_buf[i] = 0x55555555;//tmp + i;
|
|
}
|
|
pb_other_buf[0] = \
|
|
iot_getcrc32((uint8_t *)(pb_other_buf + 1), pb_size - 8);
|
|
/* update the next pb */
|
|
current_pb_ptr = (tx_pb_start *)current_pb_ptr->next_pb;
|
|
if(current_pb_ptr) {
|
|
pb_other_buf = (uint32_t *)(current_pb_ptr->pb_buf_addr);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return ERR_OK;
|
|
}
|
|
|
|
void dt_mac_tx_hwq0_re_trig()
|
|
{
|
|
uint32_t tmp = 0;
|
|
int64_t time_span = 0;
|
|
uint32_t start_time = 0, end_time = 0;
|
|
|
|
/* start time */
|
|
start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);/*for cnt*/
|
|
|
|
/* trigger hwq0 send */
|
|
tmp = RGF_HWQ_READ_REG(CFG_HWQ0_ADDR);
|
|
if (REG_FIELD_GET(CFG_DBG_HWQ0_EN, tmp)) {
|
|
/* if enable then disable first */
|
|
REG_FIELD_SET(CFG_DBG_HWQ0_EN, tmp, 0); // disable hwq
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_ADDR, tmp);
|
|
}
|
|
|
|
/* 10us with 0.04us unit */
|
|
while ((uint64_t)time_span < 250)
|
|
{
|
|
/* dly or tx fail if too quick */
|
|
end_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
|
|
time_span = end_time - start_time;
|
|
if (time_span < 0) { // wrap around
|
|
time_span = (0x100000000LL) - start_time + end_time;
|
|
}
|
|
}
|
|
|
|
REG_FIELD_SET(CFG_DBG_HWQ0_EN, tmp, 1); // enable hwq
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_ADDR, tmp);
|
|
|
|
if(glb_cfg.hwq_num > 1) {
|
|
/* trigger hwq1 send */
|
|
tmp = RGF_HWQ_READ_REG(CFG_HWQ1_ADDR);
|
|
if (REG_FIELD_GET(CFG_DBG_HWQ1_EN, tmp)) {
|
|
/* if enable then disable first */
|
|
REG_FIELD_SET(CFG_DBG_HWQ1_EN, tmp, 0); // disable hwq
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ1_ADDR, tmp);
|
|
}
|
|
REG_FIELD_SET(CFG_DBG_HWQ1_EN, tmp, 1); // enable hwq
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ1_ADDR, tmp);
|
|
}
|
|
}
|
|
|
|
void dt_mac_hwq0_ptr_set(uint32_t addr)
|
|
{
|
|
/* set hwq0's ptr list */
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_PTR_ADDR, addr);
|
|
}
|
|
|
|
void dt_mac_hwq1_ptr_set(uint32_t addr)
|
|
{
|
|
/* set hwq1's ptr list */
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ1_PTR_ADDR, addr);
|
|
}
|
|
|
|
void dtest_mac_bifs_set(uint16_t bifs)
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
tmp = RGF_TMR_READ_REG(CFG_TIMER5_ADDR);
|
|
REG_FIELD_SET(CFG_TX_BIFS_TIMER, tmp, bifs);
|
|
RGF_TMR_WRITE_REG(CFG_TIMER5_ADDR, tmp);
|
|
}
|
|
|
|
void mac_tx_burn_init()
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
#if 0
|
|
phy_txrx_ovr_set(1,2);
|
|
phy_gain_shift_set(0, 0, 0, 10);
|
|
#else
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
|
|
REG_FIELD_SET(CFG_PHY_PCS_BUSY, tmp, 0);
|
|
REG_FIELD_SET(CFG_PHY_PCS_BUSY_FORCE_EN, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_RX_VLD, tmp, 0);
|
|
REG_FIELD_SET(CFG_PHY_RX_VLD_FORCE_EN, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_RX_FRAME, tmp, 0);
|
|
REG_FIELD_SET(CFG_PHY_RX_FRAME_FORCE_EN, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_RX_READY, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_RX_READY_FORCE_EN, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_RX_ENABLE, tmp, 0);
|
|
REG_FIELD_SET(CFG_PHY_RX_ENABLE_FORCE_EN, tmp, 1);
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
|
|
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR);
|
|
REG_FIELD_SET(CFG_PHY_TX_ENABLE, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_TX_ENABLE_FORCE_EN, tmp, 1);
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_1_ADDR, tmp);
|
|
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR);
|
|
REG_FIELD_SET(CFG_PHY_TX_PHASE_SEL, tmp, 1);
|
|
REG_FIELD_SET(CFG_PHY_TX_PHASE_SEL_FORCE_EN, tmp, 1);
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_2_ADDR, tmp);
|
|
#if 0
|
|
/* en analog tx/rx */
|
|
uint8_t reg_id = ANA_GRANITE_TOP_REG;
|
|
uint32_t wdata = TOP_EN_TX_MASK | TOP_EN_DAC_MASK | \
|
|
TOP_EN_RX_MASK | TOP_EN_ADC_MASK | TOP_ENLIC_MASK;
|
|
uint32_t wmask = TOP_EN_TX_MASK | TOP_EN_DAC_MASK | \
|
|
TOP_EN_RX_MASK | TOP_EN_ADC_MASK | TOP_ENLIC_MASK;
|
|
phy_ana_i2c_write(reg_id,wdata,wmask);
|
|
#endif
|
|
|
|
#endif
|
|
}
|
|
|
|
void mac_tx_path_init()
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
/* enable DCU debug mode */
|
|
if(glb_cfg.t_type == MAC_TX_SCHED_BCN_AHEAD_ALERT) {
|
|
mac_txq_set_dbg_mode(0);// commandlist enable
|
|
} else {
|
|
mac_txq_set_dbg_mode(1);// debug enable
|
|
}
|
|
|
|
/* set hwq 0 's config */
|
|
/* set hwq0's type, cap */
|
|
tmp = RGF_HWQ_READ_REG(CFG_HWQ0_ADDR);
|
|
REG_FIELD_SET(CFG_DBG_HWQ0_TYPE, tmp, 0); // 0:TDMA, 1:CSMA
|
|
REG_FIELD_SET(CFG_DBG_HWQ0_CAP, tmp, 1); // CAP1 as default
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ0_ADDR, tmp);
|
|
if(glb_cfg.hwq_num > 1) {
|
|
/* set hwq1's type, cap */
|
|
tmp = RGF_HWQ_READ_REG(CFG_HWQ1_ADDR);
|
|
REG_FIELD_SET(CFG_DBG_HWQ1_TYPE, tmp, 0); // 0:TDMA, 1:CSMA
|
|
REG_FIELD_SET(CFG_DBG_HWQ1_CAP, tmp, 1); // CAP1 as default
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ1_ADDR, tmp);
|
|
}
|
|
|
|
/* set beacon period */
|
|
RGF_MAC_WRITE_REG(CFG_BEACON_PERIOD_ADDR, bcn_period_ms * TICKS_MS);
|
|
|
|
/* config my nid */
|
|
mac_config_nid(NULL, PHY_TXRX_NID_VAL);
|
|
|
|
/* tei cfg */
|
|
mac_config_tei(NULL, glb_cfg.src_tei);
|
|
|
|
/* enable and trigger the HW to load it */
|
|
tmp = RGF_MAC_READ_REG(CFG_TMI_CTRL_ADDR);
|
|
REG_FIELD_SET(CFG_TONE_AMP_EN, tmp, 0);
|
|
RGF_MAC_WRITE_REG(CFG_TMI_CTRL_ADDR, tmp);
|
|
|
|
/* delete timeout for long pkt */
|
|
RGF_TMR_WRITE_REG(CFG_TX_TIMEOUT_0_ADDR,0x0);
|
|
RGF_TMR_WRITE_REG(CFG_TX_TIMEOUT_1_ADDR,0x0);
|
|
RGF_TMR_WRITE_REG(CFG_TX_TIMEOUT_2_ADDR,0x0);
|
|
RGF_TMR_WRITE_REG(CFG_PHY_TX_TIMEOUT_ADDR,0x0);
|
|
|
|
#if MAC_TX_TEST_ID == MAC_TX_BURN
|
|
/* force tx */
|
|
mac_tx_burn_init();
|
|
#endif
|
|
|
|
/* set txq self poll interval */
|
|
mac_txq_set_poll_intval(1023); /* 1023 us */
|
|
|
|
/* check phy pwr sts */
|
|
phy_pm_pwr_update(PHY_PM_PWR_STS_TXRX);
|
|
|
|
/* mac auto trig */
|
|
mac_sw_trig_need_en(false);
|
|
mac_sw_trig_start(true);
|
|
|
|
/* clr phy cnt */
|
|
phy_tx_dbg_cnt_clr();
|
|
|
|
/* sw frame length en */
|
|
if (PHY_PROTO_TYPE_GET() == PLC_PROTO_TYPE_GP) {
|
|
mac_set_fc_fl_cfg_status(true);
|
|
}
|
|
|
|
/* hw retry */
|
|
tmp = RGF_MAC_READ_REG(CFG_TX_CTRL1_ADDR);
|
|
REG_FIELD_SET(CFG_HWRETRY_MODIFY, tmp , 0);
|
|
RGF_MAC_WRITE_REG(CFG_TX_CTRL1_ADDR, tmp);
|
|
}
|
|
|
|
static void geode_gpio_init(uint32_t chip_id)
|
|
{
|
|
switch (chip_id) {
|
|
case CHIP_ID_HZ3201_V1A:
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_EN_A, 34);
|
|
gpio_mtx_sig_out(GPIO_MTX_TX_EN_A, 35);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_EN_B, 36);
|
|
gpio_mtx_sig_out(GPIO_MTX_TX_EN_B, 37);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_EN_C, 38);
|
|
gpio_mtx_sig_out(GPIO_MTX_TX_EN_C, 39);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_0, 7);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_1, 8);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_2, 26);
|
|
break;
|
|
case CHIP_ID_HZ3211_V1A:
|
|
/* geode gpio init */
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_EN_A, 34);
|
|
gpio_mtx_sig_out(GPIO_MTX_TX_EN_A, 35);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_0, 7);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_1, 8);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_2, 26);
|
|
break;
|
|
case CHIP_ID_WQ3031_V1A:
|
|
/* geode gpio init */
|
|
gpio_mtx_sig_out(GPIO_MTX_ENLIC_0, 80);
|
|
gpio_mtx_sig_out(GPIO_MTX_ENLIC_1, 81);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_0, 82);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_1, 83);
|
|
gpio_mtx_sig_out(GPIO_MTX_RX_GLNA_2, 84);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void platform_tx_pre_init()
|
|
{
|
|
#if HW_PLATFORM > HW_PLATFORM_FPGA
|
|
uint32_t chip_id = iot_chip_get_chip_info();
|
|
#else
|
|
uint32_t chip_id = 0;
|
|
#endif
|
|
|
|
/* change clk to 150M */
|
|
clk_core_freq_set(CPU_FREQ_150M);
|
|
/* enable timer */
|
|
gp_timer_init();
|
|
gp_timer_enable(0,0,0);
|
|
|
|
/* geode gpio init */
|
|
geode_gpio_init(chip_id);
|
|
|
|
/* alloc 1K size ram */
|
|
os_mem_init((uint8_t *)HW_TX_ALLOC_POOL, HW_TX_ALLOC_MEM_BYTE);
|
|
|
|
/* reset phy */
|
|
phy_reset(PHY_RST_REASON_COLD);
|
|
/* reset mac */
|
|
mac_reset(MAC_RST_REASON_COLD);
|
|
}
|
|
|
|
bool_t phy_get_tx_done_from_mpdu(volatile tx_mpdu_start *mpdu)
|
|
{
|
|
return ((tx_mpdu_end*)mpdu->tx_status)->tx_done;
|
|
}
|
|
|
|
void phy_tx_done_clr(volatile tx_mpdu_start *mpdu)
|
|
{
|
|
((tx_mpdu_end*)mpdu->tx_status)->tx_done = 0;
|
|
}
|
|
|
|
uint32_t mpdu_pb_list_get_from_pb_start(tx_pb_start *pb_start)
|
|
{
|
|
return (uint32_t)pb_start;
|
|
}
|
|
|
|
uint32_t mpdu_tx_status_get_from_mpdu_end(tx_mpdu_end *mpdu_end)
|
|
{
|
|
return (uint32_t)mpdu_end;
|
|
}
|
|
|
|
uint32_t tx_complete_handler(uint32_t vector, iot_addrword_t data)
|
|
{
|
|
#if IOT_DTEST_ONLY_SUPPORT == 1
|
|
uint32_t status;
|
|
|
|
status = RGF_MAC_READ_REG(CFG_MAC_INT_STS_ADDR);
|
|
//iot_printf("intc status=0x%x\r\n",status);
|
|
|
|
if(status & (0x1 <<5)){
|
|
/* clear intr */
|
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, 0x1<<5);
|
|
RGF_HWQ_WRITE_REG(CFG_HWQ_TX_DONE_INT_CLR_ADDR,0xf);
|
|
if(!phy_get_tx_done_from_mpdu(mpdu_start))
|
|
iot_printf("Intr complete,but tx not done!\r\n");
|
|
phy_tx_done_clr(mpdu_start);
|
|
mac_tx_complete_flag = true;
|
|
}
|
|
|
|
if(status & (0x1 <<0)){
|
|
/* clear intr */
|
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, 0x1<<0);
|
|
mac_beacon_alert_flag = true;
|
|
}
|
|
|
|
if(status & (0x1 <<4)){
|
|
/* clear intr */
|
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, 0x1<<4);
|
|
|
|
mac_beacon_alert_flag = true;
|
|
}
|
|
|
|
#if MODULE_EN
|
|
/* single interrupt handler */
|
|
INTC_WRITE_REG(CFG_INT_ENA0_ADDR,0x0);
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
|
|
void mac_interrupt_init()
|
|
{
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#if IOT_DTEST_ONLY_SUPPORT == 1
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uint32_t tmp = 0;
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iot_mac_intr_info_t mac_info;
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os_mem_set(&mac_info, 0x0, sizeof(iot_mac_intr_info_t));
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/* intc en */
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INTC0_WRITE_REG(CFG_INT_ENA0_ADDR,MAC_INT_MPDU_TX_DONE_BIT_MASK | MAC_INT_BCN_ALERT_BIT_MASK);
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/* clr mac int */
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RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, MAC_INT_MPDU_TX_DONE_BIT_MASK);//tx complete
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RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, MAC_INT_BCN_ALERT_BIT_MASK);//tx beacon alert
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/* MPDU done intr enable */
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tmp = RGF_MAC_READ_REG(CFG_INT_ENA_MASK_ADDR);
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if(glb_cfg.t_type == MAC_TX_INTR_MPDU_COMPLETE)
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REG_FIELD_SET(CFG_INT_ENABLE_MASK,tmp,MAC_INT_MPDU_TX_DONE_BIT_MASK);
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else if(glb_cfg.t_type == MAC_TX_INTR_BCN_ALT)
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REG_FIELD_SET(CFG_INT_ENABLE_MASK,tmp,MAC_INT_BCN_ALERT_BIT_MASK);
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else if(glb_cfg.t_type == MAC_TX_SCHED_BCN_AHEAD_ALERT)
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REG_FIELD_SET(CFG_INT_ENABLE_MASK,tmp,MAC_INT_MPDU_TX_DONE_BIT_MASK);
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RGF_MAC_WRITE_REG(CFG_INT_ENA_MASK_ADDR, tmp);
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|
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/* pri int */
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tmp = RGF_MAC_READ_REG(CFG_INT_PRI1_MASK_ADDR);
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REG_FIELD_SET(CFG_INT_PRI1_MASK,tmp,MAC_INT_BCN_ALERT_BIT_MASK | MAC_INT_MPDU_TX_DONE_BIT_MASK);
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RGF_MAC_WRITE_REG(CFG_INT_PRI1_MASK_ADDR, tmp);
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|
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/* interrupt controller */
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mac_info.int_num = MAC_INT_1;
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mac_info.handle = iot_interrupt_create( mac_info.int_num, 0, \
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(iot_addrword_t)&mac_info, tx_complete_handler);
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iot_interrupt_attach( mac_info.handle);
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iot_interrupt_unmask( mac_info.handle);
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#endif
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}
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uint32_t IRAM_ATTR phy_intr_handler(uint32_t vector, iot_addrword_t data)
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{
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return 0;
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}
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|
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void phy_interrupt_init()
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{
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|
|
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}
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|
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void mac_tmap_init()
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{
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uint32_t tmp = 0;
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|
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tmp = RGF_MAC_READ_REG(CFG_TONE_MAP_DMA_CTRL_ADDR);
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REG_FIELD_SET(CFG_TMAP_LOAD_EN, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_TONE_MAP_DMA_CTRL_ADDR, tmp);
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tmp = RGF_MAC_READ_REG(CFG_TMI_CTRL_ADDR);
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REG_FIELD_SET(CFG_ENABLE_MAC_LOAD_TMI, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_TMI_CTRL_ADDR, tmp);
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|
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tmp = RGF_MAC_READ_REG(CFG_GP_CTRL_ADDR);
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REG_FIELD_SET(CFG_GP_PB_SIZE_SEL, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_GP_CTRL_ADDR, tmp);
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|
|
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tmp = RGF_TMR_READ_REG(CFG_TX_FC_CTRL_ADDR);
|
|
REG_FIELD_SET(CFG_TX_FC_FL_BY_SW, tmp , 1);
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|
RGF_TMR_WRITE_REG(CFG_TX_FC_CTRL_ADDR, tmp);
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|
}
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