213 lines
6.7 KiB
C
Executable File
213 lines
6.7 KiB
C
Executable File
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//-----------------------------------
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#define CFG_ANA_RX_REG_0_ADDR 0x0000
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#define RX_PWDPGFOFFSET_OFFSET 30
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#define RX_PWDPGFOFFSET_MASK 0x40000000
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#define RX_PWDPGAOFFSET_OFFSET 29
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#define RX_PWDPGAOFFSET_MASK 0x20000000
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#define RX_PWDCGM_OFFSET 28
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#define RX_PWDCGM_MASK 0x10000000
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#define RX_PGFLOOPEN_OFFSET 27
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#define RX_PGFLOOPEN_MASK 0x08000000
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#define RX_BYPHPF_OFFSET 26
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#define RX_BYPHPF_MASK 0x04000000
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#define RX_HPFENORD2_OFFSET 25
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#define RX_HPFENORD2_MASK 0x02000000
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#define RX_PGAOFFSET_OFFSET 20
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#define RX_PGAOFFSET_MASK 0x01F00000
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#define RX_PGFOFFSET_OFFSET 14
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#define RX_PGFOFFSET_MASK 0x000FC000
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#define RX_SELC_OFFSET 8
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#define RX_SELC_MASK 0x00003F00
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#define RX_GPGA_OFFSET 4
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#define RX_GPGA_MASK 0x000000F0
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#define RX_GBQ_OFFSET 2
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#define RX_GBQ_MASK 0x0000000C
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#define RX_GPGF_OFFSET 0
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#define RX_GPGF_MASK 0x00000003
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//-----------------------------------
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#define CFG_ANA_RX_REG_1_ADDR 0x0001
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#define RX_PGATESTEN_OFFSET 14
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#define RX_PGATESTEN_MASK 0x00004000
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#define RX_BQTESTEN_OFFSET 13
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#define RX_BQTESTEN_MASK 0x00002000
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#define RX_PGFTESTEN_OFFSET 12
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#define RX_PGFTESTEN_MASK 0x00001000
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#define RX_HPFTESTEN_OFFSET 11
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#define RX_HPFTESTEN_MASK 0x00000800
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#define RX_TESTEN_OFFSET 10
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#define RX_TESTEN_MASK 0x00000400
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#define RX_ATB_OFFSET 5
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#define RX_ATB_MASK 0x000003E0
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#define RX_CGMBYP_OFFSET 0
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#define RX_CGMBYP_MASK 0x0000001F
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//-----------------------------------
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#define CFG_ANA_ADC_REG_ADDR 0x0002
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#define ADC_ATB_SEL_OFFSET 13
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#define ADC_ATB_SEL_MASK 0x00006000
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#define ADC_EN_CAL_COUNTER_OFFSET 12
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#define ADC_EN_CAL_COUNTER_MASK 0x00001000
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#define ADC_EN_TIMER_OFFSET 11
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#define ADC_EN_TIMER_MASK 0x00000800
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#define ADC_CFG_SAMPLE_CLK_OFFSET 10
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#define ADC_CFG_SAMPLE_CLK_MASK 0x00000400
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#define ADC_F_H_OFFSET 7
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#define ADC_F_H_MASK 0x00000380
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#define ADC_CFG_DLY_OFFSET 4
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#define ADC_CFG_DLY_MASK 0x00000070
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#define ADC_TIMER_DLY_OFFSET 0
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#define ADC_TIMER_DLY_MASK 0x0000000F
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//-----------------------------------
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#define CFG_ANA_SADC_REG_ADDR 0x0003
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#define SADC_EN_CAL_OFFSET 27
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#define SADC_EN_CAL_MASK 0x08000000
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#define SADC_METER2PAD_EN_NEG_OVR_OFFSET 25
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#define SADC_METER2PAD_EN_NEG_OVR_MASK 0x06000000
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#define SADC_METER2PAD_EN_OVR_OFFSET 21
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#define SADC_METER2PAD_EN_OVR_MASK 0x01E00000
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#define SADC_SCLR_CNTRL_DIV2_DIV5_OFFSET 20
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#define SADC_SCLR_CNTRL_DIV2_DIV5_MASK 0x00100000
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#define SADC_SEL_SCL_MUX_OFFSET 17
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#define SADC_SEL_SCL_MUX_MASK 0x000E0000
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#define SADC_EN_CAL_COUNTER_OFFSET 16
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#define SADC_EN_CAL_COUNTER_MASK 0x00010000
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#define SADC_EN_OFFSET 15
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#define SADC_EN_MASK 0x00008000
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#define SADC_RESET_N_OFFSET 14
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#define SADC_RESET_N_MASK 0x00004000
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#define SADC_EN_TIMER_OFFSET 13
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#define SADC_EN_TIMER_MASK 0x00002000
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#define SADC_ATB_SEL_OFFSET 11
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#define SADC_ATB_SEL_MASK 0x00001800
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#define SADC_SAMPLE_SEL_OFFSET 10
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#define SADC_SAMPLE_SEL_MASK 0x00000400
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#define SADC_F_H_OFFSET 7
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#define SADC_F_H_MASK 0x00000380
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#define SADC_CFG_DLY_OFFSET 4
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#define SADC_CFG_DLY_MASK 0x00000070
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#define SADC_TIMER_DLY_OFFSET 0
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#define SADC_TIMER_DLY_MASK 0x0000000F
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//-----------------------------------
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#define CFG_ANA_PLL_REG_ADDR 0x0004
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#define PLL_CHANGE_CHANNEL_OFFSET 15
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#define PLL_CHANGE_CHANNEL_MASK 0x00008000
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#define PLL_BP_OFFSET 14
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#define PLL_BP_MASK 0x00004000
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#define PLL_M_OFFSET 6
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#define PLL_M_MASK 0x00003FC0
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#define PLL_N_OFFSET 2
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#define PLL_N_MASK 0x0000003C
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#define PLL_OD_OFFSET 0
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#define PLL_OD_MASK 0x00000003
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//-----------------------------------
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#define CFG_ANA_DAC_REG_ADDR 0x0005
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#define DAC_INVCLKEN_OFFSET 14
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#define DAC_INVCLKEN_MASK 0x00004000
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#define DAC_MINSCALE_B_OFFSET 13
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#define DAC_MINSCALE_B_MASK 0x00002000
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#define DAC_FULLSCALE_OFFSET 12
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#define DAC_FULLSCALE_MASK 0x00001000
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#define DAC_BURNIN_OFFSET 11
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#define DAC_BURNIN_MASK 0x00000800
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#define DAC_DATAOVREN_OFFSET 10
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#define DAC_DATAOVREN_MASK 0x00000400
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#define DAC_DATAOVR_OFFSET 0
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#define DAC_DATAOVR_MASK 0x000003FF
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//-----------------------------------
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#define CFG_ANA_TX_REG_ADDR 0x0006
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#define TX_ATB_OFFSET 12
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#define TX_ATB_MASK 0x0003F000
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#define TX_CGMBYP_OFFSET 7
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#define TX_CGMBYP_MASK 0x00000F80
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#define TX_PWDCGM_OFFSET 6
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#define TX_PWDCGM_MASK 0x00000040
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#define TX_GPGA_OFFSET 4
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#define TX_GPGA_MASK 0x00000030
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#define TX_PGATESTEN_OFFSET 3
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#define TX_PGATESTEN_MASK 0x00000008
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#define TX_FLTTESTEN_OFFSET 2
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#define TX_FLTTESTEN_MASK 0x00000004
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#define TX_TESTEN_OFFSET 1
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#define TX_TESTEN_MASK 0x00000002
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#define TX_COMPEN_OFFSET 0
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#define TX_COMPEN_MASK 0x00000001
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//-----------------------------------
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#define CFG_ANA_BIAS_REG_0_ADDR 0x0007
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#define BIAS_ADJ_IR25U_BIT0_OFFSET 21
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#define BIAS_ADJ_IR25U_BIT0_MASK 0xFFE00000
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#define BIAS_ADJ_IC25U_BIT0_OFFSET 0
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#define BIAS_ADJ_IC25U_BIT0_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_ANA_BIAS_REG_1_ADDR 0x0008
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#define BIAS_ADJ_IR25U_BIT1_OFFSET 21
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#define BIAS_ADJ_IR25U_BIT1_MASK 0xFFE00000
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#define BIAS_ADJ_IC25U_BIT1_OFFSET 0
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#define BIAS_ADJ_IC25U_BIT1_MASK 0x001FFFFF
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//-----------------------------------
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#define CFG_ANA_BIAS_REG_2_ADDR 0x0009
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#define BIAS_SEL_IC_TEST_OFFSET 24
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#define BIAS_SEL_IC_TEST_MASK 0xFF000000
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#define BIAS_SEL_IR_TEST_OFFSET 17
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#define BIAS_SEL_IR_TEST_MASK 0x00FE0000
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#define BIAS_SEL_VBG_TEST_OFFSET 16
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#define BIAS_SEL_VBG_TEST_MASK 0x00010000
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#define BIAS_TEST_VBG_OFFSET 15
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#define BIAS_TEST_VBG_MASK 0x00008000
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#define BIAS_EN_ICAL_OFFSET 14
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#define BIAS_EN_ICAL_MASK 0x00004000
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#define BIAS_CAL_OFFSET 9
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#define BIAS_CAL_MASK 0x00003E00
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#define BIAS_TRIM_SADCREF_OFFSET 6
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#define BIAS_TRIM_SADCREF_MASK 0x000001C0
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#define BIAS_TRIM_ADCREF_OFFSET 3
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#define BIAS_TRIM_ADCREF_MASK 0x00000038
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#define BIAS_TRIM_DCDC_OFFSET 0
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#define BIAS_TRIM_DCDC_MASK 0x00000007
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//-----------------------------------
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#define CFG_ANA_TOP_REG_ADDR 0x000A
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#define TOP_TX_DIV_OVR_OFFSET 23
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#define TOP_TX_DIV_OVR_MASK 0x01800000
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#define TOP_RX_DIV_OVR_OFFSET 21
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#define TOP_RX_DIV_OVR_MASK 0x00600000
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#define TOP_EN_XO_OFFSET 19
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#define TOP_EN_XO_MASK 0x00080000
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#define TOP_EN_PLLOUT_300M_OFFSET 18
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#define TOP_EN_PLLOUT_300M_MASK 0x00040000
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#define TOP_EN_DAC_OFFSET 17
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#define TOP_EN_DAC_MASK 0x00020000
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#define TOP_RESET_N_ADC_OFFSET 16
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#define TOP_RESET_N_ADC_MASK 0x00010000
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#define TOP_EN_ADC_OFFSET 15
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#define TOP_EN_ADC_MASK 0x00008000
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#define TOP_TESTPAD_EN_OFFSET 14
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#define TOP_TESTPAD_EN_MASK 0x00004000
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#define TOP_ATB2PAD_EN_OFFSET 13
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#define TOP_ATB2PAD_EN_MASK 0x00002000
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#define TOP_GLNA_OFFSET 10
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#define TOP_GLNA_MASK 0x00001C00
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#define TOP_ENLIC_OFFSET 8
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#define TOP_ENLIC_MASK 0x00000300
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#define TOP_SADC_SCALING_OFFSET 7
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#define TOP_SADC_SCALING_MASK 0x00000080
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#define TOP_SEL_METER_INPUT_OFFSET 4
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#define TOP_SEL_METER_INPUT_MASK 0x00000070
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#define TOP_EN_SADC_OFFSET 3
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#define TOP_EN_SADC_MASK 0x00000008
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#define TOP_EN_BIAS_OFFSET 2
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#define TOP_EN_BIAS_MASK 0x00000004
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#define TOP_EN_TX_OFFSET 1
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#define TOP_EN_TX_MASK 0x00000002
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#define TOP_EN_RX_OFFSET 0
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#define TOP_EN_RX_MASK 0x00000001
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