578 lines
24 KiB
C
Executable File
578 lines
24 KiB
C
Executable File
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//-----------------------------------
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#define CFG_SADC0_RVER_ADDR 0x0000
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#define SADC0_RF_VER_OFFSET 0
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#define SADC0_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SADC0_CHN_CFG_ADDR 0x0004
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#define CHN1_TOP_SOFT_RST_OFFSET 31
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#define CHN1_TOP_SOFT_RST_MASK 0x80000000
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#define CHN1_PHASE3_3_KEEP_RAW_REGDATA_OFFSET 30
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#define CHN1_PHASE3_3_KEEP_RAW_REGDATA_MASK 0x40000000
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#define CHN1_PHASE3_2_KEEP_RAW_REGDATA_OFFSET 29
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#define CHN1_PHASE3_2_KEEP_RAW_REGDATA_MASK 0x20000000
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#define CHN1_PHASE3_1_KEEP_RAW_REGDATA_OFFSET 28
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#define CHN1_PHASE3_1_KEEP_RAW_REGDATA_MASK 0x10000000
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#define CHN1_PHASE3_0_KEEP_RAW_REGDATA_OFFSET 27
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#define CHN1_PHASE3_0_KEEP_RAW_REGDATA_MASK 0x08000000
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#define CHN1_PHASE2_KEEP_RAW_REGDATA_OFFSET 26
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#define CHN1_PHASE2_KEEP_RAW_REGDATA_MASK 0x04000000
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#define CHN1_PHASE1_KEEP_RAW_REGDATA_OFFSET 25
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#define CHN1_PHASE1_KEEP_RAW_REGDATA_MASK 0x02000000
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#define CHN1_PHASE0_KEEP_RAW_REGDATA_OFFSET 24
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#define CHN1_PHASE0_KEEP_RAW_REGDATA_MASK 0x01000000
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#define CHN1_START_SEL_OFFSET 23
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#define CHN1_START_SEL_MASK 0x00800000
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#define CHN1_PHASE3_3_KEEP_RAW_DATA_OFFSET 22
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#define CHN1_PHASE3_3_KEEP_RAW_DATA_MASK 0x00400000
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#define CHN1_PHASE3_2_KEEP_RAW_DATA_OFFSET 21
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#define CHN1_PHASE3_2_KEEP_RAW_DATA_MASK 0x00200000
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#define CHN1_PHASE3_1_KEEP_RAW_DATA_OFFSET 20
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#define CHN1_PHASE3_1_KEEP_RAW_DATA_MASK 0x00100000
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#define CHN1_PHASE3_0_KEEP_RAW_DATA_OFFSET 19
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#define CHN1_PHASE3_0_KEEP_RAW_DATA_MASK 0x00080000
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#define CHN1_PHASE2_KEEP_RAW_DATA_OFFSET 18
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#define CHN1_PHASE2_KEEP_RAW_DATA_MASK 0x00040000
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#define CHN1_PHASE1_KEEP_RAW_DATA_OFFSET 17
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#define CHN1_PHASE1_KEEP_RAW_DATA_MASK 0x00020000
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#define CHN1_PHASE0_KEEP_RAW_DATA_OFFSET 16
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#define CHN1_PHASE0_KEEP_RAW_DATA_MASK 0x00010000
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#define CHN1_HIGH_PREC_SINGLE_PHASE_MOD_OFFSET 15
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#define CHN1_HIGH_PREC_SINGLE_PHASE_MOD_MASK 0x00008000
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#define CHN1_FILTER_CLK_FRC_ON_OFFSET 14
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#define CHN1_FILTER_CLK_FRC_ON_MASK 0x00004000
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#define CHN1_WAIT_ANA_SAT_TIME_OFFSET 6
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#define CHN1_WAIT_ANA_SAT_TIME_MASK 0x00003FC0
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#define CHN1_SINGLE_PHASE_SETTING_OFFSET 4
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#define CHN1_SINGLE_PHASE_SETTING_MASK 0x00000030
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#define CHN1_SDM_SAT_BYPASS_OFFSET 3
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#define CHN1_SDM_SAT_BYPASS_MASK 0x00000008
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#define CHN1_STOP_OFFSET 2
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#define CHN1_STOP_MASK 0x00000004
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#define CHN1_START_OFFSET 1
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#define CHN1_START_MASK 0x00000002
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//-----------------------------------
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#define CFG_SADC0_CHN_MUX_SEL_CFG_ADDR 0x0008
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#define CHN1_PHASE3_3_SEL_MUX_OFFSET 28
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#define CHN1_PHASE3_3_SEL_MUX_MASK 0xF0000000
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#define CHN1_PHASE3_2_SEL_MUX_OFFSET 24
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#define CHN1_PHASE3_2_SEL_MUX_MASK 0x0F000000
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#define CHN1_PHASE3_1_SEL_MUX_OFFSET 20
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#define CHN1_PHASE3_1_SEL_MUX_MASK 0x00F00000
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#define CHN1_PHASE3_0_SEL_MUX_OFFSET 16
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#define CHN1_PHASE3_0_SEL_MUX_MASK 0x000F0000
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#define CHN1_PHASE2_SEL_MUX_OFFSET 8
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#define CHN1_PHASE2_SEL_MUX_MASK 0x00000F00
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#define CHN1_PHASE1_SEL_MUX_OFFSET 4
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#define CHN1_PHASE1_SEL_MUX_MASK 0x000000F0
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#define CHN1_PHASE0_SEL_MUX_OFFSET 0
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#define CHN1_PHASE0_SEL_MUX_MASK 0x0000000F
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//-----------------------------------
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#define CFG_SADC0_CHN_SAMPLE_TIME_ADDR 0x000C
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#define CHN1_SUB_PHASE3_SETTING_OFFSET 30
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#define CHN1_SUB_PHASE3_SETTING_MASK 0xC0000000
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#define CHN1_PHASE3_3_CLR_AUTO_EN_OFFSET 29
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#define CHN1_PHASE3_3_CLR_AUTO_EN_MASK 0x20000000
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#define CHN1_PHASE3_2_CLR_AUTO_EN_OFFSET 28
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#define CHN1_PHASE3_2_CLR_AUTO_EN_MASK 0x10000000
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#define CHN1_PHASE3_1_CLR_AUTO_EN_OFFSET 27
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#define CHN1_PHASE3_1_CLR_AUTO_EN_MASK 0x08000000
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#define CHN1_PHASE3_0_CLR_AUTO_EN_OFFSET 26
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#define CHN1_PHASE3_0_CLR_AUTO_EN_MASK 0x04000000
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#define CHN1_PHASE2_CLR_AUTO_EN_OFFSET 25
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#define CHN1_PHASE2_CLR_AUTO_EN_MASK 0x02000000
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#define CHN1_PHASE1_CLR_AUTO_EN_OFFSET 24
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#define CHN1_PHASE1_CLR_AUTO_EN_MASK 0x01000000
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#define CHN1_PHASE0_CLR_AUTO_EN_OFFSET 23
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#define CHN1_PHASE0_CLR_AUTO_EN_MASK 0x00800000
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#define CHN1_WAIT_SDM_SAT_TIME_OFFSET 16
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#define CHN1_WAIT_SDM_SAT_TIME_MASK 0x000F0000
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#define CHN1_SAMPLE_DATA_3RD_NUM_OFFSET 12
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#define CHN1_SAMPLE_DATA_3RD_NUM_MASK 0x0000F000
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#define CHN1_SAMPLE_DATA_2ND_NUM_OFFSET 4
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#define CHN1_SAMPLE_DATA_2ND_NUM_MASK 0x00000FF0
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#define CHN1_SAMPLE_DATA_1ST_NUM_OFFSET 0
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#define CHN1_SAMPLE_DATA_1ST_NUM_MASK 0x0000000F
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//-----------------------------------
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#define CFG_SADC0_CHN_FILTER_CFG_ADDR 0x0010
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#define CHN1_PHASE3_3_FILTER_CNT_LIMIT_OFFSET 28
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#define CHN1_PHASE3_3_FILTER_CNT_LIMIT_MASK 0x30000000
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#define CHN1_PHASE3_2_FILTER_CNT_LIMIT_OFFSET 26
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#define CHN1_PHASE3_2_FILTER_CNT_LIMIT_MASK 0x0C000000
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#define CHN1_PHASE3_1_FILTER_CNT_LIMIT_OFFSET 24
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#define CHN1_PHASE3_1_FILTER_CNT_LIMIT_MASK 0x03000000
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#define CHN1_PHASE3_0_FILTER_CNT_LIMIT_OFFSET 22
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#define CHN1_PHASE3_0_FILTER_CNT_LIMIT_MASK 0x00C00000
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#define CHN1_PHASE2_FILTER_CNT_LIMIT_OFFSET 20
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#define CHN1_PHASE2_FILTER_CNT_LIMIT_MASK 0x00300000
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#define CHN1_PHASE1_FILTER_CNT_LIMIT_OFFSET 18
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#define CHN1_PHASE1_FILTER_CNT_LIMIT_MASK 0x000C0000
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#define CHN1_PHASE0_FILTER_CNT_LIMIT_OFFSET 16
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#define CHN1_PHASE0_FILTER_CNT_LIMIT_MASK 0x00030000
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#define METER_ADC_CHN1_DO_ORDER_OFFSET 10
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#define METER_ADC_CHN1_DO_ORDER_MASK 0x00000400
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#define CHN1_SINC_CNT_LIMIT_OFFSET 5
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#define CHN1_SINC_CNT_LIMIT_MASK 0x000003E0
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#define METER_ADC_CHN1_DO3_INV_OFFSET 4
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#define METER_ADC_CHN1_DO3_INV_MASK 0x00000010
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#define METER_ADC_CHN1_DO2_INV_OFFSET 3
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#define METER_ADC_CHN1_DO2_INV_MASK 0x00000008
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#define METER_ADC_CHN1_DO1_INV_OFFSET 2
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#define METER_ADC_CHN1_DO1_INV_MASK 0x00000004
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#define METER_ADC_CHN1_DO_SEL_OFFSET 0
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#define METER_ADC_CHN1_DO_SEL_MASK 0x00000003
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//-----------------------------------
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#define CFG_SADC0_PHASE0_THRS_CFG_ADDR 0x0014
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#define ADC0_PHASE0_THRS_OFFSET 0
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#define ADC0_PHASE0_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE1_THRS_CFG_ADDR 0x0018
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#define ADC0_PHASE1_THRS_OFFSET 0
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#define ADC0_PHASE1_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE2_THRS_CFG_ADDR 0x001C
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#define ADC0_PHASE2_THRS_OFFSET 0
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#define ADC0_PHASE2_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_0_THRS_CFG_ADDR 0x0020
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#define ADC0_PHASE3_0_THRS_OFFSET 0
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#define ADC0_PHASE3_0_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_1_THRS_CFG_ADDR 0x0024
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#define ADC0_PHASE3_1_THRS_OFFSET 0
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#define ADC0_PHASE3_1_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_2_THRS_CFG_ADDR 0x0028
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#define ADC0_PHASE3_2_THRS_OFFSET 0
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#define ADC0_PHASE3_2_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_3_THRS_CFG_ADDR 0x002C
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#define ADC0_PHASE3_3_THRS_OFFSET 0
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#define ADC0_PHASE3_3_THRS_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE_DATA_CLR_ADDR 0x0030
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#define ADC0_PHASE3_3_CLR_OFFSET 6
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#define ADC0_PHASE3_3_CLR_MASK 0x00000040
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#define ADC0_PHASE3_2_CLR_OFFSET 5
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#define ADC0_PHASE3_2_CLR_MASK 0x00000020
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#define ADC0_PHASE3_1_CLR_OFFSET 4
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#define ADC0_PHASE3_1_CLR_MASK 0x00000010
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#define ADC0_PHASE3_0_CLR_OFFSET 3
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#define ADC0_PHASE3_0_CLR_MASK 0x00000008
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#define ADC0_PHASE2_CLR_OFFSET 2
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#define ADC0_PHASE2_CLR_MASK 0x00000004
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#define ADC0_PHASE1_CLR_OFFSET 1
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#define ADC0_PHASE1_CLR_MASK 0x00000002
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#define ADC0_PHASE0_CLR_OFFSET 0
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#define ADC0_PHASE0_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_SADC0_PHASE0_RDATA_ADDR 0x0034
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#define ADC0_PHASE0_DATA_VALID_OFFSET 24
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#define ADC0_PHASE0_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE0_DATA_OFFSET 0
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#define ADC0_PHASE0_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE1_RDATA_ADDR 0x0038
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#define ADC0_PHASE1_DATA_VALID_OFFSET 24
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#define ADC0_PHASE1_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE1_DATA_OFFSET 0
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#define ADC0_PHASE1_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE2_RDATA_ADDR 0x003C
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#define ADC0_PHASE2_DATA_VALID_OFFSET 24
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#define ADC0_PHASE2_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE2_DATA_OFFSET 0
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#define ADC0_PHASE2_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_0_RDATA_ADDR 0x0040
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#define ADC0_PHASE3_0_DATA_VALID_OFFSET 24
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#define ADC0_PHASE3_0_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE3_0_DATA_OFFSET 0
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#define ADC0_PHASE3_0_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_1_RDATA_ADDR 0x0044
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#define ADC0_PHASE3_1_DATA_VALID_OFFSET 24
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#define ADC0_PHASE3_1_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE3_1_DATA_OFFSET 0
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#define ADC0_PHASE3_1_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_2_RDATA_ADDR 0x0048
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#define ADC0_PHASE3_2_DATA_VALID_OFFSET 24
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#define ADC0_PHASE3_2_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE3_2_DATA_OFFSET 0
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#define ADC0_PHASE3_2_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_PHASE3_3_RDATA_ADDR 0x004C
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#define ADC0_PHASE3_3_DATA_VALID_OFFSET 24
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#define ADC0_PHASE3_3_DATA_VALID_MASK 0x01000000
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#define ADC0_PHASE3_3_DATA_OFFSET 0
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#define ADC0_PHASE3_3_DATA_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_SADC0_MTR_SEL_MUX_CFG_ADDR 0x0050
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#define CHN1_PHASE3_3_MTR_SEL_MUX_OFFSET 25
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#define CHN1_PHASE3_3_MTR_SEL_MUX_MASK 0x0E000000
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#define CHN1_PHASE3_2_MTR_SEL_MUX_OFFSET 22
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#define CHN1_PHASE3_2_MTR_SEL_MUX_MASK 0x01C00000
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#define CHN1_PHASE3_1_MTR_SEL_MUX_OFFSET 19
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#define CHN1_PHASE3_1_MTR_SEL_MUX_MASK 0x00380000
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#define CHN1_PHASE3_0_MTR_SEL_MUX_OFFSET 16
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#define CHN1_PHASE3_0_MTR_SEL_MUX_MASK 0x00070000
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#define CHN1_PHASE2_MTR_SEL_MUX_OFFSET 6
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#define CHN1_PHASE2_MTR_SEL_MUX_MASK 0x000001C0
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#define CHN1_PHASE1_MTR_SEL_MUX_OFFSET 3
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#define CHN1_PHASE1_MTR_SEL_MUX_MASK 0x00000038
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#define CHN1_PHASE0_MTR_SEL_MUX_OFFSET 0
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#define CHN1_PHASE0_MTR_SEL_MUX_MASK 0x00000007
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//-----------------------------------
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#define CFG_SADC0_VCM_CH1_SEL_MUX_ADDR 0x0054
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#define CHN1_PHASE3_3_SEL_VCM_OFFSET 19
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#define CHN1_PHASE3_3_SEL_VCM_MASK 0x00080000
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#define CHN1_PHASE3_2_SEL_VCM_OFFSET 18
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#define CHN1_PHASE3_2_SEL_VCM_MASK 0x00040000
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#define CHN1_PHASE3_1_SEL_VCM_OFFSET 17
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#define CHN1_PHASE3_1_SEL_VCM_MASK 0x00020000
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#define CHN1_PHASE3_0_SEL_VCM_OFFSET 16
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#define CHN1_PHASE3_0_SEL_VCM_MASK 0x00010000
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#define CHN1_PHASE2_SEL_VCM_OFFSET 2
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#define CHN1_PHASE2_SEL_VCM_MASK 0x00000004
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#define CHN1_PHASE1_SEL_VCM_OFFSET 1
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#define CHN1_PHASE1_SEL_VCM_MASK 0x00000002
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#define CHN1_PHASE0_SEL_VCM_OFFSET 0
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#define CHN1_PHASE0_SEL_VCM_MASK 0x00000001
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//-----------------------------------
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#define CFG_SADC0_RST_CH1_ADDR 0x0058
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#define CHN1_PHASE3_3_RST_OFFSET 19
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#define CHN1_PHASE3_3_RST_MASK 0x00080000
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#define CHN1_PHASE3_2_RST_OFFSET 18
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#define CHN1_PHASE3_2_RST_MASK 0x00040000
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#define CHN1_PHASE3_1_RST_OFFSET 17
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#define CHN1_PHASE3_1_RST_MASK 0x00020000
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#define CHN1_PHASE3_0_RST_OFFSET 16
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#define CHN1_PHASE3_0_RST_MASK 0x00010000
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#define CHN1_PHASE2_RST_OFFSET 2
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#define CHN1_PHASE2_RST_MASK 0x00000004
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#define CHN1_PHASE1_RST_OFFSET 1
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#define CHN1_PHASE1_RST_MASK 0x00000002
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#define CHN1_PHASE0_RST_OFFSET 0
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#define CHN1_PHASE0_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_SADC0_IFRED_CH1_EN_ADDR 0x005C
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#define CHN1_PHASE3_3_TSW_IFRED_EN_OFFSET 19
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#define CHN1_PHASE3_3_TSW_IFRED_EN_MASK 0x00080000
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#define CHN1_PHASE3_2_TSW_IFRED_EN_OFFSET 18
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#define CHN1_PHASE3_2_TSW_IFRED_EN_MASK 0x00040000
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#define CHN1_PHASE3_1_TSW_IFRED_EN_OFFSET 17
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#define CHN1_PHASE3_1_TSW_IFRED_EN_MASK 0x00020000
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#define CHN1_PHASE3_0_TSW_IFRED_EN_OFFSET 16
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#define CHN1_PHASE3_0_TSW_IFRED_EN_MASK 0x00010000
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#define CHN1_PHASE2_TSW_IFRED_EN_OFFSET 2
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#define CHN1_PHASE2_TSW_IFRED_EN_MASK 0x00000004
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#define CHN1_PHASE1_TSW_IFRED_EN_OFFSET 1
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#define CHN1_PHASE1_TSW_IFRED_EN_MASK 0x00000002
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#define CHN1_PHASE0_TSW_IFRED_EN_OFFSET 0
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#define CHN1_PHASE0_TSW_IFRED_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_SADC0_MTR2PAD_EN_ADDR 0x0060
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#define CHN1_PHASE3_3_TSW_MTR2PAD_EN_OFFSET 19
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#define CHN1_PHASE3_3_TSW_MTR2PAD_EN_MASK 0x00080000
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#define CHN1_PHASE3_2_TSW_MTR2PAD_EN_OFFSET 18
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#define CHN1_PHASE3_2_TSW_MTR2PAD_EN_MASK 0x00040000
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#define CHN1_PHASE3_1_TSW_MTR2PAD_EN_OFFSET 17
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#define CHN1_PHASE3_1_TSW_MTR2PAD_EN_MASK 0x00020000
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#define CHN1_PHASE3_0_TSW_MTR2PAD_EN_OFFSET 16
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#define CHN1_PHASE3_0_TSW_MTR2PAD_EN_MASK 0x00010000
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#define CHN1_PHASE2_TSW_MTR2PAD_EN_OFFSET 2
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#define CHN1_PHASE2_TSW_MTR2PAD_EN_MASK 0x00000004
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#define CHN1_PHASE1_TSW_MTR2PAD_EN_OFFSET 1
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#define CHN1_PHASE1_TSW_MTR2PAD_EN_MASK 0x00000002
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#define CHN1_PHASE0_TSW_MTR2PAD_EN_OFFSET 0
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#define CHN1_PHASE0_TSW_MTR2PAD_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_SADC0_MTR2PAD_EN_NEG_ADDR 0x0064
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#define CHN1_PHASE3_3_TSW_MTR2PAD_EN_NEG_OFFSET 19
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#define CHN1_PHASE3_3_TSW_MTR2PAD_EN_NEG_MASK 0x00080000
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#define CHN1_PHASE3_2_TSW_MTR2PAD_EN_NEG_OFFSET 18
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#define CHN1_PHASE3_2_TSW_MTR2PAD_EN_NEG_MASK 0x00040000
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#define CHN1_PHASE3_1_TSW_MTR2PAD_EN_NEG_OFFSET 17
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#define CHN1_PHASE3_1_TSW_MTR2PAD_EN_NEG_MASK 0x00020000
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#define CHN1_PHASE3_0_TSW_MTR2PAD_EN_NEG_OFFSET 16
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#define CHN1_PHASE3_0_TSW_MTR2PAD_EN_NEG_MASK 0x00010000
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#define CHN1_PHASE2_TSW_MTR2PAD_EN_NEG_OFFSET 2
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#define CHN1_PHASE2_TSW_MTR2PAD_EN_NEG_MASK 0x00000004
|
|
#define CHN1_PHASE1_TSW_MTR2PAD_EN_NEG_OFFSET 1
|
|
#define CHN1_PHASE1_TSW_MTR2PAD_EN_NEG_MASK 0x00000002
|
|
#define CHN1_PHASE0_TSW_MTR2PAD_EN_NEG_OFFSET 0
|
|
#define CHN1_PHASE0_TSW_MTR2PAD_EN_NEG_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_MTR3PAD_EN_ADDR 0x0068
|
|
#define CHN1_PHASE3_3_TSW_MTR3PAD_EN_OFFSET 19
|
|
#define CHN1_PHASE3_3_TSW_MTR3PAD_EN_MASK 0x00080000
|
|
#define CHN1_PHASE3_2_TSW_MTR3PAD_EN_OFFSET 18
|
|
#define CHN1_PHASE3_2_TSW_MTR3PAD_EN_MASK 0x00040000
|
|
#define CHN1_PHASE3_1_TSW_MTR3PAD_EN_OFFSET 17
|
|
#define CHN1_PHASE3_1_TSW_MTR3PAD_EN_MASK 0x00020000
|
|
#define CHN1_PHASE3_0_TSW_MTR3PAD_EN_OFFSET 16
|
|
#define CHN1_PHASE3_0_TSW_MTR3PAD_EN_MASK 0x00010000
|
|
#define CHN1_PHASE2_TSW_MTR3PAD_EN_OFFSET 2
|
|
#define CHN1_PHASE2_TSW_MTR3PAD_EN_MASK 0x00000004
|
|
#define CHN1_PHASE1_TSW_MTR3PAD_EN_OFFSET 1
|
|
#define CHN1_PHASE1_TSW_MTR3PAD_EN_MASK 0x00000002
|
|
#define CHN1_PHASE0_TSW_MTR3PAD_EN_OFFSET 0
|
|
#define CHN1_PHASE0_TSW_MTR3PAD_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_ATB2PAD_EN_ADDR 0x006C
|
|
#define CHN1_PHASE3_3_TSW_ATB2PAD_EN_OFFSET 19
|
|
#define CHN1_PHASE3_3_TSW_ATB2PAD_EN_MASK 0x00080000
|
|
#define CHN1_PHASE3_2_TSW_ATB2PAD_EN_OFFSET 18
|
|
#define CHN1_PHASE3_2_TSW_ATB2PAD_EN_MASK 0x00040000
|
|
#define CHN1_PHASE3_1_TSW_ATB2PAD_EN_OFFSET 17
|
|
#define CHN1_PHASE3_1_TSW_ATB2PAD_EN_MASK 0x00020000
|
|
#define CHN1_PHASE3_0_TSW_ATB2PAD_EN_OFFSET 16
|
|
#define CHN1_PHASE3_0_TSW_ATB2PAD_EN_MASK 0x00010000
|
|
#define CHN1_PHASE2_TSW_ATB2PAD_EN_OFFSET 2
|
|
#define CHN1_PHASE2_TSW_ATB2PAD_EN_MASK 0x00000004
|
|
#define CHN1_PHASE1_TSW_ATB2PAD_EN_OFFSET 1
|
|
#define CHN1_PHASE1_TSW_ATB2PAD_EN_MASK 0x00000002
|
|
#define CHN1_PHASE0_TSW_ATB2PAD_EN_OFFSET 0
|
|
#define CHN1_PHASE0_TSW_ATB2PAD_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_SCLR_CTRL_ADDR 0x0070
|
|
#define CHN1_PHASE3_3_SCLR_CTRL_OFFSET 22
|
|
#define CHN1_PHASE3_3_SCLR_CTRL_MASK 0x00C00000
|
|
#define CHN1_PHASE3_2_SCLR_CTRL_OFFSET 20
|
|
#define CHN1_PHASE3_2_SCLR_CTRL_MASK 0x00300000
|
|
#define CHN1_PHASE3_1_SCLR_CTRL_OFFSET 18
|
|
#define CHN1_PHASE3_1_SCLR_CTRL_MASK 0x000C0000
|
|
#define CHN1_PHASE3_0_SCLR_CTRL_OFFSET 16
|
|
#define CHN1_PHASE3_0_SCLR_CTRL_MASK 0x00030000
|
|
#define CHN1_PHASE2_SCLR_CTRL_OFFSET 4
|
|
#define CHN1_PHASE2_SCLR_CTRL_MASK 0x00000030
|
|
#define CHN1_PHASE1_SCLR_CTRL_OFFSET 2
|
|
#define CHN1_PHASE1_SCLR_CTRL_MASK 0x0000000C
|
|
#define CHN1_PHASE0_SCLR_CTRL_OFFSET 0
|
|
#define CHN1_PHASE0_SCLR_CTRL_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_SUB_DC_THRS_ADDR 0x0074
|
|
#define CHN1_PHASE3_3_DC_EN_OFFSET 24
|
|
#define CHN1_PHASE3_3_DC_EN_MASK 0x01000000
|
|
#define CHN1_PHASE3_3_DC_THRS_OFFSET 0
|
|
#define CHN1_PHASE3_3_DC_THRS_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_DBG_BUS0_ADDR 0x0078
|
|
#define CHN1_SIG_DBG_BUS_OFFSET 0
|
|
#define CHN1_SIG_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_TSW_SENS_ADDR 0x007C
|
|
#define CHN1_PHASE3_3_TSW_SENS_OFFSET 19
|
|
#define CHN1_PHASE3_3_TSW_SENS_MASK 0x00080000
|
|
#define CHN1_PHASE3_2_TSW_SENS_OFFSET 18
|
|
#define CHN1_PHASE3_2_TSW_SENS_MASK 0x00040000
|
|
#define CHN1_PHASE3_1_TSW_SENS_OFFSET 17
|
|
#define CHN1_PHASE3_1_TSW_SENS_MASK 0x00020000
|
|
#define CHN1_PHASE3_0_TSW_SENS_OFFSET 16
|
|
#define CHN1_PHASE3_0_TSW_SENS_MASK 0x00010000
|
|
#define CHN1_PHASE2_TSW_SENS_OFFSET 2
|
|
#define CHN1_PHASE2_TSW_SENS_MASK 0x00000004
|
|
#define CHN1_PHASE1_TSW_SENS_OFFSET 1
|
|
#define CHN1_PHASE1_TSW_SENS_MASK 0x00000002
|
|
#define CHN1_PHASE0_TSW_SENS_OFFSET 0
|
|
#define CHN1_PHASE0_TSW_SENS_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_TSW_PD_PGA_ADDR 0x0080
|
|
#define CHN1_PHASE3_3_TSW_PD_PGA_OFFSET 19
|
|
#define CHN1_PHASE3_3_TSW_PD_PGA_MASK 0x00080000
|
|
#define CHN1_PHASE3_2_TSW_PD_PGA_OFFSET 18
|
|
#define CHN1_PHASE3_2_TSW_PD_PGA_MASK 0x00040000
|
|
#define CHN1_PHASE3_1_TSW_PD_PGA_OFFSET 17
|
|
#define CHN1_PHASE3_1_TSW_PD_PGA_MASK 0x00020000
|
|
#define CHN1_PHASE3_0_TSW_PD_PGA_OFFSET 16
|
|
#define CHN1_PHASE3_0_TSW_PD_PGA_MASK 0x00010000
|
|
#define CHN1_PHASE2_TSW_PD_PGA_OFFSET 2
|
|
#define CHN1_PHASE2_TSW_PD_PGA_MASK 0x00000004
|
|
#define CHN1_PHASE1_TSW_PD_PGA_OFFSET 1
|
|
#define CHN1_PHASE1_TSW_PD_PGA_MASK 0x00000002
|
|
#define CHN1_PHASE0_TSW_PD_PGA_OFFSET 0
|
|
#define CHN1_PHASE0_TSW_PD_PGA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_TSW_METER_PGA_GAIN_ADDR 0x0084
|
|
#define CHN1_PHASE3_3_TSW_METER_PGA_GAIN_OFFSET 25
|
|
#define CHN1_PHASE3_3_TSW_METER_PGA_GAIN_MASK 0x0E000000
|
|
#define CHN1_PHASE3_2_TSW_METER_PGA_GAIN_OFFSET 22
|
|
#define CHN1_PHASE3_2_TSW_METER_PGA_GAIN_MASK 0x01C00000
|
|
#define CHN1_PHASE3_1_TSW_METER_PGA_GAIN_OFFSET 19
|
|
#define CHN1_PHASE3_1_TSW_METER_PGA_GAIN_MASK 0x00380000
|
|
#define CHN1_PHASE3_0_TSW_METER_PGA_GAIN_OFFSET 16
|
|
#define CHN1_PHASE3_0_TSW_METER_PGA_GAIN_MASK 0x00070000
|
|
#define CHN1_PHASE2_TSW_METER_PGA_GAIN_OFFSET 6
|
|
#define CHN1_PHASE2_TSW_METER_PGA_GAIN_MASK 0x000001C0
|
|
#define CHN1_PHASE1_TSW_METER_PGA_GAIN_OFFSET 3
|
|
#define CHN1_PHASE1_TSW_METER_PGA_GAIN_MASK 0x00000038
|
|
#define CHN1_PHASE0_TSW_METER_PGA_GAIN_OFFSET 0
|
|
#define CHN1_PHASE0_TSW_METER_PGA_GAIN_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_INT_RAW_ADDR 0x0100
|
|
#define ADC0_FIFO_FULL_INT_RAW_OFFSET 8
|
|
#define ADC0_FIFO_FULL_INT_RAW_MASK 0x00000100
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_RAW_OFFSET 6
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_RAW_MASK 0x00000040
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_RAW_OFFSET 5
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_RAW_MASK 0x00000020
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_RAW_OFFSET 4
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_RAW_MASK 0x00000010
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_RAW_OFFSET 3
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_RAW_MASK 0x00000008
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_RAW_OFFSET 2
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_RAW_MASK 0x00000004
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_RAW_OFFSET 1
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_RAW_MASK 0x00000002
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_RAW_OFFSET 0
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_RAW_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_INT_ST_ADDR 0x0104
|
|
#define ADC0_FIFO_FULL_INT_ST_OFFSET 8
|
|
#define ADC0_FIFO_FULL_INT_ST_MASK 0x00000100
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_ST_OFFSET 6
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_ST_MASK 0x00000040
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_ST_OFFSET 5
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_ST_MASK 0x00000020
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_ST_OFFSET 4
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_ST_MASK 0x00000010
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_ST_OFFSET 3
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_ST_MASK 0x00000008
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_ST_OFFSET 2
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_ST_MASK 0x00000004
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_ST_OFFSET 1
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_ST_MASK 0x00000002
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_ST_OFFSET 0
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_ST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_INT_ENA_ADDR 0x0108
|
|
#define ADC0_FIFO_FULL_INT_ENA_OFFSET 8
|
|
#define ADC0_FIFO_FULL_INT_ENA_MASK 0x00000100
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_ENA_OFFSET 6
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_ENA_MASK 0x00000040
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_ENA_OFFSET 5
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_ENA_MASK 0x00000020
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_ENA_OFFSET 4
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_ENA_MASK 0x00000010
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_ENA_OFFSET 3
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_ENA_MASK 0x00000008
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_ENA_OFFSET 2
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_ENA_MASK 0x00000004
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_ENA_OFFSET 1
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_ENA_MASK 0x00000002
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_ENA_OFFSET 0
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_INT_CLR_ADDR 0x010C
|
|
#define ADC0_FIFO_FULL_INT_CLR_OFFSET 8
|
|
#define ADC0_FIFO_FULL_INT_CLR_MASK 0x00000100
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_CLR_OFFSET 6
|
|
#define ADC0_PHASE3_3_EXCEED_THRS_INT_CLR_MASK 0x00000040
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_CLR_OFFSET 5
|
|
#define ADC0_PHASE3_2_EXCEED_THRS_INT_CLR_MASK 0x00000020
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_CLR_OFFSET 4
|
|
#define ADC0_PHASE3_1_EXCEED_THRS_INT_CLR_MASK 0x00000010
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_CLR_OFFSET 3
|
|
#define ADC0_PHASE3_0_EXCEED_THRS_INT_CLR_MASK 0x00000008
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_CLR_OFFSET 2
|
|
#define ADC0_PHASE2_EXCEED_THRS_INT_CLR_MASK 0x00000004
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_CLR_OFFSET 1
|
|
#define ADC0_PHASE1_EXCEED_THRS_INT_CLR_MASK 0x00000002
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_CLR_OFFSET 0
|
|
#define ADC0_PHASE0_EXCEED_THRS_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_PHASE_EXTHRS_SEL_ADDR 0x0110
|
|
#define SADC0_PHASE3_3_EXTHRS_SEL_OFFSET 6
|
|
#define SADC0_PHASE3_3_EXTHRS_SEL_MASK 0x00000040
|
|
#define SADC0_PHASE3_2_EXTHRS_SEL_OFFSET 5
|
|
#define SADC0_PHASE3_2_EXTHRS_SEL_MASK 0x00000020
|
|
#define SADC0_PHASE3_1_EXTHRS_SEL_OFFSET 4
|
|
#define SADC0_PHASE3_1_EXTHRS_SEL_MASK 0x00000010
|
|
#define SADC0_PHASE3_0_EXTHRS_SEL_OFFSET 3
|
|
#define SADC0_PHASE3_0_EXTHRS_SEL_MASK 0x00000008
|
|
#define SADC0_PHASE2_EXTHRS_SEL_OFFSET 2
|
|
#define SADC0_PHASE2_EXTHRS_SEL_MASK 0x00000004
|
|
#define SADC0_PHASE1_EXTHRS_SEL_OFFSET 1
|
|
#define SADC0_PHASE1_EXTHRS_SEL_MASK 0x00000002
|
|
#define SADC0_PHASE0_EXTHRS_SEL_OFFSET 0
|
|
#define SADC0_PHASE0_EXTHRS_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_PHASE_DMA_OUT_CFG_ADDR 0x0114
|
|
#define SADC0_PHASE3_3_DMA_OUT_EB_OFFSET 6
|
|
#define SADC0_PHASE3_3_DMA_OUT_EB_MASK 0x00000040
|
|
#define SADC0_PHASE3_2_DMA_OUT_EB_OFFSET 5
|
|
#define SADC0_PHASE3_2_DMA_OUT_EB_MASK 0x00000020
|
|
#define SADC0_PHASE3_1_DMA_OUT_EB_OFFSET 4
|
|
#define SADC0_PHASE3_1_DMA_OUT_EB_MASK 0x00000010
|
|
#define SADC0_PHASE3_0_DMA_OUT_EB_OFFSET 3
|
|
#define SADC0_PHASE3_0_DMA_OUT_EB_MASK 0x00000008
|
|
#define SADC0_PHASE2_DMA_OUT_EB_OFFSET 2
|
|
#define SADC0_PHASE2_DMA_OUT_EB_MASK 0x00000004
|
|
#define SADC0_PHASE1_DMA_OUT_EB_OFFSET 1
|
|
#define SADC0_PHASE1_DMA_OUT_EB_MASK 0x00000002
|
|
#define SADC0_PHASE0_DMA_OUT_EB_OFFSET 0
|
|
#define SADC0_PHASE0_DMA_OUT_EB_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_CHN_CFG1_ADDR 0x0118
|
|
#define SADC0_SINC5_SHIFT_NUM_OFFSET 3
|
|
#define SADC0_SINC5_SHIFT_NUM_MASK 0x000000F8
|
|
#define CHN1_PHASE_MODE_OFFSET 0
|
|
#define CHN1_PHASE_MODE_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC0_DBG_CFG_ADDR 0x0140
|
|
#define SADC0_DBG_SEL_OFFSET 1
|
|
#define SADC0_DBG_SEL_MASK 0x00000006
|
|
#define SADC0_DBG_MODE_OFFSET 0
|
|
#define SADC0_DBG_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SADC_COMMON_CFG_ADDR 0x0180
|
|
#define SADC_SOFT_START_OFFSET 0
|
|
#define SADC_SOFT_START_MASK 0x00000001
|
|
|
|
//HW module read/write macro
|
|
#define SADC0_READ_REG(addr) SOC_READ_REG(SADC0_BASEADDR + addr)
|
|
#define SADC0_WRITE_REG(addr,value) SOC_WRITE_REG(SADC0_BASEADDR + addr,value)
|